CN111835373A - Novel SWP interface circuit - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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Abstract
The invention provides a novel SWP interface circuit, which comprises an electrostatic protection circuit, a receiving circuit and a transmitting circuit, wherein the electrostatic protection circuit is connected with the receiving circuit, and the receiving circuit is connected with the transmitting circuit; in this novel SWP interface circuit, introduce fifth NMOS transistor, sixth NMOS transistor and second amplifier for the source-drain voltage of third NMOS transistor is the same with the fourth NMOS transistor, and the effectual mismatch that has reduced third NMOS transistor and fourth NMOS transistor mirror current reduces novel SWP interface circuit's static consumption effectively, and this novel SWP interface circuit simple structure, easily integration, output voltage is stable.
Description
Technical Field
The invention relates to the technical field of integrated circuits of SIM card technology, in particular to a novel SWP interface circuit.
Background
The SWP SIM card is a security chip with a new specification, the card number and the password are stored in the SIM card, and point-to-point communication is realized with CLF (master device) through an SWP interface on the SIM card. As shown in fig. 1, the SWP interface is a single line for implementing full duplex communication, i.e., a digital modulation signal S1 in a voltage domain and a digital modulation signal S2 in a current domain, and the SWP interface is a key circuit for implementing point-to-point communication between the SWP SIM card and the CLF terminal (non-front end), and its performance is directly related to how well the SIM card communicates with the CLF terminal.
In recent years, a mobile phone is no longer a simple communication tool, and becomes a reliable mobile payment tool, and plays an irreplaceable role in the fields of shopping, transportation, banks and the like, so that the design and research of a high-quality and low-cost SWP circuit have very important significance.
Referring to fig. 2, a conventional SWP interface circuit structure is shown, and the working principle is as follows: the SIM SWP interface on the SWP SIM card is a slave interface, the CLF SWP interface on the CLF end is a master interface, the CLF SWP interface sends a digital pulse modulation signal S1, the high level duration time 0.75T is logic '1', the high level duration time 0.25T is logic '0', wherein 'T' is 1bit cycle time. The SIM SWP interface sends a current modulation signal S2, which is logic '1' when the current 600 uA-1000 uA is drawn from the CLF terminal, and logic '0' when the current-20 uA-0 uA is drawn from the CLF terminal. When the CLF terminal sends the S1 signal at a high level, the SWP SIM card transmits the S2 signal by means of a pull-up current or a pull-off current, i.e., data is transmitted in a full duplex mode.
The SWPI is an input/output port of an SWP interface circuit of the SWP SIM card, the first diode D1 and the second diode D2 are an electrostatic protection circuit of the SWP interface, an input signal of the SWP interface circuit passes through a low-pass filter formed by the first resistor R1 and the first capacitor C1, is shaped by the first-stage Schmitt trigger ST, and then passes through two-stage buffers of the first inverter INV1 and the second inverter INV2 to output a digital signal. Meanwhile, when the SWP SIM card receives the digital modulation signal S1 in the voltage domain as a high level signal, the SWP interface circuit transfers the digital modulation signal S2 in the current domain by means of the pull-down transistor fourth NMOS transistor NM4 or the switching transistor fifth NMOS 5, when the digital modulation signal S2 in the current domain is at a high level, the fifth NMOS transistor NM5 is turned on, the pull-down current of the fourth NMOS transistor NM4 is in a range of 600uA to 1000uA, and when S2 is at a low level, the fifth NMOS transistor NM5 is turned off, the fourth NMOS transistor NM4 is turned on, and the pull-down current is in a range of-20 uA to 0 uA. The key circuit of the SWP SIM card is a transmitting circuit, and the transmitting circuit is a current amplifying circuit composed of a reference current IREF, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first PMOS transistor PM1, and a second PMOS transistor PM 2.
However, the SWP interface circuit of the SWP SIM card has some disadvantages:
1. in the SWP interface circuit, the reference current IREF is relatively small, and is usually below 1uA, so that the amplification factor of the current amplification circuit is 600 times to 1000 times, and the current amplifier is easily mismatched, which causes the pull-down current of the fourth NMOS transistor NM4 to be too small or too large, and does not meet the requirements of the SWP protocol.
2. When the digital modulation signal S2 in the current domain is at a low level, the 80uA current in the second PMOS transistor PM2 flows away from the fifth NMOS transistor NM5, which is not favorable for low power circuit design.
Disclosure of Invention
In view of the above-mentioned deficiencies in the prior art, the present invention provides a novel SWP interface circuit, which comprises an electrostatic protection circuit, a receiving circuit and a transmitting circuit, and has the characteristics of simple structure, easy integration and stable output voltage.
In order to achieve the technical purpose, the technical scheme adopted by the invention is as follows:
a novel SWP interface circuit comprises an electrostatic protection circuit, a receiving circuit and a transmitting circuit;
the electrostatic protection circuit comprises a first diode and a second diode; the anode of the first diode is connected with the input and output end of the SWP interface circuit, the cathode of the first diode is connected with a power supply end VDD, the cathode of the second diode is connected with the input and output end of the SWP interface circuit, and the anode of the second diode is connected with a ground end VSS;
the receiving circuit includes a first capacitor, a first resistor, a first schmitt trigger, a first inverter, and a second inverter; one end of the first resistor is connected with the input and output end of the SWP interface circuit, the other end of the first resistor and one end of the first resistor are connected with the input end of the first Schmitt trigger, the other end of the first capacitor is connected with the ground terminal VSS, the output end of the first Schmitt trigger is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is the output end of the SWP interface circuit, the power supply end of the first Schmitt trigger, the power supply end of the first inverter and the power supply end of the second inverter are connected with the power supply end VDD, and the ground end of the first Schmitt trigger, the ground end of the first inverter and the ground end of the second inverter are connected with the ground terminal VSS;
the transmitting circuit comprises a first reference current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first amplifier, a second amplifier and a third inverter; one end of a first reference current source is connected with a power supply end VDD, the other end of the first reference current source, the gate end and the drain end of a first NMOS transistor are connected with the positive input end of a first amplifier, the negative input end of the first amplifier, the gate end and the drain end of a second NMOS transistor are connected with the drain end of a first PMOS transistor, the gate end, the drain end of a second PMOS transistor, the gate end and the drain end of a second PMOS transistor are connected with the drain end of a fifth NMOS transistor, the gate end of the fifth NMOS transistor and the gate end of a sixth NMOS transistor are connected with the output end of a second amplifier, the source end of the fifth NMOS transistor and the positive input end of the second amplifier are connected with the drain end of a third NMOS transistor, the gate end of the third NMOS transistor, the output end of the first amplifier and the gate end of the fourth NMOS transistor are connected with the drain end of a seventh NMOS transistor, the drain end of the fourth NMOS transistor and the negative input end of the second amplifier are connected with the drain end of the sixth NMOS transistor, the drain terminal of the sixth NMOS transistor is connected with the input-output terminal, the gate terminal of the seventh NMOS transistor is connected with the output terminal of the third inverter, the input terminal of the third inverter is connected with the digital modulation signal of the current domain, the source terminal and the substrate of the first NMOS transistor, the source terminal and the substrate of the seventh NMOS transistor, the source terminal and the substrate of the third NMOS transistor, the source terminal and the substrate of the fourth NMOS transistor, the substrate of the fifth NMOS transistor, the substrate of the sixth NMOS transistor, the ground terminal of the first amplifier, the ground terminal of the second amplifier, and the ground terminal of the third inverter are connected with a ground terminal VSS, and the source terminal and the substrate of the first PMOS transistor, the source terminal and the substrate of the second PMOS transistor, the power terminal of the first amplifier, the power terminal of the second amplifier, and the power terminal of the third inverter are connected with a power terminal VDD.
Due to the adoption of the structure, compared with the prior art, the invention has the following advantages:
(1) in the novel SWP interface circuit, the fifth NMOS transistor, the sixth NMOS transistor and the second amplifier are introduced, so that the source-drain voltages of the third NMOS transistor and the fourth NMOS transistor are the same, and the mismatch of mirror currents of the third NMOS transistor and the fourth NMOS transistor is effectively reduced;
(2) in the novel SWP interface circuit, the first NMOS transistor, the second NMOS transistor and the first amplifier are introduced, so that the current of the third NMOS transistor is exactly 80 times of the reference current IREF, and mismatching is not easy to occur;
(3) in the novel SWP interface circuit, the fifth NMOS transistor and the sixth NMOS transistor are introduced, so that the static power consumption of the novel SWP interface circuit is effectively reduced;
(4) the novel SWP interface circuit has the advantages of simple structure, easy integration and stable output voltage.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a block diagram of a data transmission for an SWP interface circuit;
FIG. 2 is a SWP circuit structure diagram of a conventional SWP SIM card;
fig. 3 is a circuit diagram of the novel SWP interface according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 3 is a circuit diagram of the novel SWP interface according to the embodiment of the present invention. The novel SWP interface circuit includes an electrostatic protection circuit 101, a receiving circuit 102, and a transmitting circuit 103.
The electrostatic protection circuit 101 comprises a first diode D1 and a second diode D2; the anode of the first diode D1 is connected to the input/output end SWPI of the SWP interface circuit, the cathode of the first diode D1 is connected to the power supply terminal VDD, the cathode of the second diode D2 is connected to the input/output end SWPI of the SWP interface circuit, and the anode of the second diode D2 is connected to the ground terminal VSS.
The receiving circuit 102 includes a first capacitor C1, a first resistor R1, a first schmitt trigger ST, a first inverter INV1, and a second inverter INV 2; one end of the first resistor R1 is connected to the input/output end SWPI of the SWP interface circuit, the other end of the first resistor R1 and one end of the first resistor R1 are connected to the input end of the first schmitt trigger ST, the other end of the first capacitor C1 is connected to the ground terminal VSS, the output end of the first schmitt trigger ST is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is the output end SWPO of the SWP interface circuit, the power ends of the first schmitt trigger ST, the first inverter INV1 and the second inverter INV2 are connected to the power end VDD, and the ground end of the first schmitt trigger ST, the first inverter INV1 and the second inverter INV2 are connected to the ground terminal VSS.
The transmission circuit 103 includes a first reference current source IREF, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, a first PMOS transistor PM1, a second PMOS transistor PM2, a first amplifier AMP1, a second amplifier AMP2, and a third inverter INV 3; one end of the first reference current source IREF is connected to the power supply terminal VDD, the other end of the first reference current source IREF, the gate and drain of the first NMOS transistor NM1 are connected to the positive input terminal of the first amplifier AMP1, the negative input terminal of the first amplifier AMP1, the gate and drain of the second NMOS transistor NM2 are connected to the drain of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the gate and drain of the second PMOS transistor PM2 are connected to the drain of the fifth NMOS transistor NM5, the gate of the fifth NMOS transistor NM5, the gate of the sixth NMOS transistor NM6 are connected to the output terminal of the second amplifier AMP2, the source terminal of the fifth NMOS transistor NM5, the positive input terminal of the second amplifier AMP2 are connected to the drain of the third NMOS transistor NM3, the gate of the third NMOS transistor NM3, the output terminal of the first amplifier AMP1, the gate of the fourth NMOS transistor NM4 are connected to the drain of the seventh NMOS transistor NM7, a drain terminal of the fourth NMOS transistor NM4, a negative input terminal of the second amplifier AMP2 is connected to a source terminal of the sixth NMOS transistor NM6, a drain terminal of the sixth NMOS transistor NM6 is connected to the input/output terminal SWPI, a gate terminal of the seventh NMOS transistor NM7 is connected to an output terminal of the third inverter INV3, an input terminal of the third inverter INV3 is connected to the digital modulation signal S2 of the current domain, a source terminal and a substrate of the first NMOS transistor NM1, a source terminal and a substrate of the seventh NMOS transistor NM7, a source terminal and a substrate of the third NMOS transistor NM3, a source terminal and a substrate of the fourth NMOS transistor NM4, a substrate of the fifth NMOS transistor NM5, a substrate of the sixth NMOS transistor NM6, a ground terminal of the first amplifier AMP1, a ground terminal of the second amplifier 2, a ground terminal of the third inverter INV3 is connected to a ground terminal, a drain terminal and a source terminal of the first PMOS transistor PM1, a source terminal and a substrate of the second PMOS transistor NM2, a source terminal of the second amplifier AMP1, The power supply terminal of the second amplifier AMP2 and the power supply terminal of the third inverter INV3 are connected to the power supply terminal VDD.
Referring to fig. 3, the working process of the novel SWP interface circuit of the present invention is: when the SWP interface circuit works, an input/output end SWPI is an SWP input/output end of an SWP SIM card, a first diode D1 and a second diode D2 provide electrostatic protection for the SWP interface circuit, and an input signal of the SWP interface circuit passes through a low-pass filter consisting of a first resistor R1 and a first capacitor C1, is shaped by a first-stage Schmitt trigger ST, and then passes through two-stage buffers of a first inverter INV1 and a second inverter INV2 to output a digital signal; meanwhile, when the SWP interface circuit receives a high-level signal of the digital modulation signal S1 in the voltage domain, the SWP interface circuit transmits the digital modulation signal S2 in the current domain by means of the pull-down transistors fourth NMOS transistor NM4 and sixth NMOS transistor NM6 or the switching transistor seventh NMOS transistor NM7, when the digital modulation signal S2 in the current domain is at a high level, the seventh NMOS transistor NM7 is turned on, the pull-down currents of the fourth NMOS transistor NM4 and sixth NMOS transistor NM6 are in a range of 600uA to 1000uA, when the digital modulation signal S2 in the current domain is at a low level, the seventh NMOS transistor NM7 is turned off, the fourth NMOS transistor NM4 is turned on, and the pull-down currents are in a range of-20 uA to 0uA, thereby achieving stability of the SWP interface circuit.
As can be seen from the above, in the embodiment of the present invention, the electrostatic protection circuit 101, the receiving circuit 102, and the transmitting circuit 103 effectively improve the stability of the SWP interface circuit.
The above embodiments are merely illustrative of the basic idea of the present invention, and the constituent circuits related to the present invention are not drawn in terms of the number of constituent circuits, shapes, arrangement of devices, and connection modes in actual implementation. The actual implementation of the method can be changed freely according to the type, number, connection mode, device arrangement mode and device parameters of each circuit.
The above-mentioned embodiments are only preferred embodiments of the present invention, and do not limit the extension of the technical solution of the present invention. Any modifications, equivalent changes and obvious changes of the known technology made by the technical proposal of the invention by the technical personnel in the field are all within the protection scope of the invention.
Claims (1)
1. A novel SWP interface circuit is characterized by comprising an electrostatic protection circuit, a receiving circuit and a transmitting circuit;
the electrostatic protection circuit comprises a first diode and a second diode; the anode of the first diode is connected with the input and output end of the SWP interface circuit, the cathode of the first diode is connected with a power supply end VDD, the cathode of the second diode is connected with the input and output end of the SWP interface circuit, and the anode of the second diode is connected with a ground end VSS;
the receiving circuit includes a first capacitor, a first resistor, a first schmitt trigger, a first inverter, and a second inverter; one end of the first resistor is connected with the input and output end of the SWP interface circuit, the other end of the first resistor and one end of the first resistor are connected with the input end of the first Schmitt trigger, the other end of the first capacitor is connected with the ground terminal VSS, the output end of the first Schmitt trigger is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is the output end of the SWP interface circuit, the power supply end of the first Schmitt trigger, the power supply end of the first inverter and the power supply end of the second inverter are connected with the power supply end VDD, and the ground end of the first Schmitt trigger, the ground end of the first inverter and the ground end of the second inverter are connected with the ground terminal VSS;
the transmitting circuit comprises a first reference current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first amplifier, a second amplifier and a third inverter; one end of a first reference current source is connected with a power supply end VDD, the other end of the first reference current source, the gate end and the drain end of a first NMOS transistor are connected with the positive input end of a first amplifier, the negative input end of the first amplifier, the gate end and the drain end of a second NMOS transistor are connected with the drain end of a first PMOS transistor, the gate end, the drain end of a second PMOS transistor, the gate end and the drain end of a second PMOS transistor are connected with the drain end of a fifth NMOS transistor, the gate end of the fifth NMOS transistor and the gate end of a sixth NMOS transistor are connected with the output end of a second amplifier, the source end of the fifth NMOS transistor and the positive input end of the second amplifier are connected with the drain end of a third NMOS transistor, the gate end of the third NMOS transistor, the output end of the first amplifier and the gate end of the fourth NMOS transistor are connected with the drain end of a seventh NMOS transistor, the drain end of the fourth NMOS transistor and the negative input end of the second amplifier are connected with the drain end of the sixth NMOS transistor, the drain terminal of the sixth NMOS transistor is connected with the input-output terminal, the gate terminal of the seventh NMOS transistor is connected with the output terminal of the third inverter, the input terminal of the third inverter is connected with the digital modulation signal of the current domain, the source terminal and the substrate of the first NMOS transistor, the source terminal and the substrate of the seventh NMOS transistor, the source terminal and the substrate of the third NMOS transistor, the source terminal and the substrate of the fourth NMOS transistor, the substrate of the fifth NMOS transistor, the substrate of the sixth NMOS transistor, the ground terminal of the first amplifier, the ground terminal of the second amplifier, and the ground terminal of the third inverter are connected with a ground terminal VSS, and the source terminal and the substrate of the first PMOS transistor, the source terminal and the substrate of the second PMOS transistor, the power terminal of the first amplifier, the power terminal of the second amplifier, and the power terminal of the third inverter are connected with a power terminal VDD.
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| CN201911099040.5A CN111835373B (en) | 2019-11-18 | 2019-11-18 | Novel SWP interface circuit |
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| CN201911099040.5A CN111835373B (en) | 2019-11-18 | 2019-11-18 | Novel SWP interface circuit |
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Cited By (1)
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| CN112118004A (en) * | 2020-11-19 | 2020-12-22 | 四川科道芯国智能技术股份有限公司 | SWP interface circuit and terminal |
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| CN111835373B (en) | 2023-11-14 |
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