CN114978147B - Low-power consumption silicon dioxide insulated gate digital isolator based on edge detection - Google Patents
Low-power consumption silicon dioxide insulated gate digital isolator based on edge detection Download PDFInfo
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- CN114978147B CN114978147B CN202210919032.6A CN202210919032A CN114978147B CN 114978147 B CN114978147 B CN 114978147B CN 202210919032 A CN202210919032 A CN 202210919032A CN 114978147 B CN114978147 B CN 114978147B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the technical field of isolators, in particular to a low-power-consumption silicon dioxide insulated gate digital isolator based on edge detection. The invention greatly reduces the overall power consumption of the system, prolongs the standby time and expands the application of the digital isolator in a system with limited power consumption and thermal performance while ensuring the signal transmission quality.
Description
Technical Field
The invention relates to the technical field of isolators, in particular to a low-power-consumption silicon dioxide insulated gate digital isolator based on edge detection.
Background
The isolator is a device for signal transmission in an electrical isolation state, can effectively reduce interference among different circuits, and is widely applied to various electronic system devices such as industrial control, communication networks, automotive electronics, consumer electronics and the like. The existing isolator technology can ensure that two circuits in one system are kept independent, the safety of operators is guaranteed, and the damage to the circuits and equipment is avoided.
Fig. 7 is a conventional On-Off-Keying (OOK) modulation based silicon dioxide insulated gate digital isolator, and the overall architecture mainly consists of a high-frequency oscillator 10, an OOK modulator 11, a driver 12, a silicon dioxide insulated gate 20, an amplifier 31 and an OOK demodulator 32. The high frequency oscillator 10 continues to operate and consumes a large amount of current. When the input signal is high level, the OOK modulator 11 outputs a signal generated by the high frequency oscillator to the driver 12. The amplifier 31 receives the signal output by the driver 12 through the silicon dioxide insulated gate 20, amplifies the signal, and feeds the amplified signal to the OOK demodulator 32. The OOK demodulator 32 restores the amplified high frequency signal to a direct current level signal. The specific transmission waveform is shown in fig. 6.
In the application of digital isolation, the OOK modulation and demodulation technology is widely applied and has good reliability and stability. However, the high-frequency oscillator and the high-frequency amplifier which work continuously inevitably consume excessive current, resulting in excessive static power consumption (more than or equal to 1 mA), so that the application of the OOK modulation and demodulation technology in a system with limited power consumption and thermal performance represented by battery power supply is greatly limited.
Disclosure of Invention
The invention provides a low-power-consumption silicon dioxide insulated gate digital isolator based on edge detection, which is used for encoding the edge of an input signal by detecting the edge of the input signal, thereby greatly reducing the power consumption of a system while ensuring the isolation capability.
In order to realize the purpose of the invention, the adopted technical scheme is as follows: the low-power-consumption silicon dioxide insulated gate digital isolator based on edge detection comprises an input buffer, an encoder, a transmitter, a silicon dioxide insulated gate, a receiver, a decoder and an output driver, wherein an external signal enters the encoder through the input buffer, the encoder encodes an input signal, the encoder simultaneously detects the edge of the input signal, and if the rising edge of the input signal is detected, the encoder outputs two narrow pulse signals to the transmitter; if the falling edge of the input signal is detected, the encoder outputs a narrow pulse signal to the transmitter; according to the number of pulses output by the encoder, the transmitter sends a corresponding group number of high-frequency pulses to the receiver through the silicon dioxide insulated gate, the receiver shapes the received high-frequency pulses and sends the high-frequency pulses to the decoder, and if the decoder receives the two pulses, a high level is output to the output driver; if the decoder receives a pulse, outputting a low level to the output driver; the output driver buffers the output result of the decoder and drives the resistive load or the capacitive load.
As an optimization scheme of the invention, the low-power-consumption silicon dioxide insulated gate digital isolator based on the edge detection further comprises a first low dropout linear regulator LDO1, a second low dropout linear regulator LDO2 and a third low dropout linear regulator LDO3, wherein the first low dropout linear regulator LDO1 is used for supplying power to the encoder, the second low dropout linear regulator LDO2 is used for supplying power to the transmitter, and the third low dropout linear regulator LDO3 is used for supplying power to the receiver and the decoder respectively.
As an optimization scheme of the invention, the low-power-consumption silicon dioxide insulated gate digital isolator based on edge detection further comprises a refresher and a first oscillator, wherein the first oscillator is used for providing a reference clock for the refresher, the refresher is used for monitoring an input signal, and if the input signal is not overturned for a long time, the refresher drives an encoder to output a narrow pulse; if the signal is high level, the refresher drives the encoder to send two narrow pulses to the emitter; if the signal is low, the refresher drives the encoder to send a narrow pulse to the transmitter.
As an optimization scheme of the invention, the low-power-consumption silicon dioxide insulated gate digital isolator based on edge detection further comprises a watchdog timer and a second oscillator, wherein the second oscillator provides a reference clock for the watchdog timer, the watchdog timer is connected with a decoder and is used for monitoring an output signal of the receiver, and if the output signal is not overturned for a long time, the watchdog timer drives the decoder to output a default level.
As an optimized scheme of the invention, the silicon dioxide insulated gate comprises a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, wherein the first capacitor C1 and the second capacitor C2 are connected between the transmitter and the receiver in series, and the third capacitor C3 and the fourth capacitor C4 are connected between the transmitter and the receiver in series.
As an optimization scheme of the invention, the encoder adopts an asynchronous circuit to process the input signal, and completes the detection and encoding based on the edge while the input signal is overturned.
As an optimization scheme of the invention, the decoder adopts an asynchronous circuit to process the received pulse, completes decoding while receiving the pulse and outputs a corresponding level.
As an optimization scheme of the invention, the refresher, the first oscillator, the second oscillator and the watchdog timer can all realize lower static power consumption by closing chip pins.
The invention has the positive effects that: based on the OOK modulation and demodulation technology, the invention greatly reduces the overall power consumption of the system, prolongs the standby time and expands the application of the digital isolator in the system design with limited power consumption and thermal performance while ensuring the signal transmission quality.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
FIG. 1 is an overall schematic block diagram of the present invention;
FIG. 2 is a waveform diagram illustrating a signal transmission process according to the present invention;
FIG. 3 is a schematic diagram of the internal circuit structure of the encoder of the present invention;
FIG. 4 is a schematic diagram of the internal circuit structure of the receiver of the present invention;
FIG. 5 is a schematic diagram of the internal circuit structure of the output driver of the present invention;
fig. 6 is a waveform diagram of a conventional On-Off-keying modulated transmission process.
Fig. 7 is a schematic diagram of a conventional On-Off-Keying modulation structure.
Wherein: 100. input buffer, 101, encoder, 102, transmitter, 103, refresher, 104, first oscillator, 200, silicon dioxide insulated gate, 300, receiver, 301, decoder, 302, second oscillator, 303, output driver, 304, watchdog timer.
Detailed Description
As shown in fig. 1, the present invention discloses a low power consumption silicon dioxide insulated gate digital isolator based on edge detection, which includes an input buffer 100, an encoder 101, a transmitter 102, a silicon dioxide insulated gate 200, a receiver 300, a decoder 301 and an output driver 303, wherein an external signal enters the encoder 101 through the input buffer 100, the encoder 101 encodes an input signal, the encoder 101 simultaneously detects edges of the input signal, and if a rising edge of the input signal is detected, the encoder 101 outputs two narrow pulse signals to the transmitter 102; if the falling edge of the input signal is detected, the encoder 101 outputs a narrow pulse signal to the transmitter 102; according to the number of pulses output by the encoder 101, the transmitter 102 sends a corresponding group number of high-frequency pulses to the receiver 300 through the silicon dioxide insulated gate 200, the receiver 300 shapes the received high-frequency pulses and sends the shaped high-frequency pulses to the decoder 301, and if the decoder 301 receives two pulses, a high level is output to the output driver 303; if the decoder 301 receives a pulse, it outputs a low level to the output driver 303; the output driver 303 buffers the output result of the decoder 301 and drives the load. The waveform of the whole transmission process is shown in fig. 2.
The refresher 103 constantly monitors the dc state of the input signal. If the input signal is not inverted within the set time, there is no signal edge for the encoder 101 to detect, and the refresher 103 will detect the dc state of the current signal. If the signal is high, the refresher 103 drives the encoder 101 to send two pulses. If the signal is low, the refresher 103 drives the encoder 101 to send a pulse. After receiving the pulse signal, the decoder 301 maintains a corresponding dc state according to the number of pulses. If decoder 301 receives two pulses, decoder 301 remains high. If decoder 301 receives a pulse, decoder 301 remains low.
The low-power-consumption silicon dioxide insulated gate digital isolator based on the edge detection further comprises a first low-dropout linear regulator LDO1, a second low-dropout linear regulator LDO2 and a third low-dropout linear regulator LDO3, wherein the first low-dropout linear regulator LDO1 is used for supplying power to the encoder 101, the second low-dropout linear regulator LDO2 is used for supplying power to the transmitter 102, and the third low-dropout linear regulator LDO3 is used for respectively supplying power to the receiver 300 and the decoder 301.
The low-power-consumption silicon dioxide insulated gate digital isolator based on the edge detection further comprises a refresher 103 and a first oscillator 104, wherein the first oscillator 104 is used for providing a reference clock for the refresher 103. The refresher 103 monitors the input signal, and if the input signal is not inverted for a long time, the refresher 103 drives the encoder 101 to output a narrow pulse. If the signal is high, the refresher 103 drives the encoder 101 to send two narrow pulses to the transmitter 102. If the signal is low, the refresher 103 drives the encoder 101 to send a narrow pulse to the transmitter 102.
The low-power consumption silicon dioxide insulated gate digital isolator based on the edge detection further comprises a watchdog timer 304 and a second oscillator 302, the second oscillator 302 provides a reference clock for the watchdog timer 304, the watchdog timer 304 is connected with the decoder 301, the watchdog timer 304 is used for monitoring an output signal of the receiver 300, and if the output signal is not turned over for a long time, the watchdog timer 304 drives the decoder 301 to output a default level. The default level is high or low.
The silicon dioxide insulated gate 200 includes a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4, the first capacitor C1 and the second capacitor C2 are connected in series between the transmitter 102 and the receiver 300, and the third capacitor C3 and the fourth capacitor C4 are connected in series between the transmitter 102 and the receiver 300. The silicon dioxide insulated gate has the advantages of low cost, good voltage resistance, strong electromagnetic compatibility and easy compatibility of CMOS process. Through the series connection of the two silicon dioxide insulated gates, the multiplication of voltage resistance is realized, and the double protection effect is realized on the receiving and transmitting end.
As shown in fig. 3, the encoder 101 processes the input signal by using an asynchronous circuit, and completes the edge-based detection and encoding while the input signal is inverted. The encoder 101 consumes current only when the input signal is inverted, and has no static standby power consumption. In addition, unlike a synchronous encoding circuit based on clock edge triggering, the encoder 101 operating based on an asynchronous circuit can complete edge-based detection and encoding while the input signal is inverted, and does not need to refer to a clock signal, simplifying the circuit structure. The encoder 101 includes rising edge detection, falling edge detection, and rising or falling edge detection, and the detected signals are synthesized and output.
As shown in fig. 4, the receiver 300 includes a current source I, a first P-type fet PM1, a second P-type fet PM2, a first N-type fet NM1, a second N-type fet NM2, a third N-type fet NM3, a first resistor R1, a second resistor R2, a fifth capacitor C5, and a sixth capacitor C6, the fifth capacitor C5 is connected between the positive input terminal of the receiver 300 and the gate of the first N-type fet NM1, the drain of the first N-type fet NM1 is connected to the current source I and the drain of the first P-type fet PM1 respectively, the first resistor R1 and the second resistor R2 are connected in series between the grid of the first N-type field effect transistor NM1 and the grid of the second N-type field effect transistor NM2, the sixth capacitor C6 is connected between the grid of the second N-type field effect transistor NM2 and the negative input end of the receiver 300, the drain of the second N-type field effect transistor NM2 is connected with the drain of the first P-type field effect transistor PM1, the source of the second N-type field effect transistor NM2 is grounded, the source of the first P-type field effect transistor PM1 is connected with the source of the second P-type field effect transistor PM2, and the drain of the third N-type field effect transistor NM3 and the drain of the second P-type field effect transistor PM2 are both connected with the output end of the receiver 300.
As shown in fig. 5, the output driver 303 includes an and gate, a not gate, a PMOSFET power field effect transistor, and an NMOSFET power field effect transistor, where the load includes a resistive load C and a capacitive load R, the output end of the nand gate of the PMOSFET power field effect transistor is connected, the gate of the NMOSFET power field effect transistor is connected to the output end of the and gate, the drain of the PMOSFET power field effect transistor is connected to the drain of the NMOSFET power field effect transistor, the source of the PMOSFET power field effect transistor is connected to the power supply, and the NMOSFET power field effect transistor is grounded.
The decoder 301 processes the received pulse by using an asynchronous circuit, completes decoding while receiving the pulse, and outputs a corresponding level. Decoder 301 consumes current only at the time the pulse is received and there is no static standby power consumption. In addition, unlike a synchronous decoding circuit based on clock edge triggering, the decoder 301 operating based on an asynchronous circuit can complete decoding while receiving pulses and output a corresponding level without reference to a clock signal, a counter, a comparator, and the like, thereby simplifying the circuit structure.
The refresher 103, the first oscillator 104, the second oscillator 302, and the watchdog timer 304 may all achieve lower static power consumption through chip pin shut-down. Chip pin shut-down connects the chip pin to chip ground.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. Low-power consumption silica insulated gate digital isolator based on edge detection, its characterized in that: the device comprises an input buffer (100), an encoder (101), a transmitter (102), a silicon dioxide insulated gate (200), a receiver (300), a decoder (301) and an output driver (303), wherein an external signal enters the encoder (101) through the input buffer (100), the encoder (101) encodes the input signal, the encoder (101) simultaneously detects the edge of the input signal, and if the rising edge of the input signal is detected, the encoder (101) outputs two narrow pulse signals to the transmitter (102); if the falling edge of the input signal is detected, the encoder (101) outputs a narrow pulse signal to the transmitter (102); according to the number of pulses output by the encoder (101), the transmitter (102) sends a corresponding group number of high-frequency pulses to the receiver (300) through the silicon dioxide insulated gate (200), the receiver (300) shapes the received high-frequency pulses and sends the high-frequency pulses to the decoder (301), and if the decoder (301) receives two pulses, a high level is output to the output driver (303); outputting a low level to the output driver (303) if the decoder (301) receives a pulse; the output driver (303) buffers the output result of the decoder (301) and drives a resistive load or a capacitive load;
the encoder (101) comprises rising edge detection, falling edge detection and rising or falling edge detection, and detected signals are output after being synthesized;
the decoder (301) processes the received pulse by adopting an asynchronous circuit, completes decoding while receiving the pulse and outputs a corresponding level;
the silicon dioxide insulated gate (200) comprises a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4, wherein the first capacitor C1 and the second capacitor C2 are connected between the transmitter (102) and the receiver (300) in series, and the third capacitor C3 and the fourth capacitor C4 are connected between the transmitter (102) and the receiver (300) in series.
2. The edge-detection-based low-power silicon dioxide insulated gate digital isolator according to claim 1, characterized in that: the low-power-consumption silicon dioxide insulated gate digital isolator based on the edge detection further comprises a first low dropout linear regulator (LDO 1), a second low dropout linear regulator (LDO 2) and a third low dropout linear regulator (LDO 3), wherein the first low dropout linear regulator (LDO 1) is used for supplying power to the encoder (101), the second low dropout linear regulator (LDO 2) is used for supplying power to the transmitter (102), and the third low dropout linear regulator (LDO 3) is used for supplying power to the receiver (300) and the decoder (301) respectively.
3. The edge-detection-based low-power silicon dioxide insulated gate digital isolator according to claim 2, characterized in that: the low-power-consumption silicon dioxide insulated gate digital isolator based on the edge detection further comprises a refresher (103) and a first oscillator (104), wherein the first oscillator (104) is used for providing a reference clock for the refresher (103), the refresher (103) is used for monitoring an input signal, and if the input signal is not turned over for a long time, the refresher (103) drives an encoder (101) to output a narrow pulse; if the signal is high level, the refresher (103) drives the encoder (101) to send two narrow pulses to the transmitter (102); if the signal is low, the refresher (103) drives the encoder (101) to send a narrow pulse to the transmitter (102).
4. The edge-detection-based low-power silicon dioxide insulated gate digital isolator according to claim 3, characterized in that: the low-power-consumption silicon dioxide insulated gate digital isolator based on the edge detection further comprises a watchdog timer (304) and a second oscillator (302), the second oscillator (302) provides a reference clock for the watchdog timer (304), the watchdog timer (304) is connected with a decoder (301), the watchdog timer (304) is used for monitoring an output signal of a receiver (300), and if the output signal is not overturned for a long time, the watchdog timer (304) drives the decoder (301) to output a default level.
5. The edge detection-based low power consumption silicon dioxide insulated gate digital isolator according to any one of claims 1-4, characterized in that: the encoder (101) processes the input signal by using an asynchronous circuit, and completes edge-based detection and encoding while the input signal is inverted.
6. The edge-detection-based low-power silicon dioxide insulated gate digital isolator according to claim 5, characterized in that: the refresher (103), the first oscillator (104), the second oscillator (302), and the watchdog timer (304) may all be turned off by chip pins to achieve lower static power consumption.
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| CN105161488A (en) * | 2015-08-31 | 2015-12-16 | 中国科学院自动化研究所 | Magnetic coupling digital isolator and coding and decoding method thereof |
| CN112039517B (en) * | 2020-09-04 | 2024-03-22 | 上海川土微电子有限公司 | Ultra-low power consumption capacitive digital isolator circuit based on Pulse-Coding |
| CN111817709B (en) * | 2020-09-04 | 2020-12-15 | 上海川土微电子有限公司 | Digital isolator circuit based on Efficient-OOK and digital isolator |
| CN114142847A (en) * | 2021-12-02 | 2022-03-04 | 矽力杰半导体技术(杭州)有限公司 | Digital isolator and digital signal transmission method |
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