KR101084818B1 - Wake-up Circuit - Google Patents

Abstract

The present invention relates to a wake-up circuit, comprising: a rectifier for converting an RF signal into a DC signal; An overvoltage protection unit for blocking an overvoltage higher than a reference voltage among the voltages transmitted from the rectifier; And a detection unit operated by a signal transmitted from the overvoltage protection unit to detect a wakeup signal. The detection unit may reduce power consumption during the wakeup operation of the sensor system, improve battery life, and detect a wakeup signal. The efficiency can be increased, and the reception sensitivity of the wakeup signal can be improved.

Wakeup, passives, scheduling

Description

Wake-up Circuit

The present invention relates to a wake up circuit.

Ubiquitous sensor network (USN) is a wireless sensor network using sensor nodes equipped with sensors that can detect recognition information about objects or surrounding environment information, and is input through various sensor nodes. It refers to a network system that processes and manages information by connecting information to the outside through a network in real time.

USN ultimately aims to create an environment that can communicate anytime, anywhere, regardless of network, device or service by giving computing and communication capabilities to everything.

The general USN is composed of a sensor node including a sensor and a communication module that detects recognition information about an object or surrounding environment information in real time, a sensor field consisting of a set of sensor nodes, and receiving information collected from a sensor field. It may be configured to include a sink node, the gateway for routing the information transmitted from the sink node to transmit to the management server through a broadband communication network.

In the above-described configuration, the sink node may be connected to the gateway through an existing infrastructure such as satellite communication, wireless LAN, Bluetooth, and wired Internet.

These USNs can be used to detect and respond to disasters in the event of a disaster such as a fire, flood or earthquake.

Since sensor nodes constituting such USNs must be driven with low power, most of them use a beacon signal or time division multiple access (TDMA) to perform periodic sleep mode and wake-up. -driven)

However, the time driving method described above has a limitation in that unnecessary wake-up occurs and immediate response is not possible during the rest period.

In addition, in order to wake up by the wakeup signal, it is necessary to periodically perform an operation of checking whether the wakeup signal is received and whether the received wakeup signal is its own wakeup signal.

However, for the confirmation operation required for the wake-up in this manner, many active elements and circuits must be operated, which causes a problem of high power consumption.

The present invention devised to solve the above problems is to provide a wake-up circuit that can reduce the power consumption during the wake-up check operation by implementing the wake-up circuit as a passive element.

In order to achieve the above object, a wake-up circuit according to an embodiment of the present invention includes a rectifier for converting an RF signal into a DC signal; An overvoltage protection unit for blocking an overvoltage higher than a reference voltage among the voltages transmitted from the rectifier; And a detection unit operated by a signal transmitted from the overvoltage protection unit to detect a wakeup signal.

In addition, the rectifier of the present invention includes N half-wave double-voltage rectifier circuits respectively formed between the N input line and ground connected in parallel to the RF signal input terminal, the half-wave double-voltage rectifier circuit has a cascade structure It is characterized in that the connection.

In addition, the half-wave double voltage rectifier circuit in the present invention, the first rectifying element and the first capacitor connected in parallel between the RF signal input terminal and the ground; A second capacitor connected between the RF signal input terminal and a first rectifying element; And a second rectifier connected between the first rectifier and the first capacitor.

Further, in the present invention, the first rectifying element and the second rectifying element are characterized in that it is composed of a native NMOSFET.

In addition, in the present invention, the first rectifying device has a drain terminal connected to the second capacitor, a gate terminal and a source terminal connected to ground, and the second rectifying device has a drain terminal and a gate terminal connected to the second capacitor. A source terminal is connected to the first capacitor.

In addition, in the present invention, the overvoltage protection unit is connected between the rectifier and the ground is turned on when the voltage transmitted from the rectifier is higher than the reference voltage, characterized in that the overvoltage protection device is configured to block the overvoltage of the voltage transmitted from the rectifier do.

In the present invention, the overvoltage protection device is characterized in that the drain terminal and the gate terminal is connected to the rectifying portion, characterized in that consisting of NMOSFET connected to the source terminal to the ground.

In addition, the detection unit in the present invention is characterized in that it comprises a first inverter and a second inverter connected in series between the overvoltage protection unit and the output terminal, and connected in parallel in a CMOS form between the driving power supply and the ground.

The first inverter may include a PMOSFET having a drain terminal connected to the driving power supply and a gate terminal connected to an output of the overvoltage protection unit; And an NMOSFET having a drain terminal connected to a source terminal of the PMOSFET, a gate terminal connected to the overvoltage protection unit together with a gate terminal of the PMOSFET, and a source terminal connected to the ground.

The second inverter may include a PMOSFET having a drain terminal connected to the driving power supply and a gate terminal connected to an output of the first inverter; And an NMOSFET having a drain terminal connected to a source terminal of the PMOSFET, a gate terminal connected to the first inverter together with a gate terminal of the PMOSFET, and a source terminal connected to the ground.

In addition, the detection unit in the present invention, the first and second inverters connected in series between the overvoltage protection unit and the output terminal, the PMOSFET and the NMOSFET in the form of CMOS between the driving power supply and ground; And a bias circuit having an NMOSFET structure in which a drain terminal is connected to a source terminal of an NMOSFET of the first inverter, a gate terminal is connected to a scheduling circuit, and a source terminal is connected to ground.

Further, in the present invention, the NMOSFET of the first inverter has a threshold voltage of 0V.

In addition, the detection unit in the present invention, the first and second inverters connected in series between the overvoltage protection unit and the output terminal, the PMOSFET and the NMOSFET in the form of CMOS between the driving power supply and ground; And a diode device formed between the driving power supply and the PMOSFET of the first inverter.

In the present invention, the diode device is characterized in that the drain terminal is connected to the driving power supply, the gate terminal and the source terminal is composed of a PMOSFET connected to each other.

Prior to this, the terms or words used in this specification and claims should not be interpreted in a conventional, lexical sense, and the inventors will appropriately define the concept of terms in order to best explain their invention in the best way possible. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that it can.

According to the present invention, since the circuit is configured using a passive element, the rectifier and the overvoltage protection unit are formed so as not to use the battery voltage, and the detector is configured to be turned off instead of in a sleep state when there is no wake-up signal. In the wake-up operation of the sensor system, power consumption can be reduced, thereby improving the battery life.

In addition, since the present invention provides an open circuit when the bias circuit is turned off, current can be prevented from being lost by the bias circuit even when the NMOSFET of the inverter is turned on due to a low threshold voltage, thereby increasing the detection efficiency of the wakeup signal. It is effective to reduce power consumption.

In addition, since the threshold voltage of the NMOSFET of the inverter is lowered due to the diode device installed between the driving power source and the inverter, the reception sensitivity of the wakeup signal can be improved.

The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and preferred embodiments in conjunction with the accompanying drawings. In the present specification, when adding reference numerals to the components of each drawing, it should be noted that the same components as possible, even if displayed on the other drawings have the same number as possible. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a wakeup circuit according to an exemplary embodiment of the present invention.

In the wake-up circuit according to an embodiment of the present invention, as shown in FIG. 1, the rectifier 10 converts an RF input signal into a DC signal, and an overvoltage that cuts an overvoltage higher than a reference voltage among voltages transmitted from the rectifier 10. The protection unit 20 and the detection unit 30 is operated by a signal transmitted from the overvoltage protection unit 20 to detect a wake-up signal.

The rectifier 10 converts an RF input signal into a DC signal using half-wave double voltage rectifier circuits MR1, MR2, ..., MRn.

The rectifier 10 has N input lines L1, L2, ..., Ln formed in parallel between the RF signal input terminal RF in and ground GND, and each input line L1, L2. The half-wave double-voltage rectifier circuits MR1, MR2, ..., MRn are formed between Ln) and ground GND.

In this case, the half-wave double voltage rectifier circuits MR1, MR2, ..., MRn are connected to each other in a cascade structure.

That is, the output of the first half-wave double-voltage rectifier circuit MR1 formed in the first input line L1 is connected to the input of the second half-wave double-voltage voltage rectifier circuit MR2 formed in the second input line L2. An output of the N-1 half-wave double-voltage rectifier circuit formed on the N-1 input line is connected to an input of the N-th half-wave double-voltage rectifier circuit MRn formed on the N-th input line Ln.

The output of the N-th half-wave voltage rectifier circuit MRn is connected to an input of the overvoltage protection unit 20.

Meanwhile, the half-wave double-voltage rectifier circuits MR1, MR2, ..., MRn are first rectifying elements M11, M12, ..., connected in parallel between the RF signal input terminal RF in and ground (GND). M1n) and a second capacitor C21 connected between the first capacitors C11, C12, ..., C1n, the RF signal input terminal RF in and the first rectifying elements M11, M12, ..., M1n. , C22, ..., C2n, a second rectifying element connected between the first rectifying elements (M11, M12, ..., M1n) and the first capacitors (C11, C12, ..., C1n) M21, M22, ..., M2n).

The first rectifying elements M11, M12, ..., M1n and the second rectifying elements M21, M22, ..., M2n have a threshold voltage to increase the conversion efficiency of converting an RF signal into a DC signal. Not only are these little or zero volt native NMOSFETs, they are also configured with the smallest NMOSFETs to maximize input impedance.

In this case, the first rectifying elements M11, M12, ..., M1n have a drain terminal connected to the second capacitors C21, C22, ..., C2n, and a gate terminal and a source terminal connected to the ground GND. The second rectifier (M21, M22, ..., M2n) is connected to the drain capacitor and the gate terminal to the second capacitor (C21, C22, ..., C2n), the first capacitor (C11, C12) , ..., C1n) is connected to the source terminal.

Meanwhile, the half-wave double-voltage rectifier circuits MR1, MR2,..., And MRn have the first rectifying elements M11, M12,..., M1n and the second rectifying element when a (-) RF signal is input. M21, M22, ..., M2n are conducted so that the RF signals are charged to the first capacitors C11, C12, ..., C1n and the second capacitors C21, C22, ..., C2n, and ( +) When the RF signal is input, the first rectifiers M11, M12, ..., M1n are turned off, and the RF signals stored in the second capacitors C21, C22, ..., C2n are converted to the second rectifier. RF signals discharged to M21, M22, ..., M2n and discharged to the second rectifying elements M21, M22, ..., M2n and the first capacitors C11, C12, ..., The RF signal stored in C1n) is added to twice the RF signal and transferred to the next half-wave double voltage rectifier circuit.

As described above, in the wake-up circuit of the present invention, the rectifier 10 is configured to generate a DC voltage by the RF input signal, and has a structure in which no external power consumption is used.

The rectifier 10 may adjust the reception sensitivity by adjusting the size of the NMOSFET constituting the rectifier element and the number of stages of the half-wave double-voltage rectifier circuits MR1, MR2, ..., MRn.

The overvoltage protection unit 20 serves to block an overvoltage higher than a reference voltage among the DC voltages transmitted from the rectifier 10.

To this end, the overvoltage protection unit 20 is connected between the rectifier 10 and the ground (GND) (or the detector 30 and the ground (GND)) is a signal transmitted from the rectifier 10 (that is, DC Voltage) is greater than or equal to a reference value, and is turned on (that is, turned on) and includes an overvoltage protection device M1 that cuts off the overvoltage of the voltage transmitted from the rectifier 10.

In this case, the overvoltage protection device M1 of the overvoltage protection unit 20 maintains an off state (ie, turn-off) when the signal transmitted from the rectifier 10 is less than or equal to a reference value.

The overvoltage protection device M1 includes an NMOSFET having a drain terminal and a gate terminal connected to the output of the rectifier 10 and a source terminal connected to the ground GND.

Meanwhile, in FIG. 1, the overvoltage protection unit 20 is configured with only one overvoltage protection device M1, but the overvoltage protection unit 20 has the output and the ground of the rectifier 10 according to the overvoltage to be protected. Two or more overvoltage protection devices may be connected in series between the GNDs.

The detector 30 is operated by a signal transmitted from the overvoltage protection unit 20 to detect a wakeup signal.

The detection unit 30 is connected in parallel between the driving power supply VDD (for example, battery power supply) and the ground GND in a CMOS form, and is connected in series between the overvoltage protection unit 20 and the output terminal Vout. The first inverter P1 and N1 and the second inverter P2 and N2 are connected to each other.

In this case, the first inverters P1 and N1 have a drain terminal connected to the driving power supply VDD (for example, a battery power supply), and a first PMOSFET P1 having a gate terminal connected to the output of the overvoltage protection unit 20. A drain terminal is connected to a source terminal of the first PMOSFET P1, a gate terminal is connected to an output of the overvoltage protection unit 20 together with a gate terminal of the first PMOSFET P1, and a ground GND. The first NMOSFET N1 has a source terminal connected thereto.

In the first inverters P1 and N1, a common terminal between the source terminal of the first PMOSFET P1 and the drain terminal of the first NMOSFET N1 is used as an output.

The second inverters P2 and N2 have a drain terminal connected to a driving power supply VDD, a second PMOSFET P2 having a gate terminal connected to an output of the first inverters P1 and N1, and the second PMOSFET ( A drain terminal is connected to a source terminal of P2, a gate terminal is connected to an output of the first inverters P1 and N1 together with a gate terminal of the second PMOSFET P2, and a source terminal is connected to ground GND. A second NMOSFET N2 is connected.

In the second inverters P2 and N2, a common terminal of the source terminal of the second PMOSFET P2 and the drain terminal of the second NMOSFET N2 is used as an output, and the output of the second inverters P2 and N2 is a wake. It is connected to a main circuit (not shown) that senses an up signal.

When the RF signal is not input to the RF signal input terminal RF in, the detector 30 does not transmit a DC voltage proportional to the RF signal, so that the first PMOSFET P1 of the first inverters P1 and N1 is turned on. Since the first NMOSFET N1 is turned off, the driving power supply VDD is output through the first PMOSFET P1, and the second inverters P2 and N2 are transferred through the first inverters P1 and N1. Since the second PMOSFET P2 is turned off and the second NMOSFET N2 is turned on by the driving power supply VDD, the low power signal (for example, 0V) is output.

However, when the RF signal is input, the detector 30 turns off the first PMOSFET P1 of the first inverters P1 and N1 and turns on the first NMOSFET N1 by a DC voltage proportional to the RF signal. Outputs a low state signal (for example, 0 V), and the second inverters P2 and N2 are driven by the low state signal transmitted through the first inverters P1 and N1 to the second PMOSFET. Since P2 is turned on and the second NMOSFET N2 is turned off, the driving power supply VDD is output to the main circuit (not shown) through the second PMOSFET P2.

As a result, the main circuit operates according to the interrupt signal (or wake-up signal).

As described above, the wakeup circuit according to the embodiment of the present invention forms a circuit using a passive element, and the rectifier 10 and the overvoltage protection unit 20 are formed so as not to use the battery voltage VDD, and the wakeup signal. If not, since the detector 30 is configured to be turned off instead of in a sleep state, power consumption may be reduced during wakeup of the sensor system, thereby improving battery life.

In the wake-up circuit according to the embodiment of the present invention, when the NMOSFETs of the first inverters P1 and N1 are configured as NMOSFETs having almost no threshold voltage or having a threshold voltage of 0V, the turn-on voltage of the inverter is increased. It becomes low and it is possible to raise the reception sensitivity of the detector 30.

However, when the NMOSFET having a low threshold voltage is used, current consumption of several kilowatts is generated through the inverter path even in the standby time, and thus the battery efficiency is reduced. Thus, the wake-up circuit according to another embodiment of the present invention is illustrated in FIG. 2. In order to increase the reception sensitivity by using the detector 30 and to improve the efficiency of the battery, a duty scheduling method may be used by using a bias circuit.

FIG. 2 is a diagram illustrating another embodiment of the detector illustrated in FIG. 1.

In FIG. 2, only the detection unit 30 of the wake-up circuit is illustrated, but the detection unit 30 illustrated in FIG. 2 forms a wake-up circuit together with the rectifier 10 and the overvoltage protection unit 20 shown in FIG. 1. You will know.

As shown in FIG. 2, the detector 30 of the wake-up circuit according to an embodiment of the present invention may include the first inverters P1 and N1 and the bias circuit N3 of the CMOS type as the driving power source VDD and the ground ( The second inverters P2 and N2, which are connected in series between the GNDs and configured in a CMOS form, are connected between the first inverters P1 and N1 and the output terminal Vout.

In this case, a first PMOSFET P1 and a first PMOSFET P1 having a drain terminal connected to a driving power supply VDD and a gate terminal connected to an output of the overvoltage protection unit 20 are connected to the first inverters P1 and N1. A first terminal is connected to the source terminal of the drain terminal, a gate terminal is connected to the output of the overvoltage protection unit 20 together with the gate terminal of the first PMOSFET (P1), the first terminal connected to the source terminal to the bias circuit (N3) It consists of an NMOSFET N1.

Here, as the first NMOSFET N1, an NMOSFET having almost no threshold voltage or 0V is used.

In the first inverters P1 and N1, a common terminal between the source terminal of the first PMOSFET P1 and the drain terminal of the first NMOSFET N1 is used as an output.

In the bias circuit N3, a gate terminal is connected to a scheduling circuit (not shown) to use a duty scheduling method, a drain terminal is connected to a source terminal of the first NMOSFET N1, and a ground GND. ) Consists of an NMOSFET with a source terminal connected to it.

This bias circuit N3 is driven according to the bias signal NBias transmitted from the scheduling circuit (not shown).

Accordingly, since the bias circuit N3 provides an open circuit when the bias circuit N3 is turned off, that is, when a low state signal is supplied to the gate terminal from the scheduling circuit, the bias circuit N3 is turned on even when the first NMOSFET N1 is turned on due to the low threshold voltage. It is possible to prevent the current from being lost by (N3).

The second inverters P2 and N2 have a drain terminal connected to a driving power supply VDD, a second PMOSFET P2 having a gate terminal connected to an output of the first inverters P1 and N1, and the second PMOSFET P2. A drain terminal is connected to a source terminal of the gate terminal, a gate terminal is connected to an output of the first inverters P1 and N1 together with a gate terminal of the second PMOSFET P2, and a source terminal is connected to ground GND. It consists of 2 NMOSFETs (N2).

In the second inverters P2 and N2, a common terminal of the source terminal of the second PMOSFET P2 and the drain terminal of the second NMOSFET N2 is used as an output, and the output of the second inverters P2 and N2 is a wake. It is connected to a main circuit (not shown) that senses an up signal.

As described above, the wakeup circuit according to another embodiment of the present invention forms a circuit using a passive element, and the rectifier 10 and the overvoltage protection unit 20 are formed so as not to use the battery voltage VDD, and the wakeup circuit is performed. If there is no signal, the detector 30 is configured to be turned off instead of in a sleep state, thereby reducing power consumption during wakeup of the sensor system, thereby improving battery life.

In addition, the wake-up circuit according to another embodiment of the present invention provides an open circuit when the bias circuit N3 is turned off, so that the first NMOSFET N1 of the first inverters P1 and N1 is caused by the low threshold voltage. Even though is conducted, the current is prevented from being lost by the bias circuit N3, so that the power consumption can be reduced while increasing the detection efficiency of the wakeup signal.

3 is a diagram illustrating still another embodiment of the detector illustrated in FIG. 1.

In FIG. 3, only the detection unit 30 of the wakeup circuit is illustrated, but the detection unit 30 illustrated in FIG. 3 forms a wakeup circuit together with the rectifier 10 and the overvoltage protection unit 20 illustrated in FIG. 1. You will know.

As shown in FIG. 3, the detector 30 of the wake-up circuit according to an embodiment of the present invention may include the diode devices P1 and P2 and the first inverters P3 and N1 having a CMOS type to supply a driving power supply VDD. ) Is connected in series between the ground and GND, and the second inverters P4 and N2 configured in the CMOS form are connected between the first inverters P3 and N1 and the output terminal Vout.

At this time, the diode elements (P1, P2) may be composed of two or one or three or more, as shown in Figure 3, not only increases the wake-up reception sensitivity of the detector 30, but also serves to prevent overvoltage do.

In other words, the diode elements P1 and P2 are installed between the driving power supply VDD and the first inverters P3 and N1 to supply the voltage of the driving power supply VDD supplied to the drain terminal of the first NMOSFET N1. As a result, the threshold voltage of the first NMOSFET N1 is reduced.

As a result, since the first NMOSFET N1 of the first inverters P3 and N1 can operate at a voltage of 0.1 to 0.2 V, the detector 30 can detect a wake-up signal even at a low voltage. The reception sensitivity of the signal can be improved.

For example, when the diode elements P1 and P2 described above are used, a reception sensitivity of -33 dBm can be obtained as shown in FIG. 4.

The diode elements P1 and P2 are formed of PMOSFETs, the gate terminal is connected to the source terminal, and the drain terminal is formed to be connected to the driving power supply VDD or to the source terminal of the first diode element P1. .

In the first inverters P3 and N1, a drain terminal is connected to the second diode element P2, and a gate terminal is connected to the output of the overvoltage protection unit 20, and the first PMOSFET P3 is connected. A first NMOSFET having a drain terminal connected to a source terminal of the gate terminal, a gate terminal connected to an output of the overvoltage protection unit 20 together with a gate terminal of the first PMOSFET P3, and a source terminal connected to ground GND. It consists of (N1).

In the first inverters P3 and N1, a common terminal between the source terminal of the first PMOSFET P3 and the drain terminal of the first NMOSFET N1 is used as an output.

Meanwhile, the first NMOSFET N1 of the first inverters P3 and N1 may be configured as an NMOSFET having almost no threshold voltage or having a threshold voltage of 0 V. The first NMOSFET N of the first inverters P3 and N1 may be configured as the first NMOSFET N1. When N1 is configured as an NMOSFET having almost no threshold voltage or having a threshold voltage of 0 V, the bias circuit N3 shown in FIG. 2 is configured to prevent the current consumption of the first inverters P3 and N1 from being connected to the first NMOSFET ( It should be formed to be connected between the source terminal of N1) and ground (GND).

The second inverters P4 and N2 have a drain terminal connected to a driving power supply VDD, a second PMOSFET P4 having a gate terminal connected to an output of the first inverters P3 and N1, and the second PMOSFET P4. A drain terminal is connected to a source terminal of the gate terminal, a gate terminal is connected to an output of the first inverters P3 and N1 together with a gate terminal of the second PMOSFET P4, and a source terminal is connected to ground GND. It consists of 2 NMOSFETs (N2).

In the second inverters P4 and N2, the common terminal of the source terminal of the second PMOSFET P4 and the drain terminal of the second NMOSFET N2 is used as an output, and the output of the second inverters P4 and N2 is a wake. It is connected to a main circuit (not shown) that senses an up signal.

As such, the wakeup circuit according to another embodiment of the present invention forms a circuit using a passive element, and the rectifier 10 and the overvoltage protection unit 20 are formed so as not to use the battery voltage VDD, and the wakeup circuit is performed. When there is no up signal, since the detector 30 is configured to be turned off instead of in a sleep state, power consumption may be reduced during the wake-up operation of the sensor system, thereby improving battery life.

In addition, the wake-up circuit according to another embodiment of the present invention uses the first inverter (P3, N1) by the diode elements (P1, P2) provided between the driving power supply (VDD) and the first inverter (P3, N1). Since the threshold voltage of the first NMOSFET N1 is lowered, the reception sensitivity of the wake-up signal can be improved.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art that various modifications of the present invention without departing from the spirit and scope of the invention described in the claims below And can be changed.

1 is a diagram illustrating a wake-up circuit according to an exemplary embodiment.

FIG. 2 is a diagram illustrating another embodiment of the detector illustrated in FIG. 1.

3 is a diagram illustrating still another embodiment of the detector illustrated in FIG. 1.

FIG. 4 is a graph illustrating reception sensitivity characteristics of the wakeup circuit including the detector illustrated in FIG. 3.

<Description of the symbols for the main parts of the drawings>

10: rectifier 20: overvoltage protection unit

30: detector

Claims (14)

delete A rectifier for converting an RF signal into a DC signal; An overvoltage protection unit for blocking an overvoltage higher than a reference voltage among the voltages transmitted from the rectifier; And A detection unit operated by a signal transmitted from the overvoltage protection unit to detect a wake-up signal, The rectifying unit, N half-wave double voltage rectifier circuits respectively formed between N input lines and ground connected in parallel to the RF signal input terminal, The half-wave double-voltage rectifier circuit is a wake-up circuit, characterized in that connected to each other in a cascade structure. The method according to claim 2, The half-wave double voltage rectifier circuit, A first rectifier and a first capacitor connected in parallel between the RF signal input terminal and a ground; A second capacitor connected between the RF signal input terminal and a first rectifying element; And And a second rectifier connected between the first rectifier and the first capacitor. The method of claim 3, And the first rectifying element and the second rectifying element comprise a native NMOSFET. The method according to claim 4, The first rectifying device has a drain terminal connected to the second capacitor, a gate terminal and a source terminal connected to ground, and the second rectifying device has a drain terminal and a gate terminal connected to the second capacitor, and the first capacitor Wake-up circuit, characterized in that the source terminal is connected to. A rectifier for converting an RF signal into a DC signal; An overvoltage protection unit for blocking an overvoltage higher than a reference voltage among the voltages transmitted from the rectifier; And A detection unit operated by a signal transmitted from the overvoltage protection unit to detect a wake-up signal, The overvoltage protection unit, Wake-up circuit is connected between the rectifier and the ground is a wake-up circuit, characterized in that the over-voltage protection device for blocking the over-voltage of the voltage transmitted from the rectifier when the voltage transmitted from the rectifier is higher than the reference voltage. The method according to claim 6, The overvoltage protection device is a wake-up circuit, characterized in that consisting of an NMOSFET connected to the drain terminal and the gate terminal connected to the rectifying portion, the source terminal to the ground. A rectifier for converting an RF signal into a DC signal; An overvoltage protection unit for blocking an overvoltage higher than a reference voltage among the voltages transmitted from the rectifier; And A detection unit operated by a signal transmitted from the overvoltage protection unit to detect a wake-up signal, The detection unit, And a first inverter and a second inverter connected in series between the overvoltage protection unit and the output terminal and connected in parallel in a CMOS form between a driving power source and a ground. The method according to claim 8, The first inverter, A PMOSFET having a drain terminal connected to the driving power supply and a gate terminal connected to an output of the overvoltage protection unit; And And a NMOSFET having a drain terminal connected to a source terminal of the PMOSFET, a gate terminal connected to the overvoltage protection unit together with a gate terminal of the PMOSFET, and a source terminal connected to the ground. The method according to claim 8, The second inverter, A PMOSFET having a drain terminal connected to the driving power supply and a gate terminal connected to an output of the first inverter; And And a NMOSFET having a drain terminal connected to a source terminal of the PMOSFET, a gate terminal connected to the first inverter together with a gate terminal of the PMOSFET, and a source terminal connected to the ground. A rectifier for converting an RF signal into a DC signal; An overvoltage protection unit for blocking an overvoltage higher than a reference voltage among the voltages transmitted from the rectifier; And A detection unit operated by a signal transmitted from the overvoltage protection unit to detect a wake-up signal, The detection unit, A first inverter and a second inverter connected in series between the overvoltage protection unit and an output terminal, and having a PMOSFET and an NMOSFET connected in a CMOS form between a driving power source and a ground; And And a bias circuit having an NMOSFET structure having a drain terminal connected to the source terminal of the NMOSFET of the first inverter, a gate terminal connected to the scheduling circuit, and a source terminal connected to the ground. The method of claim 11, The NMOSFET of the first inverter has a threshold voltage of 0V. A rectifier for converting an RF signal into a DC signal; An overvoltage protection unit for blocking an overvoltage higher than a reference voltage among the voltages transmitted from the rectifier; And A detection unit operated by a signal transmitted from the overvoltage protection unit to detect a wake-up signal, The detection unit, A first inverter and a second inverter connected in series between the overvoltage protection unit and an output terminal, and having a PMOSFET and an NMOSFET connected in a CMOS form between a driving power source and a ground; And And a diode element formed between the driving power supply and the PMOSFET of the first inverter. 14. The method of claim 13, The diode device, A wake-up circuit comprising a PMOSFET having a drain terminal connected to the driving power supply and a gate terminal and a source terminal connected to each other.

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