CN108471312A - D-A converter - Google Patents
D-A converter Download PDFInfo
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- CN108471312A CN108471312A CN201710100285.XA CN201710100285A CN108471312A CN 108471312 A CN108471312 A CN 108471312A CN 201710100285 A CN201710100285 A CN 201710100285A CN 108471312 A CN108471312 A CN 108471312A
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- current
- current source
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- source array
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Abstract
The present invention provides a kind of D-A converter, including buffer circuit, current switching circuit and weighted current generation circuit.Buffer circuit receives the digital signal for having N number of bits and clock signal and exports N number of switch control signal according to this.Current switching circuit is with N number of switch and according to switch control signal to be turned on or off.There is weighted current generation circuit M current source array, each current source array to export K output current.The current value of each output current of each current source array is incremented by with binary weighting formula from low to high respectively, and 2 times of the maximum output current that the minimum output current of m-th of current source array is 1 current source array of m, and N is that M is multiplied by K, and 1<m≦M.The totalling current value for the output current that the output of D-A converter is exported by M current source array.
Description
Technical field
The present invention relates to a kind of conversion technologies, and more particularly to a kind of current type D-A converter.
Background technology
D-A converter (Digital to Analog Converter, DAC) has widely been applied now
In the data conversion of electronic device, corresponding analog signal mainly is converted digital signals into, and be provided to electronic device
To carry out related application.Wherein, current type D-A converter (Current DAC) is a kind of high speed number-mould common now
Converter can directly drive load since it is not required to additional amplifier as auxiliary, become high-res,
The D-A converter of high speed frequently with one of best framework.
Now in the performance indicator of D-A converter, static and two aspect of dynamic can be divided into.In terms of static characteristic,
Main is exactly to accumulate nonlinearity erron (Integral nonlinearity error, INL) and differential-non-linearity error
(Differential nonlinearity error, DNL).The size of this two indexs is determined by the matching of current source.
When the number of bits converted is bigger, the quantity needed for its usual unitary current source transistor will be more, shared
Area will be bigger, can be only achieved preferable accumulation nonlinearity erron and differential-non-linearity error.Therefore, for general N bis-
For system Bit-digital-analog converter, 2 are needed in totalNA unitary current source transistor, so the area in total current source can be with
Number of bits increases and quickly increases.
In addition, in terms of dynamic characteristic, main performance indicator is exactly spurious-free dynamic range (Spurious Free
Dynamic Range, SFDR) and speed.Accumulate nonlinearity erron and spurious-free dynamic range all with unitary current source transistor
Output impedance it is related, when number of bits is bigger, the number of current source transistor is more, required unitary current source crystal
The output impedance of pipe will become bigger, and then can not be applied in the system of low supply voltage.
Invention content
In view of this, the present invention provides a kind of current type D-A converter, the framework of multiple reference current sources can be used
The single reference current source in traditional design is replaced, thereby realizes the electric current that a power is low, area is small and output impedance is low
Formula D-A converter.
The D-A converter of the present invention, suitable for carrying out conversion to having the digital signal of N number of bits,
N is conjunction number, including：Buffer circuit, current switching circuit and weighted current generation circuit.Buffer circuit receive digital signal with
Clock signal, and using clock signal as time reference, react on digital signal and export N number of switch control signal.Electric current is opened
Powered-down road has N number of switch, and each switch is according to corresponding switch control signal to be turned on or off.Weighted current generation circuit has
There are M current source array, each current source array to export K output current.The electricity of each output current of each current source array
Flow valuve is incremented by with binary weighting formula from low to high respectively, and the minimum output current of m-th of current source array is the m-1 electricity
2 times of the maximum output current of stream source array.Wherein N is that M is multiplied by K, and M, K and m are the positive integer more than 1, and 1<m≦M.Wherein
The output of D-A converter passes through N number of totalling current value for switching the output current exported by M current source array.
The single current source array in traditional design can be divided into independence based on above-mentioned, of the invention D-A converter
It is multiple, and generate multiple independent reference currents respectively by multiple reference current sources and be provided to corresponding current source battle array
Row.Thereby, the quantity and area of the current source transistor needed for each current source array can be reduced.Meanwhile it can also reduce unit
The output impedance of current source transistor, to realize that power is low and performance more preferably D-A converter.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and coordinate shown attached drawing
It is described in detail below.
Description of the drawings
Fig. 1 shows the schematic diagram of the D-A converter of one embodiment of the invention；
Fig. 2 shows the schematic diagrames of the current switching circuit of one embodiment of the invention and weighted current generation circuit；
Fig. 3 shows the schematic diagram of the weighted current lens array of one embodiment of the invention；
Fig. 4 shows the schematic diagram of the reference current source of one embodiment of the invention；
Fig. 5 shows the schematic diagram of the D-A converter of another embodiment of the present invention.
Reference sign：
100、500：D-A converter；
110、510：Buffer circuit；
120、530：Current switching circuit；
122_1~122_N：Switch；
130：Weighted current generation circuit；
210：Reference current generates unit；
220_1~220_M：Reference current source；
231_1~231_K, 232_1~232_K, 23M_1~23M_K：Current source；
240：Output loading；
310：Weighted current lens array；
520：Decoding circuit；
532_1~532_L：First switch；
534_1~534_2J：Second switch；
540：Current generating circuit；
AS：Analog signal；
CLK：Clock signal；
CSA1~CSAM：Current source array；
CSAF1~CSAFM：First current source array；
CSAS：Second current source array；
DS：Digital signal；
IOUT1_1~IOUT1_K, IOUT2_1~IOUT2_K, IOUTM_1~IOUTM_K, IOUTF1_1~IOUTF1_
K, IOUTFM_1~IOUTFM_K, IOUTS_1~IOUTS_2J：Output current；
IREF1~IREFM：Reference current；
OP1、OP2：Operational amplifier；
Q1、Q2：N type field effect transistor；
R1、R2：Resistance；
SB1~SBN, SBF1~SBFL, SBS1~SBSJ：Binary digit signal；
SC1~SCN：Switch control signal；
SCF1~SCFL：First switch controls signal；
SCS1~SCS2J：Second switch controls signal；
SOUT：Output；
T：Output node；
Vcc：Supply voltage；
VREF：Reference voltage.
Specific implementation mode
With reference first to Fig. 1, in the present embodiment, D-A converter 100 includes buffer circuit 110, current switching circuit
120 and weighted current generation circuit 130.The D-A converter 100 of the present embodiment is suitable for having N number of bits
Digital signal DS carries out conversion.Digital signal DS can be by binary digit signal SB1~SBN of single binary digit come structure
At.Wherein, since D-A converter 100 in design can will be electric according to the number of bits of handled digital signal DS
Stream source array decile be independent it is multiple carry out conversion processing, N is necessary for closing number.For current source array is carried out
The detailed description of decile please refers to aftermentioned.
Buffer circuit 110 receives digital signal DS and clock signal CLK, and using clock signal CLK as time reference, can
It reacts on digital signal DS and exports N number of switch control signal SC1~SCN.For example, buffer circuit 110 can for example including
Input buffer and latch, and the clock signal CLK that arranges in pairs or groups carrys out the digital signal DS synchronism outputs N according to N number of bits
A switch control signal SC1~SCN.
Current switching circuit 120 couples buffer circuit 110.Current switching circuit 120 has N number of switch 122_1~122_
N, respectively switch 122_1~122_N according to corresponding switch control signal SC1~SCN to be turned on or off.For example, when opening
When pass control signal is low logic level (the first logic level), the switch controlled will disconnect, when switch control signal is
When high logic level (the second logic level), the switch controlled can be connected.It should be noted that in other embodiments, opening
The state of switch can also be controlled according to the logic level with aforementioned opposite way by closing control signal, and the present invention is not according to this
Limit.
Weighted current generation circuit 130 couples current switching circuit 120.Weighted current generation circuit 130 has M electric current
Source array CSA1~CSAM, and the exportable K output current of each current source array CSA1~CSAM.For example, current source battle array
Row CSA1 K output current IO UT1_1~IOUT1_K of output, K output current IO UT2_1 of current source array CSA2 outputs~
IOUT2_K.And so on, current source array CSAM exports K output current IO UTM_1~IOUTM_K.And N is that M is multiplied by K, M
And K is the positive integer more than 1.That is, the factor for being more than 1 that M and K is N.
In addition, each output current of each current source array CSA1~CSAM current value respectively from low to high with two into
Weighting type processed is incremented by, and the maximum output current that the minimum output current of m-th of current source array is the m-1 current source array
2 times.Wherein m is positive integer more than 1, and 1<m≦M.For example, following table 1 is described when N is 12, M is 3 and K is 4
In the case of, the output current value of current source array CSA1~CSA3.
Table 1
As shown in Table 1, in embodiments of the present invention, each output current IO UT1_1 of current source array CSA1~
The current value of IOUT1_4 is incremented by with binary weighting formula from low to high respectively.Wherein, IREF1 is adopted by current source array CSA1
Reference current.In addition, the minimum output current IOUT2_1 of the 2nd current source array CSA2 is the 1st current source array
The minimum output current IOUT3_1 of 2 times of the maximum output current IOUT1_4 of CSA1, the 3rd current source array CSA3 is the 2nd
2 times of the maximum output current IOUT2_4 of a current source array CSA2.Due to the output current IO UT2_ of current source array CSA2
1~IOUT2_4 can be considered that binary weighting formula is carried out on the basis of 24IREF1 to be incremented by, ginseng used by current source array CSA2
24IREF1 can be equal to by examining electric current IREF2.Similarly, output current IO UT3_1~IOUT3_4 of current source array CSA3 is visual
It is incremented by carry out binary weighting formula on the basis of 28IREF1, reference current IREF3 used by current source array CSA2 can be waited
In 28IREF1.
The output SOUT of D-A converter 100 is then exported by M current source array CSA1~CSAM by N number of switch
Output current totalling current value.By foregoing circuit structure, D-A converter 100 can according to digital signal DS (two into
Signal SB1~SBN in position processed) logic level control being turned on or off for each switch 122_1~122_N, thereby make corresponding
Output current by the switch of conducting converge into add up current value output SOUT.Output SOUT can for example be provided to one
Output loading (such as resistance) completes conversion to generate transformed analog signal.
For current switching circuit 120 among more detailed description D-A converter 100 and weighted current generation circuit
130 circuit structure and make flowing mode, please refers to Fig. 2 below and illustrate.
As shown in Fig. 2, can further include that reference current generates unit 210 in weighted current generation circuit 130.Reference current
It generates unit 210 and is respectively coupled to M current source array CSA1~CSAM.Reference current, which generates unit 210, has M reference current
Source 220_1~220_M.Each reference current source 220_1~220_M is responsible for generating different reference currents to corresponding electric current
Source array.Specifically, as shown in Fig. 2, reference current source 220_1 can generate reference current IREF1 and be provided to corresponding electricity
In the array CSA1 of stream source.Thereby, as indicated above as current source array CSA1 output current IO UT1_1~IOUT1_K it is defeated
Go out current value to be may be set to respectively from low to high with incremental IREF1,2IREF1 ... the 2K-1IREF1 of binary weighting formula (in Fig. 2
In be equivalent to current source 231_1~231_K to be indicated).
In addition, reference current source 220_2 can generate reference current IREF2 and be provided to corresponding current source array CSA2
In.By preceding description it is found that the minimum output current IOUT2_1 of current source array CSA2 should be the maximum of current source array CSA1
2 times of output current IO UT1_K, since the current value of output current IO UT1_K is 2K-1IREF1, therefore output current IO UT2_1
Current value should be 2KIREF1.Therefore, the current value for the reference current IREF2 that reference current source 220_2 is provided should be
2KIREF1.And so on, it is by m-1 by the reference current that m-th of reference current source is generated to m-th of current source array
Reference current source generates the K powers times of 2 of the reference current to the m-1 current source array.Reference current source 220_M is provided
Reference current IREFM should be 2 (M-1) KIREF1.
In addition, as shown in Fig. 2, each current source array CSA1~CSAM has K output end.In current switching circuit 120
Included in each switch 122_1~122_N first end couple it is right among the output end of each current source array CSA1~CSAM
The output end answered, respectively the second end of switch 122_1~122_N then couple output node T.Each switch 122_1~122_N then by
It controls in corresponding switch control signal SC1~SCN, thereby by each switch 122_1~122_N outputs corresponding output current
Output node T is converged into, and current value (output SOUT) will be added up by output node T and exported.In fig. 2, output node T
Output loading 240 is coupled, transformed analog signal AS can be thereby generated by output loading 240, to complete conversion.
In one embodiment of this invention, each current source array may include weighted current lens array.As shown in figure 3, weighting
Current lens array 310 couples corresponding reference current source 220_1 among M reference current source 220_1~220_M.Also, it weights
Current lens array 310 can based on by mirror than generated in such a way that binary weighting formula is incremental K output current IO UT1_1~
IOUT1_K.In the present embodiment, so-called " mirror ratio " e.g. refer to for reference current source 220_1 and current source 231_1~
231_K and for forming principal and subordinate (master/slave) unit current source number of transistors purpose ratio of current mirror.In general,
If the breadth length ratio (width/length ratio) for implementing the transistor of current mirror is identical, you can according to principal and subordinate's unit current source
The ratio of transistor, by being provided from side electric current on the basis of the primary side current of current mirror.For example, in the present embodiment, it refers to
The reference current IREF1 that current source 220_1 is provided is the primary side current of current mirror, and by adjusting main side and from the mirror between side
Penetrate ratio, you can determine current source 231_1~231_K exported as output current IO UT1_1~IOUT1_ from side electric current
K。
Furthermore since the D-A converter 100 of the present invention is divided by multiple reference current source 220_1~220_M
Multiple independent reference current IREF1~IREFM are not generated is provided to corresponding current source array CSA1~CSAM, therefore each electricity
The maximum output current that stream source array CSA1~CSAM is exported all is based on different binary systems received by each current source array
The reference current of weighting degree and pass through mirror formed.The feelings of all reference currents are formed with single reference current source is used
Condition is compared, and is not required to carry out mirror on the basis of minimum reference current, can be significantly decreased needed for weighted current lens array most
Big mirror ratio, and then quantity, area and the output impedance of unitary current source transistor can be reduced.
Fig. 2 is returned to, the reference current IREF2 that reference current source 220_2 is provided is provided equal to reference current source 220_1
Reference current IREF1 2 K powers times.Reference current source 220_1's and reference current source 220_2 illustrated below
Structure.
Fig. 4 is please referred to, reference current source 220_1 includes n type field effect transistor Q1, resistance R1 and operational amplifier OP1.
The drain electrode of n type field effect transistor Q1 couples power source voltage Vcc, and provides reference current by the drain electrode of n type field effect transistor Q1
IREF1。
The source electrode of the first end coupling n type field effect transistor Q1 of resistance R1, the second end of resistance R1 couple earthing potential.Fortune
Calculate the source electrode of the non-inverting input coupling n type field effect transistor Q1 of amplifier OP1, the inverting input of operational amplifier OP1
Reference voltage VREF is received, and the inverting input of operational amplifier OP1 is coupled to the fortune in other reference current sources 220_2
Calculate the inverting input of amplifier OP2.Reference current source 220_2 includes n type field effect transistor Q2, resistance R2 and operation amplifier
Device OP2, structure are similar with reference current source 220_1.
Wherein, the size of resistance R2 possessed by the 2nd reference current source 220_2 is the 1st reference current source 220_1 institute
The K powers times of the 2 of the size for the resistance R1 having.Thereby, make the reference current IREF2 that reference current source 220_2 is provided can
It is equal to the K powers times of the 2 of the reference current IREF1 that reference current source 220_1 is provided.
It should be noted that in one embodiment, also assortable decoding circuit comes to digital signal in D-A converter
The binary digit signal of middle part is decoded, and thereby generates switch control signal.
As shown in figure 5, in the present embodiment, D-A converter 500 includes buffer circuit 510, decoding circuit 520, electricity
Flow switching circuit 530 and current generating circuit 540.D-A converter 500 is suitable for the number to having N number of bits
Signal DS carries out conversion.In embodiments of the present invention, digital signal DS includes the first signal and J of L number of bits
The second signal (N=L+J) of number of bits, wherein as shown in figure 5, the first signal can be by the binary digit of single binary digit
Signal SBF1~SBFL is constituted, and second signal can be made of binary digit signal SBS1~SBSJ of single binary digit,
And L is necessary for closing number.
Buffer circuit 510 receives the first signal (binary digit signal SBF1~SBFL) and clock signal CLK, and with clock pulse
Signal CLK can react on binary digit signal SBF1~SBFL and export L first switch control signal as time reference
SCF1~SCFL.For example, buffer circuit 510 can be for example including input buffer and latch, and clock signal of arranging in pairs or groups
CLK comes according to L first switch control signal SCF1~SCFL of binary digit signal SBF1~SBFL synchronism outputs.
Decoding circuit 520 receives second signal (binary digit signal SBS1~SBSJ) and clock signal CLK, and with clock pulse
Signal CLK is decoded and exports 2 J power second switches to binary digit signal SBS1~SBSJ as time reference
Control signal SCS1~SCS2J。
Current switching circuit 530 couples buffer circuit 510 and decoding circuit 520.Current switching circuit 530 has L the
J power second switches 534_1~534_2 of one switch 532_1~532_L and 2J, each first switch 532_1~532_L according to
According to corresponding first switch control signal SCF1~SCFL to be turned on or off, each second switch 534_1~534_2JAccording to right
The second switch control signal SCS1~SCS2 answeredJTo be turned on or off.For example, when switch control signal is that low logic is accurate
When position (the first logic level), the switch controlled will disconnect, when switch control signal is that (the second logic is accurate for high logic level
Position) when, the switch controlled can be connected.It should be noted that in other embodiments, switch control signal also can according to it is preceding
The logic level of opposite way is stated to control the state of switch, the embodiment of the present invention is not limited according to this.
Current generating circuit 540 couples current switching circuit 530.Current generating circuit 540 has M the first current source battle arrays
Arrange CSAF1~CSAFM and the second current source array CSAS, each exportable K outputs of first current source array CSAF1~CSAFM
Electric current.For example, the first current source array CSAF1 exports K output current IO UTF1_1~IOUTF1_K, the first current source
Array CSAF2 exports K output current IO UTF2_1~IOUTF2_K.And so on, the first current source array CSAFM exports K
A output current IO UTFM_1~IOUTFM_K.Wherein L is that M is multiplied by K, M and K as the positive integer more than 1.That is, M and K
For the factor for being more than 1 of L.
In addition, the current value difference of each output current of each first current source array CSAF1~CSAFM is from low to high
It is incremented by with binary weighting formula, and the minimum output current of m-th of first current source arrays is m-1 the first current source arrays
2 times of maximum output current, wherein m is the positive integer more than 1, and 1<m≦M.Here, the first current source array CSAF1~
CSAFM make flowing mode and current source array CSA1~CSAM of previous embodiment is same or similar, therefore its detailed content is herein
It repeats no more.
Second current source array CSAS then exports 2 J power output current IOs UTS_1~IOUTS_2J, wherein J is also
Positive integer more than 1.The current value of each output current of second current source array CSAS is identical, is all equal to the 1st first
The half of the minimum output current of current source array (the first current source array CSAF1) times or the first current source of m-th
Twice of the maximum output current of array (the first current source array CSAFM).Specifically, when the first signal (believe by binary digit
Number SBF1~SBFL) for digital signal DS high binary digit part and second signal (binary digit signal SBS1~SBSJ) is
When the low binary digit part of digital signal DS, each output current value of the second current source array CSAS is equal to the first current source
The half of the minimum output current of array CSAF1 times.Conversely, when the first signal (binary digit signal SBF1~SBFL) is
The low binary digit part of digital signal DS and height that second signal (binary digit signal SBS1~SBSJ) is digital signal DS
When binary digit part, each output current value of the second current source array CSAS be then the first current source array CSAFM most
Twice of big output current.
The output SOUT of D-A converter 500 is M first current source array CSAF1~CSAFM and the second current source
J power second switches 534_1~534_2 that array SCAS passes through L first switch 532_1~532_L and 2JIt is exported
The totalling current value of output current.By foregoing circuit structure, D-A converter 500 can be according to digital signal DS (including two
System position signal SBF1~SBFL and binary digit signal SBS1~SBSJ) logic level lead on-off control each switch
It opens, corresponding output current is thereby made to converge into the output SOUT for adding up current value by the switch of conducting.Export SOUT
It can be for example provided to an output loading (such as resistance), to generate transformed analog signal, complete conversion.
In conclusion the present invention D-A converter can respectively be generated by multiple reference current sources it is multiple independent
Reference current is provided to corresponding independent current array.Thereby, by by the single current source array of tradition be divided into array compared with
Small independence is multiple, can reduce the quantity and area of the unitary current source transistor needed for each current source array.Meanwhile also may be used
The output impedance of unitary current source transistor is reduced, and then improves accumulation nonlinearity erron and reduces spurious-free dynamic range,
To realize that power is low and performance more preferably D-A converter.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (8)
1. a kind of D-A converter, which is characterized in that suitable for having a digital signal of N number of bits into line number-
Mould is converted, and N is to close number, and the D-A converter includes：
One buffer circuit receives the digital signal and a clock signal, and using the clock signal as a time reference, instead
Digital signal described in Ying Yu and export N number of switch control signal；
One current switching circuit couples the buffer circuit, and with N number of switch, each switch described is opened according to corresponding
Control signal is closed to be turned on or off；And
One weighted current generation circuit, couples the current switching circuit, with M current source array, each current source
Array exports K output current, and the current value of each output current of each current source array is respectively from low to high with two
System Weighting type is incremented by, and the maximum output electricity that the minimum output current of m-th of current source array is the m-1 current source array
2 times of stream, wherein N are that M is multiplied by K, and M, K and m are the positive integer more than 1, and 1<M≤M,
The output of the wherein described D-A converter by the M current source array by it is described it is N number of switch export described in
The one of output current adds up current value.
2. D-A converter according to claim 1, which is characterized in that the weighted current generation circuit further includes：
One reference current generates unit, is respectively coupled to the M current source array, with M reference current source, each ginseng
Current source is examined to generate a reference current to corresponding current source array, wherein generating to described in m-th of current source array
Reference current is to generate to the 2 of the reference current of the m-1 current source array K powers times.
3. D-A converter according to claim 2, which is characterized in that each current source array includes：
One weighted current lens array couples a corresponding reference current source among the M reference current source, and is based on mirror
It penetrates than generating the K output current in such a way that binary weighting formula is incremental.
4. D-A converter according to claim 2, which is characterized in that each reference current source includes：
One n type field effect transistor, drain electrode one supply voltage of coupling, and provide the reference current by its drain electrode；
One resistance, first end couple the source electrode of the n type field effect transistor, and second end couples an earthing potential；And
One operational amplifier；Its non-inverting input couples the source electrode of the n type field effect transistor, and inverting input receives one
Reference voltage, and the inverting input for the operational amplifier being coupled in other reference current sources,
Wherein, the size of the resistance possessed by the m-1 reference current source is described possessed by m-th of reference current source
The K powers times of the 2 of the size of resistance.
5. D-A converter according to claim 2, which is characterized in that each current source array has K output
The first end at end, each switch couples a corresponding output end among the output end, the second end coupling of each switch
One output node.
6. D-A converter according to claim 4, which is characterized in that when the switch control signal is patrolled for one first
When collecting level, the switch controlled disconnects, and when the switch control signal is second logic level, is controlled
The switch conduction, thereby by each switch export it is corresponding it is described output current to the output node, and by institute
It states output node and exports the totalling current value.
7. D-A converter according to claim 5, which is characterized in that the output node couples an output loading,
And a transformed analog signal is generated by the output loading.
8. a kind of D-A converter, which is characterized in that suitable for having a digital signal of N number of bits into line number-
Mould is converted, and the digital signal includes a second signal of one first signal and J number of bits of L number of bits, N=L+
J, and L is to close number, the D-A converter includes：
One buffer circuit receives first signal and a clock signal, and using the clock signal as a time reference, instead
First signal described in Ying Yu and export L first switch control signal；
One decoding circuit receives the second signal and the clock signal, and using the clock signal as the time base
Standard is decoded and exports 2 J power second switches control signal to the second signal；
One current switching circuit couples the buffer circuit and the decoding circuit, the J powers with L first switch Yu 2
A second switch, each first switch control signal to be turned on or off according to the corresponding first switch, and each described the
Two switches control signal to be turned on or off according to the corresponding second switch；And
One current generating circuit couples the current switching circuit, with M the first current source arrays and one second current source
Array, each first current source array export K output current, each output current of each first current source array
Current value be incremented by from low to high with binary weighting formula respectively, and the minimum output current of m-th of first current source arrays is
2 times of the maximum output current of m-1 the first current source arrays, wherein L are that M is multiplied by K, and J, M, K and m are just whole more than 1
Number, and 1<M≤M, the J power output currents of second current source array output 2, second current source array it is each
The current value of a output current is identical and the half times of minimum output current equal to the 1st the first current source array or
Twice of the maximum output current of the first current source array of m-th,
The output of the wherein described D-A converter is that the M the first current source arrays pass through with second current source array
The L first switch adds up current value with the one of described 2 J power second switches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710100285.XA CN108471312A (en) | 2017-02-23 | 2017-02-23 | D-A converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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