CN206741242U - A kind of vibration signals collecting circuit - Google Patents

Abstract

The utility model belongs to avionics, is related to a kind of vibration signals collecting circuit.The vibration signals collecting circuit includes some vibrating sensor interface circuits, signal condition passage, analog to digital conversion circuit, PLD and DSP.The corresponding one group of vibration signal of vibration signal conditioning passage, and be all connected on analog to digital conversion circuit, and analog to digital conversion circuit is connected on PLD, and PLD is connected with DSP.The signal conditioning circuit is made up of high-pass filtering circuit, voltage follower circuit, pga circuit, Anti-aliasing Filter Circuits and the smoothed filter circuit being sequentially connected.The Anti-aliasing Filter Circuits reference clock pin is connected to the clock module in PLD.The utility model sets cut-off frequency by PLD, the interference signal in effective attenuation signal, can realize Multi-channel Vibration Signals parallel acquisition, ensures the temporal correlation between other airborne record system gathered datas.

Description

A kind of vibration signals collecting circuit

Technical field

The utility model belongs to avionics, is related to a kind of vibration signals collecting circuit.

Background technology

In the test of helicopter rotary part, analysis of vibration signal method is to realize one of effective ways of fault diagnosis, is led to Cross and spectrum analysis is done to vibration signal, obtain the frequency domain characteristic of vibration signal, carry out fault diagnosis and the analysis of mechanical system, together When according to appropriate fault model judge the current working condition of parts, provide appropriate message for system operation and maintenance.

But vibration signal is typically random unstable state, so synchronous acquisition and the processing of vibration signal must be carried out.And Current existing vibration test system, hardware realize complicated, poor real, are not easy to realize the collection of multiple signals synchronous high-speed and place Reason.

Also, on-board data record system is all without providing high precision clock synchronizing function, temporal correlation between data Difference, when a problem occurs, it is impossible to using temporal correlation between data come problem analysis exactly.

Utility model content

Purpose of utility model：Provide a kind of circuit that can be realized to vibration signal multi-channel high-speed synchronous acquisition.

Technical scheme：A kind of vibration signals collecting circuit, it includes some vibrating sensor interface circuits, signal condition leads to Road, analog to digital conversion circuit, PLD and DSP, wherein, the corresponding one group of vibration letter of vibration signal conditioning passage Number, the vibration signal conditioning passage is all connected on analog to digital conversion circuit, and analog to digital conversion circuit is connected to FPGA On device, and the PLD is connected with DSP, wherein, the signal conditioning circuit is filtered by the high pass being sequentially connected Wave circuit, voltage follower circuit, pga circuit, Anti-aliasing Filter Circuits and smoothed filter circuit composition, it is described anti-mixed Folded filter circuit reference clock pin is connected to the clock module in PLD.

The vibrating sensor interface circuit is constant current source driving circuit.The high-pass filtering circuit is 1 rank RC filtered electricals Road.

The pga circuit is connected with PLD, and gain is set by PLD.

The Anti-aliasing Filter Circuits use 8 rank SCFs, and cut-off frequency is by reference to clock setting.Output Smothing filtering uses 2 rank Butterworth filters.

Analog-digital conversion circuit as described includes 16 separate successive approximation A/D converters of 6 tunnels.

The PLD includes analog-to-digital conversion control sequential module, clock module, control register, state and posted Storage and data cache module, wherein, analog-to-digital conversion control sequential module connection analog-digital converter, and deposited respectively with control Device connects with status register, and control register connects DSP with status register, data cache module respectively with analog-to-digital conversion Device connects with DSP.

The DSP has CPCI interfaces, and data are exchanged with data management module by CPCI.

Beneficial effect：Each passage in the utility model vibration signals collecting circuit has signal conditioning circuit, uses 8 Rank oblong switches capacitive filter realizes anti-aliasing filter, and its cut-off frequency can be set by PLD, effectively be declined Interference signal in cut signal.The utility model realizes analog to digital conversion circuit logic control using PLD, realizes Multi-channel Vibration Signals parallel acquisition, it is independent of each other between analog-to-digital conversion module, 32 road vibration signals collectings can be achieved, single channel is adopted Sample rate reaches as high as 150kbps, according to Shannon sampling thheorems, can meet vibration signals collecting requirement in most cases.And And multi-channel Vibration Signal synchronous acquisition is realized by PLD, keep multiple phase letters being sampled between signal Breath, while 16 analog-digital converters are selected, the high precision collecting of vibration signal can be achieved.

By DSP according to IRIG-B form collator vibration datas, ensure between other data of airborne record system collection Temporal correlation, realize that high-speed data exchanges with data management module by CPCI interfaces, using Synchronous time average algorithm, Add Hanning window algorithm and fft algorithm, obtain the characteristic frequency and amplitude of vibration signal.

Brief description of the drawings

Fig. 1 is the utility model vibration signals collecting circuit diagram；

Fig. 2 is the utility model signal conditioning circuit figure；

Fig. 3 is programming device logical device structured flowchart；

Wherein, 1- sensor interface circuitries, 2- signal conditioning circuits, 3- analog to digital conversion circuits, 4- PLDs, 5-DSP, 6- driver, 7-SDRAM, 8- high-pass filtering circuit, 9- voltage follower circuits, 10- pga circuits, 11- resist Aliasing filter circuit, 12- smoothed filter circuits, 13- analog-to-digital conversions control sequential, 14- control registers, 15- Clock management moulds Block, 16- status registers, 17- data buffer storages.

Embodiment

The utility model is described in further detail below in conjunction with the accompanying drawings.

Referring to Fig. 1, it is the utility model vibration signals collecting circuit diagram.The vibration signals collecting circuit bag Include some vibrating sensor interface circuits, signal condition passage, analog to digital conversion circuit, PLD and DSP circuit.Institute Vibration signal conditioning passage is stated to be all connected on analog to digital conversion circuit, and analog to digital conversion circuit is connected to PLD On.And the PLD is connected with DSP Processor, meanwhile, the PLD has analog to digital conversion circuit Control logic passage, and for pga circuit gain set setting passage.By PLD pair IRIG-B clocks are counted, and produce passage time scale information.DSP arranges data according to IRIG-B data formats, is stored in CPCI Mapping space, data management module read data by CPCI interfaces.DSP carries out video analysis to vibration data, is vibrated The characteristic frequency and amplitude of data.

The vibrating sensor interface circuit is constant-current source circuit, and supply voltage is 16~32V, output current 2.2mA, Excitation is provided for integrated piezoelectric formula vibrating sensor, vibration signal is converted to voltage signal by driving vibrating sensor.

Vibration signal is both needed to carry out the suitable tune of signal before analog-to-digital conversion is carried out.The vibration signal conditioning passage please join Fig. 2 is read, corresponding one group of vibration signal, it is electric by the high-pass filtering circuit, voltage follower circuit, programmable amplification being sequentially connected Road, Anti-aliasing Filter Circuits and smoothed filter circuit composition.The conditioning such as it is amplified, filters to vibration signal.

Described high-pass filtering circuit is single order RC high-pass filters, and vibrating sensor output signal passes through high-pass filtering Device, the DC component in signal is filtered out, avoid the setting of DC component influence channel gain and spectrum analysis in signal.

Described programmable amplifier makes it meet that analog to digital conversion circuit input range will the appropriate amplification of vibration signal Ask.Programmable amplifier selects the AD8251 of AD companies, and the chip be difference instrumentation amplifier, makes an uproar with input impedance is high and low The characteristics such as sound, gain programmable.Multiplication factor optional 1,2,4,8.Set according to airborne configuration by PLD per road Acquisition channel gain.

The frequency overlapped-resistable filter is used to filter out the interference signal that signal intermediate frequency rate is more than 1/2 sample frequency, by outside passband High-frequency signal be substantially filtered out, prevent gather signal frequency spectrum produce aliasing.Frequency overlapped-resistable filter is from MAXIM companies MAX293, the chip are 8 rank ellipse switching capacity low pass filters, and operating voltage is ± 5V.Can be by reference to clock setting The cut-off frequency of wave filter, the relation between reference clock and cut-off frequency are 50:1, the cut-off frequency of frequency overlapped-resistable filter is 4kHz, reference clock 200kHz.Hardware need not be changed, changes the reference clock frequency of PLD output, i.e., The cut-off frequency of each path filter can be changed.

Output smoothing wave filter uses 2 rank Butterworth LPFs, the cut-off frequency of Butterworth LPF For 10kHz, modulated interferer signal caused by SCF is filtered out.

Analog-digital conversion circuit as described include 6 passages, 16, high speed, low-power consumption, successive approximation A/D converter, sample rate Up to 250kbps, supply voltage ± 5V~± 15V.Can in a manner of parallel and serial with external circuitses interface, output signal Compatible 3.3V or 5V level.

The PLD (FPGA) uses XC4VLX25 chips, is set by PLD programmable The multiplication factor of amplifier, output switch capacitive filter reference clock.PLD master clock is 24.576MHz. The controlling of sampling register that PLD is set according to DSP, including sampling length, sample frequency etc., output A/D conversions Control sequential, and transformation result is read by SPI interface and is stored in internal data buffering area.

Referring to Fig. 3, multi-channel Vibration Signal synchronizes collection, first, FPGA is sent out to A/D conversion chips respective channel Go out to start conversion/CONVST signals, A/D conversion chips start to change, BUSY pins output high level, when FPGA detects BUSY When pin is low level, this A/D is converted.Data time sequence is read in FPGA outputs, and transformation result is read by SPI interface In FPGA data buffering area.

Data buffer zone by BlocKRAM examples metaplasia inside FPGA into, the vibration data spatial cache of each passage is 2kB, By double-port access, it is divided into 2 areas, using ping-pong operation.Avoid front-end collection interface and DSP access conflicts.Gather at 128 points Afterwards, FPGA puts this bag data collection complement mark in status register, and DSP fetches according to and carried out whole according to status register reads Reason.

IRIG-B time scale informations carry out Accumulating generation by FPGA to the synchronised clock of input.When markers reset signal is high electricity Usually, FPGA carries out accumulated counts to synchronizing clock signals, and when reset clock signal is high level, count value is reset.DSP When reading vibration data from PLD, current time scale information is obtained, according to IRIG-B form collator packets.Cause Synchronised clock used in switches other with the collection of airborne record system, analog signal is same source, therefore can be ensured more Correlation between kind data.

The DSP is high performance fixed-point DSP, has CPCI interfaces, completes task scheduling, data acquisition and processing (DAP) work. When upper electric, DSP initializes according to airborne configuration to vibration signals collecting interface, and during normal work, cyclic polling can be compiled Status register in journey logical device, when PLD completes a vibration signal sampling period, DSP is from programmable Logical device reads sampled data, according to IRIG-B form collator packets, and by data in the way of circulating and storing, write-in CPCI mapping spaces, while write pointer address is updated, when data management module has determined new data renewal, pass through CPCI interfaces Read data.Data recording equipment is sent by data management module to be recorded.

The CPCI interfaces, meet the bus specifications of PCI 2.2, when upper electric, by the initial CPCI interfaces of data management module, PCI space is mapped to memory headroom by DSP by EMIF interfaces.During normal work, DSP interrupts according to 1ms cyclic pollings CPCI Mark, obtain data management module order, including self-test, data acquisition, program loading etc..The DSP cycles write vibration data CPCI spaces, and refresh flags are updated the data, data management module obtains vibration data by CPCI interfaces.

For DSP according to IRIG-B form collator vibration datas, IRIG-B is the interface that the standard that defines was downloaded and managed to data File, time bag, high-precision absolute time and relative time are supported, the temporal correlation of retrieval data can be wrapped passage time.Adopt With IRIG-B form collator vibration datas, the temporal correlation of each systematic parameter is ensure that, in analyze data, can determine that each system The order and each systematic parameter that system event occurs change with time situation.The markers precision of vibration data can reach 1ms, full The data analysis requirement of the foot overwhelming majority.

When each passage collects at 1024, DSP is analyzed the channel data, and the spy of vibration signal is calculated Levy frequency and amplitude.Described data processing method includes：Synchronous time average algorithm, windowing algorithm, spectrum analysis.

Synchronous time average method is the process of the extracting cycle signal from the signal for be mixed with noise jamming.It is with certain week Phase is interval intercept signal, the signal segment superposed average that then will be intercepted, eliminates the aperiodic component in signal and does at random Disturb, retain the periodic component of determination.

Described windowing algorithm, it is before to vibration data spectrum analysis, process of convolution is carried out to data using Hanning window, The frequency as caused by rectangular window is avoided to reveal.Described spectrum analysis, it is to be transformed into vibration signal from time domain using fft algorithm Frequency domain, obtain the characteristic frequency of vibration signal and corresponding amplitude.And judge that parts are current according to appropriate fault diagnosis model Working condition.

Claims (8)

1. A kind of 1. vibration signals collecting circuit, it is characterised in that：Lead to including some vibrating sensor interface circuits, signal condition Road, analog to digital conversion circuit, PLD and DSP, wherein, the corresponding one group of vibration letter of vibration signal conditioning passage Number, the vibration signal conditioning passage is all connected on analog to digital conversion circuit, and analog to digital conversion circuit is connected to FPGA On device, and the PLD is connected with DSP, wherein, the signal conditioning circuit is filtered by the high pass being sequentially connected Wave circuit, voltage follower circuit, pga circuit, Anti-aliasing Filter Circuits and smoothed filter circuit composition, it is described anti-mixed Folded filter circuit reference clock pin is connected to the clock module in PLD.
2. 2. vibration signals collecting circuit according to claim 1, it is characterised in that：The vibrating sensor interface circuit is Constant current source driving circuit, the high-pass filtering circuit are 1 rank RC filter circuits.
3. 3. vibration signals collecting circuit according to claim 1, it is characterised in that：Pga circuit is patrolled with programmable Device connection is collected, gain is set by PLD.
4. 4. vibration signals collecting circuit according to claim 1, it is characterised in that：The Anti-aliasing Filter Circuits use 8 Rank SCF, cut-off frequency is by reference to clock setting.
5. 5. vibration signals collecting circuit according to claim 1, it is characterised in that：Output smoothing filtering uses 2 rank Barts Butterworth wave filter.
6. 6. vibration signals collecting circuit according to claim 1, it is characterised in that：Analog-digital conversion circuit as described includes 6 tunnels 16 separate successive approximation A/D converters.
7. 7. vibration signals collecting circuit according to claim 1, it is characterised in that：The PLD includes mould Number conversion and control tfi module, clock module, control register, status register and data cache module, wherein, modulus turns Control sequential module connection analog-digital converter is changed, and is connected respectively with control register and status register, and control register DSP is connected with status register, data cache module is connected with analog-digital converter and DSP respectively.
8. 8. vibration signals collecting circuit according to claim 1, it is characterised in that：The DSP has CPCI interfaces, passes through CPCI exchanges data with data management module.