CN206595264U - One kind passivation contact all back-contact electrodes solar battery structure - Google Patents
One kind passivation contact all back-contact electrodes solar battery structure Download PDFInfo
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Abstract
The utility model discloses one kind passivation contact all back-contact electrodes solar battery structure, its structure includes silicon chip substrate, in silicon chip substrate front, pyramid matte is set, the silicon chip substrate back side forms burnishing surface, at the silicon chip substrate back side, tunneling oxide layer is set, N-type polycrystalline silicon layer and p-type polysilicon layer are alternately arranged on tunneling oxide layer, kept apart in the middle of N-type polycrystalline silicon layer and p-type polysilicon layer by intrinsically polysilicon layer, corresponding N areas Metal contact electrode and P areas Metal contact electrode are set respectively on N-type polycrystalline silicon floor and p-type polysilicon floor.As another improved structure, backside passivation film can be set, and set N area's Metal contact electrodes and P areas Metal contact electrode in opening contact hole thereon.Technical solutions of the utility model are applied to full back electrode cell by contact means are passivated, and can greatly reduce recombination-rate surface, particularly metal contact zone recombination rate, open-circuit voltage are lifted, so as to lift battery efficiency.
Description
Technical field
The utility model is related to technical field of solar batteries, more particularly to a kind of passivation contact all back-contact electrodes solar cell
Structure.
Background technology
Solar cell, as a kind of clean energy resource, is new energy, and can be restructured the use of energy, and its eternal developing direction is
Improve efficiency and reduce cost.
The preparation flow of all back-contact electrodes solar cell is complicated, mainly complicated back-patterned process, is related to repeatedly
Mask and diffusion process.Localization diffusion is carried out generally by patterned oxidation mask.The graphical needs of mask are used
Silk-screen printing or laser technology, add processing step.The height of battery open circuit voltage depends on the quality of passivation effect, at present
General full back electrode cell is all to use AlOx、SiNxOr SiO2Passivating back is carried out Deng membrane structure.This passivating structure
Recombination-rate surface can be reduced, the lifting of split pressure has certain help.But, want to develop toward higher open-circuit voltage,
Such a passivating technique also encounters bottleneck, the particularly recombination rate of metal contact zone greatly, limits the lifting of battery efficiency.
Utility model content
The purpose of this utility model is to provide a kind of passivation contact all back-contact electrodes solar battery structure, advantageously reduces passivation
Area and metal contact zone recombination rate, lifting open-circuit voltage and battery efficiency.
To achieve the above object, the utility model provides a kind of passivation contact all back-contact electrodes solar battery structure, including
Silicon chip substrate, pyramid matte is set in silicon chip substrate front, and the silicon chip substrate back side forms burnishing surface, set at the silicon chip substrate back side
Tunneling oxide layer is put, N-type polycrystalline silicon layer and p-type polysilicon layer, N-type polycrystalline silicon layer and p-type are alternately arranged on tunneling oxide layer
Kept apart in the middle of polysilicon layer by intrinsically polysilicon layer, set corresponding respectively on N-type polycrystalline silicon layer and p-type polysilicon layer
N areas Metal contact electrode and P areas Metal contact electrode.
Further improvement is that, set the back side blunt in N-type polycrystalline silicon layer, p-type polysilicon layer and intrinsically polysilicon layer
Change film, overleaf the position of correspondence N areas Metal contact electrode is provided with N areas contact hole on passivating film, overleaf right on passivating film
Answer the position of P areas Metal contact electrode to be provided with P areas contact hole, then the metal contact of corresponding N areas is set in N areas contact hole
Electrode, sets corresponding P areas Metal contact electrode in P areas contact hole, and N areas are stretched out in the upper end of N areas Metal contact electrode
P areas contact hole is stretched out in contact hole, the upper end of P areas Metal contact electrode, and wherein passivating back membrane structure is AlOx/SiNxOr
SiO2/AlOx/SiNxStack membrane combination.
Further, the silicon chip substrate is to be additionally provided with front-surface field on N-type silicon chip substrate, pyramid matte,
Front passivated reflection reducing membrane is set on the outside of front-surface field.
Wherein preferred, the thickness of tunneling oxide layer is 0.5-5nm, and polysilicon layer thicknesses are 20-300nm.
One of which passivation contact all back-contact electrodes solar cell preparation method, comprises the following steps：
1）Pre-treatment is carried out to n type single crystal silicon piece substrate, it is pyramid matte to form front, the back side is the one side of burnishing surface
Polish making herbs into wool structure；
2）Tunneling oxide layer growth is carried out to the silicon chip Jing Guo pre-treatment, thermal oxide layer is grown by boiler tube mode, or
Wet oxidation layer is grown by Ozone Water, or grown by chemical method, tunneling oxide layer thickness is 0.5-5nm；
3）Intrinsic amorphous silicon layer or polysilicon layer, intrinsic amorphous silicon layer are overleaf grown using LPCVD or PECVD methods
Or polysilicon layer thicknesses are 20-300nm；
4）Phosphorus is injected using ion injection method on the pyramid matte of front, as front-surface field, or passes through boiler tube
Diffusion, APCVD methods are formed, and sheet resistance is 100-1000 Ω/；
5）The place to form p-type polysilicon layer doped region is overleaf needed to carry out boron injection, boron is injected by silicon chip
Top sets the mask of correspondence figure to realize that local injects；
6）The place to form N-type polycrystalline silicon layer doped region is overleaf needed to carry out phosphorus injection, phosphorus is injected by silicon chip
Top sets the mask with correspondence figure to realize that local injects, and the mask graph that boron injects and phosphorus injects is in alternately row
Row, are formed by mask graph and are injected and the undoped region in the middle of phosphorus injection zone, i.e. intrinsically polysilicon layer between boron
Region；
7）Silicon chip substrate by three injections is made annealing treatment altogether, makes amorphous crystallization of silicon into polysilicon, notes simultaneously
Enter foreign atom and diffuse into polysilicon layer；
8）Silicon chip substrate Jing Guo common annealing is cleaned, passivating film, passivation film structure is then overleaf formed
For AlOx/SiNxOr SiO2/AlOx/SiNxStack membrane combination, front formed front passivated reflection reducing membrane, structure be individual layer or
Lamination SiNx, or SiO2/SiNx/SiNxOyStack membrane combination；
9）Perforate processing is carried out to backside passivation film, perforate processing is carried out in P areas and N areas, output respectively P areas contact hole and
N areas contact hole；
10）Corresponding P areas Metal contact electrode and N areas metal contact electricity are prepared on P areas contact hole and N areas contact hole
Pole.
Wherein, the contact hole in backside passivation film, by laser, the mode of etching slurry or stop slurry is formed.
It is preferred that, N areas Metal contact electrode and P areas Metal contact electrode, including respective thin grid line and main gate line, use
In layer of metal design or double-layer metallization design, wherein layer of metalization design, thin grid line is segmented, close to opposite
Disconnected near the main gate line of polarity, break distance is 0.05-0.3mm, main grid demand pairs are 2-20 pairs；Double-layer metallization is designed
In, thin grid line is not segmented, and is isolated by the way that insulating barrier is provided below in main gate line, and insulating barrier is line segment structure, positioned at main gate line
On the thin grid line of lower section opposite polarity, the thin grid line of opposite polarity is covered, the purpose of isolation is reached, main grid demand pairs are 2-10
It is right；N areas Metal contact electrode and P areas Metal contact electrode are by silk-screen printing, and plating, or method of evaporating are made.
It can also be first to use that N-type and p-type polysilicon layer preparation method are overleaf alternately arranged on tunneling oxide layer
LPCVD or PECVD methods overleaf grow intrinsic amorphous silicon layer or polysilicon layer；In intrinsic amorphous silicon layer or polysilicon layer
Upper use thermal oxide or APCVD depositions prepare first time silicon oxide masking film layer；First time silicon oxide masking film layer is carried out for the first time
Graphical treatment, reserving needs to carry out boron doped part；Boron diffusing, doping is carried out, the pyroprocess of boron diffusion is simultaneously so that non-
Crystal silicon crystallization, becomes polysilicon；First time silicon oxide masking film layer is removed, then is prepared second using thermal oxide or APCVD depositions
Silicon oxide masking film layer；Second of graphical treatment is carried out to second of silicon oxide masking film layer, the portion for needing to carry out phosphorus doping is reserved
Point；Carry out phosphorus diffusion doping；Second of silicon oxide masking film layer is removed, N-type and the p-type polysilicon layer being alternately arranged.
It can also be first to use that N-type and p-type polysilicon layer preparation method are overleaf alternately arranged on tunneling oxide layer
LPCVD or PECVD methods overleaf grow intrinsic amorphous silicon layer or polysilicon layer；In intrinsic amorphous silicon layer or polysilicon layer
Upper local prints boron slurry, is used as p type island region；Local prints phosphorus slurry in intrinsic amorphous silicon layer or polysilicon layer, is used as N-type
Area, wherein p type island region and N-type region are alternately arranged, and centre is kept apart by intrinsic amorphous silicon layer or polysilicon layer；To printing
The silicon chip that boron is starched and phosphorus is starched is made annealing treatment, and makes amorphous crystallization of silicon into polysilicon, while boron and phosphorus atoms are toward expansion in polysilicon
Dissipate, complete doping.
It can also be to use LPCVD that N-type and p-type polysilicon layer preparation method are overleaf alternately arranged on tunneling oxide layer
Or PECVD methods overleaf grow the p-type or N-type non-crystalline silicon layer or polysilicon layer of doping in situ；The p-type adulterated in the original location or
First time silica or silicon nitride mask layer are prepared in N-type non-crystalline silicon layer or polysilicon layer；The is carried out to first time mask layer
Graphical treatment, removes the doped amorphous silicon layer outside mask protection, obtain doping in situ p-type or N-type non-crystalline silicon or
Polysilicon region；One layer of tunneling oxide layer is regrowed, and using the N-type or P of LPCVD or PECVD methods growth doping in situ
Type amorphous silicon layer or polysilicon layer, this secondary growth doped layer are opposite with first time doping channel type；Regrow second of oxygen
SiClx or silicon nitride mask layer, and second of graphical place of doped amorphous silicon layer or polysilicon layer progress to the second secondary growth
Reason and etching, obtain the N-type or P-type non-crystalline silicon or polysilicon region of doping in situ；Remove mask layer, and being annealed twice
Processing, regulation doping curve, while making amorphous crystallization of silicon, obtains N-type and the p-type polycrystalline being alternately arranged on the tunneling oxide layer of the back side
Silicon layer.
All back-contact electrodes solar cell is recognized extensively as a kind of high-efficiency solar cell structure, its high efficiency prospect.Closely
Come, the development of passivation contact technique causes each major company and research institute to have an optimistic view of application of the technology on solar cell one after another.Cause
This, all back-contact electrodes solar cell is combined with passivation contact, will be a very promising developing direction.By being passivated contact
Technology, can greatly reduce the compound of each region, significantly improve battery open circuit voltage, add full back electrode cell front without screening
The electric current advantage of gear, its efficiency improvement potential is huge.
Technical solutions of the utility model are applied to full back electrode cell by contact means are passivated, and can greatly reduce surface
Recombination rate, particularly metal contact zone recombination rate, lift open-circuit voltage, so as to lift battery efficiency.
What technical solutions of the utility model were brought has the beneficial effect that：By all back-contact electrodes solar cell and passivation contact technique
It is combined together, by one layer of tunneling oxide layer and the p-type being alternately arranged thereon and n-type doping polysilicon layer, obtains more current
The more excellent inactivating performance of common passivation technology.Passivation contact all back-contact electrodes solar cell described in the utility model, carrier
Corresponding doped polysilicon layer is entered by one layer of tunneling oxide layer tunnel and carries out selective transmission and collection.The p-type of doping is more
Crystal silicon and N-type polycrystalline silicon carry out selective transmission to hole and electronics respectively, then are collected by correspondence p-type and N-type electrode.
The excellent inactivating performance of polysilicon can greatly reduce the compound of metal contact zone, and lifting battery opens pressure and efficiency.
Brief description of the drawings
Fig. 1 is the structural representation of the utility model embodiment one；
Fig. 2 is the structural representation of the utility model embodiment two；
Fig. 3 is the structural representation of the utility model embodiment three；
Wherein, 1- silicon chip substrates, 2- pyramid mattes, 3- tunneling oxide layers, 4-N type polysilicon layers, 5-P type polysilicons
Layer, 6- polysilicon layers, 7-N areas Metal contact electrode, 8-P areas Metal contact electrode, 9-N areas contact hole, 10- backside passivation films,
11-P areas contact hole, 12- front-surface fields, 13- fronts passivated reflection reducing membrane.
Embodiment
Describe optimal technical scheme of the present utility model in detail below in conjunction with the accompanying drawings.
Embodiment one
As shown in figure 1, a kind of passivation contact all back-contact electrodes solar battery structure of the present utility model, including silicon chip substrate 1,
Pyramid matte 2 is set in the front of silicon chip substrate 1, the back side of silicon chip substrate 1 forms burnishing surface, sets and satisfies at the back side of silicon chip substrate 1
Oxide layer 3 is worn, N-type polycrystalline silicon layer 4 and p-type polysilicon layer 5, N-type polycrystalline silicon layer 4 and p-type are alternately arranged on tunneling oxide layer 3
Kept apart in the middle of polysilicon layer 5 by intrinsically polysilicon layer 6, setting pair respectively on N-type polycrystalline silicon layer 4 and p-type polysilicon layer 5
The N areas Metal contact electrode 7 and P areas Metal contact electrode 8 answered.
The silicon chip substrate 1 is to be additionally provided with front-surface field 12 on N-type silicon chip substrate, pyramid matte 2, in front-surface field
12 outsides set front passivated reflection reducing membrane 13.
Wherein preferred, the thickness of tunneling oxide layer 3 is 0.5-5nm, and the thickness of polysilicon layer 6 is 20-300nm.
Embodiment two
As shown in Fig. 2 a kind of passivation contact all back-contact electrodes solar battery structure of the present utility model, including silicon chip substrate 1,
Pyramid matte 2 is set in the front of silicon chip substrate 1, the back side of silicon chip substrate 1 forms burnishing surface, sets and satisfies at the back side of silicon chip substrate 1
Oxide layer 3 is worn, N-type polycrystalline silicon layer 4 and p-type polysilicon layer 5, N-type polycrystalline silicon layer 4 and p-type are alternately arranged on tunneling oxide layer 3
Kept apart in the middle of polysilicon layer 5 by intrinsically polysilicon layer 6, setting pair respectively on N-type polycrystalline silicon layer 4 and p-type polysilicon layer 5
The N areas Metal contact electrode 7 and P areas Metal contact electrode 8 answered.
Further, backside passivation film is set in N-type polycrystalline silicon layer 4, p-type polysilicon layer 5 and intrinsically polysilicon layer 6
10, overleaf the position of correspondence N areas Metal contact electrode 7 is provided with N areas contact hole 9 on passivating film 10, overleaf passivating film 10
The position of upper correspondence P areas Metal contact electrode 8 is provided with P areas contact hole 11, and corresponding N areas are then set in N areas contact hole 9
Metal contact electrode 7, sets corresponding P areas Metal contact electrode 8, and N areas Metal contact electrode 7 in P areas contact hole 11
Upper end stretch out N areas contact hole 9, P areas contact hole 11, the wherein knot of backside passivation film 10 are stretched out in the upper end of P areas Metal contact electrode 8
Structure is AlOx/SiNxOr SiO2/AlOx/SiNxStack membrane combination.
Further, the silicon chip substrate 1 is to be additionally provided with front-surface field on N-type silicon chip substrate, pyramid matte 2
12, in the outside of front-surface field 12, front passivated reflection reducing membrane 13 is set.
Wherein preferred, the thickness of tunneling oxide layer 3 is 0.5-5nm, and the thickness of polysilicon layer 6 is 20-300nm.
Embodiment three
As shown in figure 3, a kind of passivation contact all back-contact electrodes solar battery structure of the present utility model, including silicon chip substrate 1,
Pyramid matte 2 is set in the front of silicon chip substrate 1, the back side of silicon chip substrate 1 forms burnishing surface, sets and satisfies at the back side of silicon chip substrate 1
Oxide layer 3 is worn, N-type polycrystalline silicon layer 4 and p-type polysilicon layer 5, N-type polycrystalline silicon layer 4 and p-type are alternately arranged on tunneling oxide layer 3
Kept apart in the middle of polysilicon layer 5 by intrinsically polysilicon layer 6, setting pair respectively on N-type polycrystalline silicon layer 4 and p-type polysilicon layer 5
The N areas Metal contact electrode 7 and P areas Metal contact electrode 8 answered.
Further, backside passivation film is set in N-type polycrystalline silicon layer 4, p-type polysilicon layer 5 and intrinsically polysilicon layer 6
10, overleaf the position of correspondence N areas Metal contact electrode 7 is provided with N areas contact hole 9 on passivating film 10, overleaf passivating film 10
The position of upper correspondence P areas Metal contact electrode 8 is provided with P areas contact hole 11, and corresponding N areas are then set in N areas contact hole 9
Metal contact electrode 7, sets corresponding P areas Metal contact electrode 8, and N areas Metal contact electrode 7 in P areas contact hole 11
Upper end stretch out N areas contact hole 9, P areas contact hole 11, the wherein knot of backside passivation film 10 are stretched out in the upper end of P areas Metal contact electrode 8
Structure is AlOx/SiNxOr SiO2/AlOx/SiNxStack membrane combination.
Wherein described silicon chip substrate 1 is to be additionally provided with front passivated reflection reducing membrane 13 on N-type silicon chip substrate, pyramid matte 2；
The thickness of tunneling oxide layer 3 is 0.5-5nm, and the thickness of polysilicon layer 6 is 20-300nm.
Front-surface field be it is optional, can also be without, thus in some embodiments comprising front-surface field and
The technique for preparing front-surface field.
Preparation method wherein for embodiment one comprises the following steps：
1）Pre-treatment is carried out to n type single crystal silicon piece substrate, it is pyramid matte to form front, the back side is the one side of burnishing surface
Polish making herbs into wool structure；
2）Tunneling oxide layer growth is carried out to the silicon chip Jing Guo pre-treatment, thermal oxide layer is grown by boiler tube mode, or
Wet oxidation layer is grown by Ozone Water, or grown by chemical method, tunneling oxide layer thickness is 0.5-5nm；
3）Intrinsic amorphous silicon layer or polysilicon layer, intrinsic amorphous silicon layer are overleaf grown using LPCVD or PECVD methods
Or polysilicon layer thicknesses are 20-300nm；
4）Phosphorus is injected using ion injection method on the pyramid matte of front, as front-surface field, or passes through boiler tube
Diffusion, APCVD methods are formed, and sheet resistance is 100-1000 Ω/；
5）The place to form p-type polysilicon layer doped region is overleaf needed to carry out boron injection, boron is injected by silicon chip
Top sets the mask of correspondence figure to realize that local injects；
6）The place to form N-type polycrystalline silicon layer doped region is overleaf needed to carry out phosphorus injection, phosphorus is injected by silicon chip
Top sets the mask with correspondence figure to realize that local injects, and the mask graph that boron injects and phosphorus injects is in alternately row
Row, are formed by mask graph and are injected and the undoped region in the middle of phosphorus injection zone, i.e. intrinsically polysilicon layer between boron
Region；
7）Silicon chip substrate by three injections is made annealing treatment altogether, makes amorphous crystallization of silicon into polysilicon, notes simultaneously
Enter foreign atom and diffuse into polysilicon layer；
8）Prepared on the front-surface field of front and form front passivated reflection reducing membrane, structure is individual layer or lamination SiNx, or
SiO2/SiNx/SiNxOyStack membrane combination；
9）Corresponding P areas Metal contact electrode and the contact of N areas metal are prepared on p-type polysilicon floor and N-type polycrystalline silicon floor
Electrode.
Preparation method wherein for embodiment two comprises the following steps：
1）Pre-treatment is carried out to n type single crystal silicon piece substrate, it is pyramid matte to form front, the back side is the one side of burnishing surface
Polish making herbs into wool structure；
2）Tunneling oxide layer growth is carried out to the silicon chip Jing Guo pre-treatment, thermal oxide layer is grown by boiler tube mode, or
Wet oxidation layer is grown by Ozone Water, or grown by chemical method, tunneling oxide layer thickness is 0.5-5nm；
3）Intrinsic amorphous silicon layer or polysilicon layer, intrinsic amorphous silicon layer are overleaf grown using LPCVD or PECVD methods
Or polysilicon layer thicknesses are 20-300nm；
4）Phosphorus is injected using ion injection method on the pyramid matte of front, as front-surface field, or passes through boiler tube
Diffusion, APCVD methods are formed, and sheet resistance is 100-1000 Ω/；
5）The place to form p-type polysilicon layer doped region is overleaf needed to carry out boron injection, boron is injected by silicon chip
Top sets the mask of correspondence figure to realize that local injects；
6）The place to form N-type polycrystalline silicon layer doped region is overleaf needed to carry out phosphorus injection, phosphorus is injected by silicon chip
Top sets the mask with correspondence figure to realize that local injects, and the mask graph that boron injects and phosphorus injects is in alternately row
Row, are formed by mask graph and are injected and the undoped region in the middle of phosphorus injection zone, i.e. intrinsically polysilicon layer between boron
Region；
7）Silicon chip substrate by three injections is made annealing treatment altogether, makes amorphous crystallization of silicon into polysilicon, notes simultaneously
Enter foreign atom and diffuse into polysilicon layer；
8）Silicon chip substrate Jing Guo common annealing is cleaned, passivating film, passivation film structure is then overleaf formed
For AlOx/SiNxOr SiO2/AlOx/SiNxStack membrane combination, front formed front passivated reflection reducing membrane, structure be individual layer or
Lamination SiNx, or SiO2/SiNx/SiNxOyStack membrane combination；
9）Perforate processing is carried out to backside passivation film, perforate processing is carried out in P areas and N areas, output respectively P areas contact hole and
Contact hole in N areas contact hole, backside passivation film, by laser, the mode of etching slurry or stop slurry is formed；
10）Corresponding P areas Metal contact electrode and N areas metal contact electricity are prepared on P areas contact hole and N areas contact hole
Pole.
Preparation method wherein for embodiment three comprises the following steps：
1）Pre-treatment is carried out to n type single crystal silicon piece substrate, it is pyramid matte to form front, the back side is the one side of burnishing surface
Polish making herbs into wool structure；
2）Tunneling oxide layer growth is carried out to the silicon chip Jing Guo pre-treatment, thermal oxide layer is grown by boiler tube mode, or
Wet oxidation layer is grown by Ozone Water, or grown by chemical method, tunneling oxide layer thickness is 0.5-5nm；
3）Intrinsic amorphous silicon layer or polysilicon layer, intrinsic amorphous silicon layer are overleaf grown using LPCVD or PECVD methods
Or polysilicon layer thicknesses are 20-300nm；
4）First time silica is prepared in intrinsic amorphous silicon layer or polysilicon layer using thermal oxide or APCVD depositions to cover
Film layer；
5）First time graphical treatment is carried out to first time silicon oxide masking film layer, reserving needs to carry out boron doped part；
6）Boron diffusing, doping is carried out, the pyroprocess of boron diffusion causes amorphous crystallization of silicon, becomes polysilicon simultaneously；
7）First time silicon oxide masking film layer is removed, then second of silicon oxide masking film is prepared using thermal oxide or APCVD depositions
Layer；
8）Second of graphical treatment is carried out to second of silicon oxide masking film layer, the part for needing to carry out phosphorus doping is reserved；
9）Carry out phosphorus diffusion doping；
10）Second of silicon oxide masking film layer is removed, N-type and the p-type polysilicon layer being alternately arranged；
11）Front passivated reflection reducing membrane is formed on the pyramid matte of front, structure is individual layer or lamination SiNx, or SiO2/
SiNx/SiNxOyStack membrane combination, overleaf form passivating film, passivation film structure is AlOx/SiNxOr SiO2/AlOx/SiNx
Stack membrane combination；
12）Perforate processing is carried out to backside passivation film, perforate processing is carried out in P areas and N areas, P areas contact hole is outputed respectively
With N areas contact hole, the contact hole in backside passivation film, by laser, etching slurry or stops that the mode of slurry is formed；
13）Corresponding P areas Metal contact electrode and N areas metal contact electricity are prepared on P areas contact hole and N areas contact hole
Pole.
Preparation method wherein for embodiment three can also be to comprise the following steps：
1）Pre-treatment is carried out to n type single crystal silicon piece substrate, it is pyramid matte to form front, the back side is the one side of burnishing surface
Polish making herbs into wool structure；
2）Tunneling oxide layer growth is carried out to the silicon chip Jing Guo pre-treatment, thermal oxide layer is grown by boiler tube mode, or
Wet oxidation layer is grown by Ozone Water, or grown by chemical method, tunneling oxide layer thickness is 0.5-5nm；
3）Intrinsic amorphous silicon layer or polysilicon layer, intrinsic amorphous silicon layer are overleaf grown using LPCVD or PECVD methods
Or polysilicon layer thicknesses are 20-300nm；
4）Local prints boron slurry in intrinsic amorphous silicon layer or polysilicon layer, is used as p type island region；
5）Local prints phosphorus slurry in intrinsic amorphous silicon layer or polysilicon layer, is used as N-type region, wherein p type island region and N-type
Area is alternately arranged, and centre is kept apart by intrinsic amorphous silicon layer or polysilicon layer；
6）The silicon chip for printing boron slurry and phosphorus slurry is made annealing treatment, makes amorphous crystallization of silicon into polysilicon, at the same boron with
Phosphorus atoms complete doping toward diffusion in polysilicon；
7）Front passivated reflection reducing membrane is formed on the pyramid matte of front, structure is individual layer or lamination SiNx, or SiO2/
SiNx/SiNxOyStack membrane combination, overleaf form passivating film, passivation film structure is AlOx/SiNxOr SiO2/AlOx/SiNx
Stack membrane combination；
8）Perforate processing is carried out to backside passivation film, perforate processing is carried out in P areas and N areas, output respectively P areas contact hole and
Contact hole in N areas contact hole, backside passivation film, by laser, the mode of etching slurry or stop slurry is formed；
9）Corresponding P areas Metal contact electrode and N areas Metal contact electrode are prepared on P areas contact hole and N areas contact hole.
Preparation method wherein for embodiment three can also be to comprise the following steps：
1）Pre-treatment is carried out to n type single crystal silicon piece substrate, it is pyramid matte to form front, the back side is the one side of burnishing surface
Polish making herbs into wool structure；
2）Tunneling oxide layer growth is carried out to the silicon chip Jing Guo pre-treatment, thermal oxide layer is grown by boiler tube mode, or
Wet oxidation layer is grown by Ozone Water, or grown by chemical method, tunneling oxide layer thickness is 0.5-5nm；
3）The p-type or N-type non-crystalline silicon layer or polysilicon of doping in situ are overleaf grown using LPCVD or PECVD methods
Layer, amorphous silicon layer or polysilicon layer thicknesses are 20-300nm；
4）First time silica or silicon nitride are prepared in the p-type or N-type non-crystalline silicon layer or polysilicon layer adulterated in the original location
Mask layer；
5）To first time mask layer carry out first time graphical treatment, remove mask protection outside doped amorphous silicon layer or
Polysilicon layer, obtains the p-type or N-type non-crystalline silicon or polysilicon region of doping in situ；
6）One layer of tunneling oxide layer is regrowed, and using the N-type or p-type of LPCVD or PECVD methods growth doping in situ
Amorphous silicon layer or polysilicon layer, this secondary growth doped layer are opposite with first time doping channel type；
7）Regrow second of silica or silicon nitride mask layer, and doped amorphous silicon layer to the second secondary growth or
Polysilicon layer carries out second of graphical treatment and etching, obtains N-type or P-type non-crystalline silicon or the multi-crystal silicon area of doping in situ
Domain；
8）Mask layer, and being made annealing treatment twice is removed, regulation doping curve, while making amorphous crystallization of silicon, is carried on the back
N-type and the p-type polysilicon layer being alternately arranged on the tunneling oxide layer of face；
9）Front passivated reflection reducing membrane is formed on the pyramid matte of front, structure is individual layer or lamination SiNx, or SiO2/
SiNx/SiNxOyStack membrane combination, overleaf form passivating film, passivation film structure is AlOx/SiNxOr SiO2/AlOx/SiNx
Stack membrane combination；
10）Perforate processing is carried out to backside passivation film, perforate processing is carried out in P areas and N areas, P areas contact hole is outputed respectively
With N areas contact hole, the contact hole in backside passivation film, by laser, etching slurry or stops that the mode of slurry is formed；
11）Corresponding P areas Metal contact electrode and N areas metal contact electricity are prepared on P areas contact hole and N areas contact hole
Pole.
It is preferred that, N areas Metal contact electrode and P areas Metal contact electrode, including respective thin grid line and main gate line, use
In layer of metal design or double-layer metallization design, wherein layer of metalization design, thin grid line is segmented, close to opposite
Disconnected near the main gate line of polarity, break distance is 0.05-0.3mm, main grid demand pairs are 2-20 pairs；Double-layer metallization is designed
In, thin grid line is not segmented, and is isolated by the way that insulating barrier is provided below in main gate line, and insulating barrier is line segment structure, positioned at main gate line
On the thin grid line of lower section opposite polarity, the thin grid line of opposite polarity is covered, the purpose of isolation is reached, main grid demand pairs are 2-10
It is right；N areas Metal contact electrode and P areas Metal contact electrode are by silk-screen printing, and plating, or method of evaporating are made.
All back-contact electrodes solar cell is recognized extensively as a kind of high-efficiency solar cell structure, its high efficiency prospect.Closely
Come, the development of passivation contact technique causes each major company and research institute to have an optimistic view of application of the technology on solar cell one after another.Cause
This, all back-contact electrodes solar cell is combined with passivation contact, will be a very promising developing direction.By being passivated contact
Technology, can greatly reduce the compound of each region, significantly improve battery open circuit voltage, add full back electrode cell front without screening
The electric current advantage of gear, its efficiency improvement potential is huge.
Technical solutions of the utility model are applied to full back electrode cell by contact means are passivated, and can greatly reduce surface
Recombination rate, particularly metal contact zone recombination rate, lift open-circuit voltage, so as to lift battery efficiency.
What technical solutions of the utility model were brought has the beneficial effect that：By all back-contact electrodes solar cell and passivation contact technique
It is combined together, by one layer of tunneling oxide layer and the p-type being alternately arranged thereon and n-type doping polysilicon layer, obtains more current
The more excellent inactivating performance of common passivation technology.Passivation contact all back-contact electrodes solar cell described in the utility model, carrier
Corresponding doped polysilicon layer is entered by one layer of tunneling oxide layer tunnel and carries out selective transmission and collection.The p-type of doping is more
Crystal silicon and N-type polycrystalline silicon carry out selective transmission to hole and electronics respectively, then are collected by correspondence p-type and N-type electrode.
The excellent inactivating performance of polysilicon can greatly reduce the compound of metal contact zone, and lifting battery opens pressure and efficiency.
Claims (4)
1. one kind passivation contact all back-contact electrodes solar battery structure, it is characterised in that：Including silicon chip substrate, in silicon chip substrate front
Pyramid matte is set, and the silicon chip substrate back side forms burnishing surface, and tunneling oxide layer is set at the silicon chip substrate back side, in tunnel oxidation
It is alternately arranged on layer in the middle of N-type polycrystalline silicon layer and p-type polysilicon layer, N-type polycrystalline silicon layer and p-type polysilicon layer and passes through intrinsic polycrystalline
Silicon layer is kept apart, and sets corresponding N areas Metal contact electrode and P areas metal on N-type polycrystalline silicon floor and p-type polysilicon floor respectively
Contact electrode.
2. a kind of passivation contact all back-contact electrodes solar battery structure as claimed in claim 1, it is characterised in that：In N-type polycrystalline
Backside passivation film is set in silicon layer, p-type polysilicon layer and intrinsically polysilicon layer, overleaf correspondence N areas metal connects on passivating film
The position of touched electrode is provided with N areas contact hole, and overleaf the position of correspondence P areas Metal contact electrode is provided with P areas on passivating film
Contact hole, then sets corresponding N areas Metal contact electrode in N areas contact hole, and corresponding P areas are set in P areas contact hole
Metal contact electrode, and N areas contact hole is stretched out in the upper end of N areas Metal contact electrode, and the upper end of P areas Metal contact electrode is stretched out
P areas contact hole, wherein passivating back membrane structure are AlOx/SiNxOr SiO2/AlOx/SiNxStack membrane combination.
3. a kind of passivation contact all back-contact electrodes solar battery structure as claimed in claim 1 or 2, it is characterised in that：The silicon
Piece substrate is to be additionally provided with front-surface field on N-type silicon chip substrate, pyramid matte, sets front passivation to subtract on the outside of front-surface field
Anti- film.
4. a kind of passivation contact all back-contact electrodes solar battery structure as claimed in claim 1 or 2, it is characterised in that：Tunnel oxygen
The thickness for changing layer is 0.5-5nm, and polysilicon layer thicknesses are 20-300nm.
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| CN106876501A (en) * | 2017-03-10 | 2017-06-20 | 泰州乐叶光伏科技有限公司 | One kind passivation contact all back-contact electrodes solar battery structure and preparation method thereof |
| CN110061072A (en) * | 2019-04-08 | 2019-07-26 | 国家电投集团西安太阳能电力有限公司 | A kind of TBC solar battery structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106876501A (en) * | 2017-03-10 | 2017-06-20 | 泰州乐叶光伏科技有限公司 | One kind passivation contact all back-contact electrodes solar battery structure and preparation method thereof |
| CN110061072A (en) * | 2019-04-08 | 2019-07-26 | 国家电投集团西安太阳能电力有限公司 | A kind of TBC solar battery structure and preparation method thereof |
| CN111816727A (en) * | 2020-07-14 | 2020-10-23 | 普乐新能源科技(徐州)有限公司 | Interdigital back contact heterojunction solar cell based on LPCVD (low pressure chemical vapor deposition) high-efficiency amorphous silicon doping technology |
| CN112490304A (en) * | 2020-12-04 | 2021-03-12 | 东方日升（常州）新能源有限公司 | Preparation method of high-efficiency solar cell |
| CN115020534A (en) * | 2022-04-30 | 2022-09-06 | 常州时创能源股份有限公司 | Preparation method of back-side graphical N region of IBC battery |
| CN115020536A (en) * | 2022-04-30 | 2022-09-06 | 常州时创能源股份有限公司 | Preparation method of IBC battery graphical P region |
| CN115020535A (en) * | 2022-04-30 | 2022-09-06 | 常州时创能源股份有限公司 | Preparation method of back double-POLO structure of IBC battery |
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