CN206441739U - A kind of solar cell - Google Patents
A kind of solar cell Download PDFInfo
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- CN206441739U CN206441739U CN201621470544.5U CN201621470544U CN206441739U CN 206441739 U CN206441739 U CN 206441739U CN 201621470544 U CN201621470544 U CN 201621470544U CN 206441739 U CN206441739 U CN 206441739U
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- solar cell
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- grid
- pattern
- plasma reaction
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
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Abstract
This application discloses a kind of solar cell, RIE silicon chips are etched including plasma reaction, and PN junction diffusion layer, secondary gate pattern, antireflective coating and the main grid pattern set gradually in the front that plasma reaction etches RIE silicon chips, the main gate line in main grid pattern is mutually perpendicular to the secondary grid line in pair gate pattern.Prepare plasma reaction etching RIE silicon chips, PN junction diffusion layer is diffuseed to form on matte i.e. after dry etching, then one layer of secondary gate pattern is first printed in the surface of battery PN diffusion layers, i.e. without primary gate electrode, more preferable Ohmic contact is formed between enhancing silicon chip and metal grid lines, then coated with antireflection film again, is passivated the region not covered by grid line, secondly can also aoxidize the oxide included in the slurry that printing grid line is used；Finally printing carries main grid pattern, improves the depth-width ratio of main thin grid line, improves the ability for collecting carrier, the Ohmic contact between enhancing battery electrode and silicon chip, and main grid collect the effect confluxed, so as to improve the conversion efficiency of battery.
Description
Technical field
The utility model is related to field of photovoltaic technology, more specifically to a kind of solar cell.
Background technology
Solar energy is one of energy of current development, and absorbing solar energy using solar cell is converted to electric energy,
Traditional energy is substituted with very big potentiality and future.In various solar cells, silica-based solar cell is accounted for
The 90% of the total share in market.In silica-based solar cell preparation process, the preparation flow of conventional batteries is making herbs into wool-diffusion-quarter
Erosion-coated with antireflection film-silk-screen printing-sintering, however, higher production cost and inefficient always puzzlement silicon based cells development
Factor, the transformation efficiency and reduction production cost for improving solar cell are huge challenges that we face.
Therefore, reduction while battery conversion efficiency how is improved by changing battery pile face and battery structure to give birth to
Production cost is the anxious technical issues that need to address of those skilled in the art.
Utility model content
In order to solve the above technical problems, the utility model provides a kind of solar cell, the suede of solar cell is improved
Face structure, reduces the incident light loss to solar cell, and then improves the conversion efficiency of solar cell, reduces cost.
To achieve the above object, the utility model provides following technical scheme：
The utility model provides a kind of solar cell, including plasma reaction etching RIE silicon chips, and the grade from
PN junction diffusion layer, secondary gate pattern, antireflective coating and main grid pattern that the front of sub- reactive ion etching RIE silicon chips is set gradually, institute
The main gate line stated in main grid pattern is mutually perpendicular to the secondary grid line in the secondary gate pattern.
It is preferred that, in above-mentioned solar cell, the plasma reaction etching RIE silicon chips are what front surface was set gradually
The silicon chip of first matte layer and the second matte layer.
It is preferred that, in above-mentioned solar cell, the silicon chip is Buddha's warrior attendant wire cutting polysilicon chip.
It is preferred that, in above-mentioned solar cell, the thickness range of the Buddha's warrior attendant wire cutting polysilicon chip for 168nm~
212nm scopes, areal extent is 150mm*150mm~160mm*160mm.
It is preferred that, in above-mentioned solar cell, the antireflective coating is SixNyAntireflective coating, the SixNyAntireflective
The film thickness range of film is 75~85nm, and ranges of indices of refraction is 2.05~2.15.
It is preferred that, in above-mentioned solar cell, the bar number scope of the main gate line is 2~6, the bar of the secondary grid line
Number scope is 90~120.
It can be seen from the above technical proposal that there is provided a kind of solar cell, including plasma reaction etching RIE silicon
Piece, and set gradually in the front that the plasma reaction etches RIE silicon chips PN junction diffusion layer, secondary gate pattern, antireflective
Main gate line in film and main grid pattern, the main grid pattern is mutually perpendicular to the secondary grid line in the secondary gate pattern.
Prepare and diffuse to form PN junction diffusion layer, Ran Hou on plasma reaction etching RIE silicon chips, i.e., the matte after dry etching
One layer of secondary gate pattern is first printed in the surface of battery PN diffusion layers, i.e., without primary gate electrode, and diffusion, which has been etched, just directly prints secondary grid
Pattern, is that more preferable Ohmic contact is formed between silicon chip and metal grid lines in order to strengthen, because reflection is lower, battery pile face is concavo-convex
Pattern is more obvious, and the contact compatibility with slurry is poorer；Then coated with antireflection film again, is passivated the region not covered by grid line,
Secondly the oxide included in the slurry that printing grid line is used can also be aoxidized；Finally printing carries main grid pattern, in order to
The depth-width ratio of main thin grid line is improved, the ability for collecting carrier can be improved, strengthens the Ohmic contact between battery electrode and silicon chip,
And main grid collects the effect confluxed, so as to improve the conversion efficiency of battery electrical property.
Brief description of the drawings
, below will be to embodiment in order to illustrate more clearly of the utility model embodiment or technical scheme of the prior art
Or the accompanying drawing used required in description of the prior art is briefly described, it should be apparent that, drawings in the following description are only
It is embodiment of the present utility model, for those of ordinary skill in the art, on the premise of not paying creative work, also
Other accompanying drawings can be obtained according to the accompanying drawing of offer.
A kind of dereliction grid solar cell structure top view that Fig. 1 provides for the utility model embodiment；
Fig. 2 has main grid solar battery structure top view for one kind that the utility model embodiment is provided；
A kind of solar battery structure schematic diagram that Fig. 3 provides for the utility model embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out
Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of the utility model, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment obtained, belongs to the scope of the utility model protection.
Refer to Fig. 1,2 and 3, Fig. 1 bowed for a kind of dereliction grid solar cell structure that the utility model embodiment is provided
View；Fig. 2 has main grid solar battery structure top view for one kind that the utility model embodiment is provided；Fig. 3 is that this practicality is new
A kind of solar battery structure schematic diagram that type embodiment is provided.
The utility model provides a kind of solar cell, including plasma reaction etching RIE silicon chips 16, and described etc.
PN junction diffusion layer 13, secondary gate pattern, antireflective coating 14 and main grid that the front of ion reaction etching RIE silicon chips 16 is set gradually
Main gate line 12 in pattern, the main grid pattern is mutually perpendicular to the secondary grid line 11 in the secondary gate pattern.
Specifically, the utility model provide provide a kind of preparation method of solar battery, including：
Step S1：Prepare plasma reaction etching RIE silicon chips 16.
Wherein, the polysilicon chip from thickness between 210 ± 10mm, such as selects the Buddha's warrior attendant of the 156x156 sizes of type
The polysilicon chip of wire cutting, its thickness is in the range of 190 ± 220nm.To cleaning and texturing before polysilicon chip, former piece is removed in itself
Loss layer and impurity, form the first matte layer, wherein Reducing thickness control is between 0.25~0.35g.Above-mentioned ready-made polycrystalline
Piece inserts progress reactive ion dry etching in RIE equipment, that is, RIE etchings, ultimately forms a kind of bore dia up to 200~500um
The second matte layer of size shape, outward appearance is rendered as black.
Step S2：PN junction diffusion is carried out on the surface of plasma reaction etching RIE silicon chips 16, PN junction diffusion layer is formed
13, in the secondary gate pattern of the surface printing of the PN junction diffusion layer 13.
Wherein, the battery with PN junction diffusion layer 13, its sheet resistivity scope is between 90~130 Ω, and above-mentioned diffusion is well
Polysilicon chip on carry out silk-screen printing, only print and is dried without the thin grid line of main grid, forms a kind of dereliction grid cell.Need
It is noted that the radical of thin grid is not specifically limited, set according to actual needs.
Step S3：The secondary gate pattern evaporation antireflective coating 14 is covered, RIE silicon chips 16 are etched in the plasma reaction
The back side prepares back electrode 15.
Wherein, PECVD plated films are carried out on the above-mentioned cell piece without main grid, a kind of antireflective coating 14, such as Si is formedxNySubtract
Reflectance coating 14 simultaneously covers whole cell piece front surface, to the silver-colored aluminium paste of the above-mentioned multi-wafer back up for having plated film, forms back electrode
15 and the back of the body electric field.
Step S4：Main grid pattern is printed on the antireflective coating 14, the main gate line 12 in the main grid pattern with it is described
Secondary grid line 11 in secondary gate pattern is mutually perpendicular to, and solar cell is formed after being sintered.
Wherein, to the above-mentioned multi-wafer front printing silver paste for having plated film, and carried out on the dereliction grid cell of above-mentioned formation
Secondary printing, current printing uses the mask plate with main grid pattern, forms a kind of main grid and thin grid are orthogonal, sintering
The positive electrode combined together afterwards.
It is to be noted that secondary grid line 11 is that thin grid number of lines is not limited to main grid bar number, carry out as the case may be
Limit, in protection domain.For example, main grid bar number can be between 2~6, thin grizzly bar number is between 90~120.
In this preparation method, plasma reaction etching RIE silicon chips 16 are prepared, the reflectivity of polycrystalline battery is generally higher than
20%, and by RIE technologies, reflectivity can be accomplished to be less than less than 20%, reflectivity is lower, illustrates that the photon absorbed is more,
Improve electric current.PN junction diffusion layer 13 is diffuseed to form on matte after dry etching, is then first printed in the surface of battery PN diffusion layers
The secondary gate pattern of one layer of brush, i.e., without primary gate electrode, spread to have etched and just directly print secondary gate pattern, is to strengthen silicon chip and metal
More preferable Ohmic contact is formed between grid line, because reflection is lower, battery pile face bumps pattern is more obvious, and the contact with slurry is simultaneous
Capacitive is poorer；Then coated with antireflection film 14 again, is passivated the region not covered by grid line, secondly can also aoxidize printing grid line and use
Slurry in the oxide that includes；Finally printing carries main grid pattern, in order to improves the depth-width ratio of main thin grid line, can carry
Height collects the ability of carrier, and the Ohmic contact between enhancing battery electrode and silicon chip, and main grid collect the effect confluxed, from
And improve the conversion efficiency of battery electrical property.
It is described to prepare plasma reaction etching in the step S1 on the basis of above-mentioned preparation method of solar battery
RIE silicon chips 16 include：
Cleaning and texturing is carried out to the silicon chip of selection, the first matte layer is formed；
Reactive ion etching is carried out on first matte layer, the second matte layer is formed, plasma reaction etching is obtained
RIE silicon chips 16.
Wherein, Cl during preparation2The flow of gas is controlled between 400~1200sccm, O2The flow of gas is controlled 900
Between~2000sccm, SF6The input of gas and output flow are respectively between 600~700sccm and 500~650sccm, instead
It is 3~5sec between seasonable, reaction pressure is 20~24pa, and power bracket is between 1000~2000W, and the battery outward appearance made is in
Black, matte layer of the reflectivity control 1%~20%.A kind of Circularhole diameter is formed up to the nanometer of 100~800nm size shapes
The plasma reaction etching RIE silicon chips 16 of structure pile layer.
It is described to prepare plasma reaction etching in the step S1 on the basis of above-mentioned preparation method of solar battery
After RIE silicon chips 16, in addition to：
Plasma reaction etching RIE silicon chips 16 are performed etching cleaning to remove edge phosphorosilicate glass and broken
Bits.
Wherein, multi-wafer performs etching cleaning, and battery surface is stayed in after the phosphorosilicate glass and finishing fluting that remove edge
Secondly, etching discharging end is equipped with O for chip and damaged portion3Generator, by O3The battery of generator has strong passivation effect,
The anti-ageing ability of battery itself can be improved.
In the step S2, before the surface of plasma reaction etching RIE silicon chips 16 carries out PN junction diffusion, also wrap
Include：
HF pickling, ID washings and KOH alkali cleanings are carried out successively to plasma reaction etching RIE silicon chips 16.
Repaired specifically, the good multi-wafer of above-mentioned dry etching is inserted cleaning equipment, its process is：HF pickling, go from
Sub- water ID washings, KOH 10~50S of alkali cleaning durations, ID washing, HF+HNO3Mixed solution is washed, ID is washed, heat after ID washing 60s
~120s, drying.
Further, in above-mentioned solar cell, the plasma reaction etching RIE silicon chips 16 include silicon chip, and
The first matte layer, the second matte layer and the PN junction diffusion layer 13 set gradually in the silicon chip front surface.
Further, in above-mentioned solar cell, the antireflective coating 14 is SixNyAntireflective coating 14, the SixNy
The film thickness range of antireflective coating 14 is 75~85nm, and ranges of indices of refraction is 2.05~2.15.
Further, in above-mentioned solar cell, the bar number scope of the main gate line 12 is 2~6, the secondary grid line
11 bar number scope is 90~120.
It is pointed out that the bar number of the bar number of main gate line 12 and secondary grid line 11 includes but is not limited to above range, according to
Concrete condition is set, in protection domain.
Further, in above-mentioned solar cell, the silicon chip is Buddha's warrior attendant wire cutting polysilicon chip.
Wherein, the silicon chip of the Selection of Battery is cheaper than the polycrystalline that conventional slurry line is cut in Buddha's warrior attendant wire cutting polycrystalline, cost.
Silicon chip can also select other types, in protection domain.
Further, in above-mentioned solar cell, the thickness range of the Buddha's warrior attendant wire cutting polysilicon chip for 168nm~
212nm scopes, areal extent is 150mm*150mm~160mm*160mm.
The embodiment of each in this specification is described by the way of progressive, and what each embodiment was stressed is and other
Between the difference of embodiment, each embodiment identical similar portion mutually referring to.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or new using this practicality
Type.A variety of modifications to these embodiments will be apparent for those skilled in the art, determine herein
The General Principle of justice can in other embodiments be realized in the case where not departing from spirit or scope of the present utility model.Cause
This, the utility model is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The most wide scope consistent with features of novelty.
Claims (6)
1. a kind of solar cell, it is characterised in that etch RIE silicon chips including plasma reaction, and it is anti-in the plasma
PN junction diffusion layer, secondary gate pattern, antireflective coating and main grid pattern that the front of RIE silicon chips is set gradually, the master should be etched
Main gate line in gate pattern is mutually perpendicular to the secondary grid line in the secondary gate pattern.
2. solar cell as claimed in claim 1, it is characterised in that the plasma reaction etching RIE silicon chips are positive table
The first matte layer and the silicon chip of the second matte layer that face is set gradually.
3. solar cell as claimed in claim 2, it is characterised in that the silicon chip is Buddha's warrior attendant wire cutting polysilicon chip.
4. solar cell as claimed in claim 3, it is characterised in that the thickness range of the Buddha's warrior attendant wire cutting polysilicon chip
For 168nm~212nm scopes, areal extent is 150mm*150mm~160mm*160mm.
5. solar cell as claimed in claim 4, it is characterised in that the antireflective coating is SixNyAntireflective coating, it is described
SixNyThe film thickness range of antireflective coating is 75~85nm, and ranges of indices of refraction is 2.05~2.15.
6. solar cell as claimed in claim 5, it is characterised in that the bar number scope of the main gate line is 2~6, institute
The bar number scope for stating secondary grid line is 90~120.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621470544.5U CN206441739U (en) | 2016-12-29 | 2016-12-29 | A kind of solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621470544.5U CN206441739U (en) | 2016-12-29 | 2016-12-29 | A kind of solar cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206441739U true CN206441739U (en) | 2017-08-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621470544.5U Expired - Fee Related CN206441739U (en) | 2016-12-29 | 2016-12-29 | A kind of solar cell |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653949A (en) * | 2016-12-29 | 2017-05-10 | 浙江晶科能源有限公司 | Solar cell and preparation method thereof |
-
2016
- 2016-12-29 CN CN201621470544.5U patent/CN206441739U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106653949A (en) * | 2016-12-29 | 2017-05-10 | 浙江晶科能源有限公司 | Solar cell and preparation method thereof |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170825 Termination date: 20201229 |
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| CF01 | Termination of patent right due to non-payment of annual fee |