CN205959980U - Rete test structure and array substrate - Google Patents
Rete test structure and array substrate Download PDFInfo
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- CN205959980U CN205959980U CN201620956579.3U CN201620956579U CN205959980U CN 205959980 U CN205959980 U CN 205959980U CN 201620956579 U CN201620956579 U CN 201620956579U CN 205959980 U CN205959980 U CN 205959980U
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- 238000012360 testing method Methods 0.000 title claims abstract description 157
- 239000000758 substrate Substances 0.000 title abstract description 9
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- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/02—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
- G01N27/04—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
- G01N27/041—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/14—Measuring resistance by measuring current or voltage obtained from a reference source
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2844—Fault-finding or characterising using test interfaces, e.g. adapters, test boxes, switches, PIN drivers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
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Abstract
The utility model provides a rete test structure and array substrate, this rete of test structure is including the examination conductive film layer that awaits measuring, be located different layers and many test lead -out wires being connected with the examination conductive film layer electricity that awaits measuring respectively and a plurality ofly test the electric test terminals of being connected of lead -out wire with many respectively with the examination conductive film layer that awaits measuring. In being applied to array substrate with this rete test structure, can conveniently accomplish the test of square resistance to can guarantee the precision of test, can avoid test probes's frequent change simultaneously, reduce test probes's consumption, thus reduction in production cost.
Description
Technical field
This utility model is related to a kind of film layer test structure and array base palte.
Background technology
In display technology field, for example, in liquid crystal display or organic elctroluminescent device, thin film transistor (TFT)
It is the basic device in array base palte.In thin film transistor (TFT), the characteristic of each film layer affects the electrology characteristic of thin film transistor (TFT), from
And affect the final display effect of display device.
Square resistance is an important means evaluating film layer characteristic.At present, square resistance is generally real with four probe method
Now measure, tested using equidistant and alinement four probes during test, and probe directly contact film layer, for example,
Fig. 1 is the schematic diagram of test square resistance.Probe is hindered into by four probes, and it requires the distance of four end of probes equal.When
When probe is pressed in above conductive film material, ohm gauge can be used for showing the square resistance of material, and its principle is outer end
Two probes produce current field, and two inner probe test current fields visit, at this two, the potential being formed on point.Square resistance
Bigger, the potential of generation is also bigger, thus can measure the square resistance of film layer.
Utility model content
This utility model provides a kind of film layer test structure and array base palte, and this film layer test structure is applied to array base
In plate, can be readily achieved the test of square resistance, and ensure that the precision of test, simultaneously it can be avoided that test probe
Frequent replacing, reduce test probe consumption, thus reducing production cost.This can solve the test in square resistance at present
In, lead to the spacing between probe to change because probe is long-time using easily occuring bending and deformation, ultimately result in square
The inaccurate problem of measurement of resistance value.
At least one embodiment of the present utility model provides a kind of film layer test structure, including：Conductive film layer to be tested；A plurality of
Test lead-out wire, is located at different layers with described conductive film layer to be tested and is electrically connected with described conductive film layer to be tested respectively；Many
Individual calibrating terminal, multiple described calibrating terminals are electrically connected with described a plurality of test lead-out wire respectively.
For example, in the film layer test structure that this utility model one embodiment provides, one end of described test lead-out wire is even
Connect described conductive film layer to be tested, the other end connects described calibrating terminal.
For example, in the film layer test structure that this utility model one embodiment provides, described test lead-out wire and described survey
Examination terminal is integrally formed.
For example, in the film layer test structure that this utility model one embodiment provides, described test lead-out wire is arranged on institute
State above or below conductive film layer to be tested.
For example, the film layer test structure that this utility model one embodiment provides, also includes being arranged on described conduction to be tested
The insulating barrier of film layer side, described insulating barrier defines multiple first vias, and described a plurality of test lead-out wire passes through corresponding institute
State multiple first vias to electrically connect with described conductive film layer to be tested.
For example, in the film layer test structure that this utility model one embodiment provides, described first via is arranged on described
The zone line of conductive film layer to be tested.
For example, in the film layer test structure that this utility model one embodiment provides, described first mistake of arbitrary neighborhood two
The distance between hole is equal.
For example, in the film layer test structure that this utility model one embodiment provides, described first via is arranged in a linear.
For example, in the film layer test structure that this utility model one embodiment provides, the number of described first via is 4
Individual, and 4 described first via arrangement become equilateral tetragon.
For example, this utility model one embodiment provide film layer test structure in, the plurality of calibrating terminal with described
Conductive film layer to be tested is located at same layer but insulated from each other, or positioned at same layer and electric each other with described a plurality of test lead-out wire
Connect.
For example, this utility model one embodiment provide film layer test structure in, the plurality of calibrating terminal with described
In the case that conductive film layer to be tested is located at same layer, described insulating barrier also includes multiple second vias, the plurality of test lead
Sub and described a plurality of test lead-out wire is electrically connected by described second via.
At least one embodiment of the present utility model also provides a kind of array base palte, ties including the film layer test described in above-mentioned
Structure, described conductive film layer to be tested is located at grid film layer, source-drain electrode film layer or pixel electrode film layer.
For example, in the array base palte that this utility model one embodiment provides, it is described grid in described conductive film layer to be tested
In the case of the film layer of pole, described a plurality of test lead-out wire is located at described source-drain electrode film layer, and the plurality of calibrating terminal is located at institute
State grid film layer or described source-drain electrode film layer.
For example, in the array base palte that this utility model one embodiment provides, it is described source in described conductive film layer to be tested
In the case of drain electrode film layer, described a plurality of test lead-out wire is located at described grid film layer, and the plurality of calibrating terminal is located at institute
State grid film layer or described source-drain electrode film layer.
For example, in the array base palte that this utility model one embodiment provides, it is described picture in described conductive film layer to be tested
In the case of plain electrode film layer, described a plurality of test lead-out wire is located at described source-drain electrode film layer, the plurality of calibrating terminal position
In described source-drain electrode film layer or pixel electrode film layer.
Brief description
In order to be illustrated more clearly that the technical scheme of this utility model embodiment, simple by making to the accompanying drawing of embodiment below
Ground introduce it should be apparent that, drawings in the following description merely relate to some embodiments of the present utility model, rather than to this practicality
New restriction.
Fig. 1 is a kind of schematic diagram of test square resistance；
Fig. 2 is the schematic diagram after the probe deformations in Fig. 1；
A kind of schematic diagram of film layer test structure that Fig. 3 provides for this utility model one embodiment；
Fig. 4 a is for the film layer test structure in Fig. 3 along the cross section structure schematic diagram after A-B cutting；
Fig. 4 b is for the film layer test structure in Fig. 3 along the cross section structure schematic diagram after C-D cutting；
The schematic diagram of the film layer test structure that Fig. 5 provides for another embodiment of this utility model；
The schematic diagram of the film layer test structure that Fig. 6 provides for another embodiment of this utility model.
Reference：
100- film layer test structure；101- conductive film layer to be tested；102- tests lead-out wire；103- calibrating terminal；105-
Insulating barrier；106- first via；107- second via.
Specific embodiment
Purpose, technical scheme and advantage for making this utility model embodiment are clearer, new below in conjunction with this practicality
The accompanying drawing of type embodiment, is clearly and completely described to the technical scheme of this utility model embodiment.Obviously, described
Embodiment is a part of embodiment of the present utility model, rather than whole embodiments.Based on described of the present utility model
Embodiment, the every other embodiment that those of ordinary skill in the art are obtained on the premise of without creative work, all belong to
Scope in this utility model protection.
Unless otherwise defined, the technical term that the disclosure uses or scientific terminology should be this utility model art
Inside there is the ordinary meaning that the personage of general technical ability is understood." first ", " second " and similar word used in the disclosure
Language is not offered as any order, quantity or importance, and is used only to distinguish different ingredients." inclusion " or " bag
Contain " etc. similar word mean to occur element before this word or object cover the element occurring in this word presented hereinafter or
Object and its equivalent, and it is not excluded for other elements or object.The word that " connection " or " being connected " etc. are similar to is not limited to
Physics or machinery connection, but can include electrical connection, no matter be direct or indirectly." on ", D score,
"left", "right" etc. is only used for representing relative position relation, and after the absolute position being described object changes, then this relative position is closed
System is likely to correspondingly change.
Square resistance generally realizes measurement with four probe method, is surveyed using equidistant and alinement four probes
Examination, for conductive film layer, square resistance is only related to conductive film layer thickness to be tested.Square resistance is defined as：R□=
ρ/t, wherein, ρ be metallic resistance rate, t by survey thin film thickness.
The test request of square resistance is：The distance on each probe to conductive film layer border to be tested is significantly larger than any phase
Spacing between adjacent two probes, for example, between the distance of each probe to conductive film layer border to be tested is at least above adjacent probe
Away from 10 times；Probe needs to be spaced at equal intervals.
Using equidistantly and the placement that is in line four probe test square resistances when, square resistance can use below equation meter
Calculate：
Wherein, as shown in figure 1, probe 1, probe 2, probe 3 and probe 4 are successively set in conductive test film layer, Sprobe
For probe spacing, U23For the voltage difference between probe 2 and probe 3, I14For the electric current between probe 1 and probe 4.
In conventional array base palte technique, need formed such as metallic diaphragm or transparent conductive film layer, with formed grid line,
The circuit structures such as data wire, pixel electrode.In order to detect the quality of forming film of these conductive film layers, generally can be measured these conductive
The square resistance of film layer.Square resistance is the test carrying out after conductive film layer to be tested is formed and before etching operation,
Probe is positioned over region to be etched and is tested to avoid bringing damage to film layer.The disclosure inventors noted that working as probe
Long-time use after, probe such as can occur to bend, offset at the abrasion, thus leading to the spacing of probe to change, and then leads
Cause measurement error so that calculating using above-mentioned formula (1) inaccurate during resistance, measuring accuracy declines, thus may need frequently
Probe is changed on ground.For example, Fig. 2 is the schematic diagram after probe deformations.As shown in Fig. 2 probe there occurs flexural deformation, lead to probe
Between spacing there occurs change, when using square resistance formula (1) Computational block resistance value, error can occur.And, send out
A person of good sense also finds, can carry out unifying to test again, so grasp after each film layer completes after forming square resistance test pattern
Work gets up more convenient.
For solve above-mentioned in the test of square resistance, lead to using easily occuring bending and deformation visit because probe is long-time
Spacing between pin changes, and ultimately results in the inaccurate problem of measurement of square resistance, this utility model one embodiment
Provide a kind of film layer test structure, this film layer test structure includes：Conductive film layer to be tested；It is located at conductive film layer to be tested
Different layers and a plurality of test lead-out wire electrically connecting with conductive film layer to be tested respectively；Multiple calibrating terminals, the plurality of test lead
Son is electrically connected with a plurality of test lead-out wire respectively.
Embodiment one
The present embodiment provides a kind of film layer test structure, and Fig. 3 surveys for a kind of film layer that this utility model one embodiment provides
The schematic diagram of examination structure, as shown in figure 3, this film layer test structure 100 includes conductive film layer 101 to be tested, a plurality of test is drawn
Line 102 and multiple calibrating terminal 103, and a plurality of test lead-out wire 102 and conductive film layer 101 to be tested be located at different layers and point
Do not electrically connect with conductive film layer 101 to be tested, multiple calibrating terminals 103 are electrically connected with a plurality of test lead-out wire 102 respectively.
As shown in figure 3, be drawn out to by the test point on a plurality of test lead-out wire 102 conductive film layer 101 to be tested treating
Outside testing conductive film layer 101, and instead of the test point on conductive film layer 101 to be tested by multiple calibrating terminals 103, this
Sample, as long as probe moves in corresponding calibrating terminal 103, substantially surveyed is to electrically connect with each calibrating terminal 103
Resistance at each test point.
When using film layer test structure in the present embodiment, when probe due to long-time using the probe that occurs bending and deformation
Between spacing when changing, as long as probe moves in corresponding calibrating terminal 103, measured square resistance is still
Accurate, that is, using the film layer test structure in the present embodiment can be readily achieved square resistance test it is ensured that
The precision of test, it is to avoid the frequent replacing of probe, thus reduce production cost.
For example, as shown in figure 3, a plurality of test lead-out wire 102 in this film layer test structure 100 can be arranged on to be tested
Above or below conductive film layer 101.
For example, this film layer test structure 100 can be formed at the white space of substrate.Can generally form on substrate for
The pixel region of at least one display floater, white space be distributed in pixel region periphery or between.This white space is to base
Plate is removed after being cut.
For example, this conductive film layer 101 to be tested can be gate electrode film layer, source-drain electrode film layer and transparent conductive oxide system
The pixel electrode film layer of work, public electrode film layer etc..
For example, the manufacturing process of this film layer to be tested includes：By magnetron sputtering, vapour deposition (such as chemical vapor deposition
Long-pending) etc. mode conductive film layer deposit on substrate, then coating photoresist on this conductive film layer, then be exposed, develop, carve
The operation such as erosion and stripping photoresist forms conductive film layer 101 to be tested on substrate, and is correspondingly formed in pixel region
Circuit structure (such as grid line, grid, data wire, source-drain electrode, pixel electrode, public electrode etc.).
So that the film layer of formation is for gate metal film layer as a example it is illustrated below, test lead-out wire 102 can be in the source that formed
Formed when drain electrode layer or pixel electrode film layer, so can be increased without processing step.For example, form test lead-out wire
102 process includes：Source and drain metallic diaphragm is deposited by modes such as magnetron sputterings, then in film layer, coats photoresist, then enter
The operations such as row exposure, development, etching and stripping photoresist form test lead-out wire 102 on substrate.Similarly, if to be tested
When film layer is source and drain metallic diaphragm, test lead-out wire can be formed with layer with gate metal film layer or pixel electrode film layer.
For example, as shown in figure 3, multiple calibrating terminal 103 is located at same layer but insulated from each other with conductive film layer 101 to be tested
Or multiple calibrating terminals 103 are located at same layer and are electrically connected to each other with a plurality of test lead-out wire 102.List so can be saved
Solely do the operation of calibrating terminal.Same layer is located at by calibrating terminal and conductive film layer to be tested but is said as a example insulated from each other
Bright, the forming process of calibrating terminal is formed with conductive film layer to be tested simultaneously.
For example, as shown in figure 3, the width of calibrating terminal 103 is more than the corresponding width testing lead-out wire 102, calibrating terminal
103 size should measure in order to probe and be advisable, and the shape of calibrating terminal 103 is also unrestricted, still in order to probe
Measure and be advisable.As shown in figure 3, calibrating terminal 103 is square, in other embodiment of the present utility model, test lead
The shape of son 103 can also be circle, rectangle, polygon etc..
For example, on the premise of ensureing calibrating terminal and conductive film layer insulation to be tested, calibrating terminal can be arranged on
Calibrating terminal, in order to ensure the convenience tested, is arranged on same straight by the optional position around conductive film layer to be tested as far as possible
On line.In the case that the width of test lead-out wire is fixing, the length of test lead-out wire is arranged the shortest, drawn with reducing test
The resistance of outlet itself gives the impact that the degree of accuracy of test causes.And it is to be tested to ensure that test point can be drawn out to by test lead-out wire
Outside film layer.
For example, the cross section structure schematic diagram after Fig. 4 a cuts along A-B for the film layer test structure in Fig. 3, as shown in fig. 4 a,
This film layer test structure also includes being arranged on the insulating barrier 105 of conductive film layer 101 side to be tested, and insulating barrier 105 defines
Multiple first vias 106, a plurality of test lead-out wire passes through multiple first vias 106 and conductive film layer 101 electricity to be tested accordingly
Connect.
For example, as shown in fig. 4 a, the first via 106 is arranged on the zone line of conductive film layer 101 to be tested.
For example, as shown in fig. 4 a, the distance between two first vias 106 of arbitrary neighborhood are equal.
For example, as shown in fig. 4 a, the number of the first via is 4, and 4 the first vias are arranged in a linear.
For example, as shown in figure 5,4 the first vias may be arranged in square or rhombus, as long as meeting adjacent two
Spacing between individual first via is equal.But when the first via arrangement becomes square or rhombus, calculated using formula
Need during resistance to be multiplied by corresponding coefficient.
For example, the cross section structure schematic diagram after Fig. 4 b cuts along C-D for the film layer test structure in Fig. 3, such as Fig. 3 and Fig. 4 b
Shown, in the case that multiple calibrating terminals are located at same layer with conductive film layer to be tested, insulating barrier 105 also includes multiple second
Via 107, multiple calibrating terminals 103 are electrically connected by the second via 107 with a plurality of test lead-out wire 102.
After the film layer test structure in the present embodiment completes, contact four terminals using four probe groups, two
Input respectively and output current on two probes of side, measure the voltage difference on middle two terminals, according to square resistance simultaneously
Formula can be calculated square resistance.When the film layer test structure in the present embodiment is carried out with square resistance test, visit
The contact position of pin, on calibrating terminal, even if long-time use of probe deforms, because the area of calibrating terminal is larger, is surveyed
Error in the test value that test result also square resistance will not because of the change of probe spacing.
For example, in the present embodiment, the spread geometry of multiple vias is also not limited to be arranged in a linear and is in equilateral four
Side shape arrangement, can also be other arrangement modes, as long as can match with the computing formula of corresponding square resistance,
This repeats no more.
Embodiment two
A kind of the present embodiment film layer test structure of offer, the schematic diagram of the film layer test structure that Fig. 6 provides for the present embodiment,
In this film layer test structure, multiple test lead-out wires 102 ends extend each self-corresponding calibrating terminal 103 and the two one
Body shapes.
For example, multiple calibrating terminals 103 are extended by the end of multiple test lead-out wires 102 respectively and constitute, and calibrating terminal
103 width is more than the corresponding width testing lead-out wire 102, now multiple test lead-out wires 102 and multiple calibrating terminals 103
Positioned at same layer.As shown in fig. 6, calibrating terminal 103 is extended by the end of multiple test lead-out wires 102 respectively constituting.For example, survey
The flat shape of examination terminal 103 can be square, and its length of side is more than the width of test lead-out wire 102.
In the present embodiment, constitute except multiple calibrating terminals 103 are extended by the end of multiple test lead-out wires 102 respectively
Outward, other architectural features all refer to the associated description in embodiment one, will not be described here.
For example, in the present embodiment, the spread geometry of multiple vias is also not limited to be arranged in a linear and is in equilateral four
Side shape arrangement, can also be other arrangement modes, as long as can match with the computing formula of corresponding square resistance,
This repeats no more.
Embodiment three
The present embodiment provides a kind of array base palte, including the arbitrary film layer test knot in embodiment one or embodiment two
Structure.
For example, this conductive film layer to be tested is located at grid film layer, source-drain electrode film layer or pixel electrode film layer.
For example, in the case that conductive film layer to be tested is grid film layer, a plurality of test lead-out wire is located at source-drain electrode film
Layer, multiple calibrating terminals are located at grid film layer or source-drain electrode film layer.If using the film layer test structure in embodiment two,
Then multiple calibrating terminals and a plurality of test lead-out wire are located at same film layer.
For example, in the case that conductive film layer to be tested is source-drain electrode film layer, a plurality of test lead-out wire is located at gate electrode film
Layer, multiple calibrating terminals are located at grid film layer or source-drain electrode film layer.If using the film layer test structure in embodiment two,
Then multiple calibrating terminals and a plurality of test lead-out wire are located at same film layer.
For example, in the case that conductive film layer to be tested is pixel electrode film layer, a plurality of test lead-out wire is located at source and drain electricity
Pole film layer, multiple calibrating terminals are located at source-drain electrode film layer or pixel electrode film layer.If surveyed using the film layer in embodiment two
Examination structure, then multiple calibrating terminals and a plurality of test lead-out wire are located at same film layer.
A kind of film layer test structure that embodiment of the present utility model provides and array base palte are at least had and are had with the next item down
Beneficial effect：
(1) this film layer test structure is applied in array base palte, the test of square resistance can be readily achieved, and
Ensure that the precision of test, simultaneously it can be avoided that the frequent replacing of test probe, reducing the consumption of test probe, thus reducing
Production cost；
(2) can carry out again after forming square resistance test pattern unifying to test, so grasp after each film layer completes
Work gets up more convenient.
Have following some need explanation：
(1) this utility model embodiment accompanying drawing relates only to the structure being related to this utility model embodiment, other knots
Structure refers to be commonly designed.
(2) for clarity, in the accompanying drawing for describing embodiment of the present utility model, the thickness quilt in layer or region
Zoom in or out, that is, these accompanying drawings are not drawn according to actual ratio.It is appreciated that ought such as layer, film, region or substrate it
The element of class be referred to as positioned at another element " on " or during D score, this element can " direct " be located at another element " on " or
D score, or there may be intermediary element.
(3) in the case of not conflicting, the feature in embodiment of the present utility model and embodiment can be mutually combined with
Obtain new embodiment.
The above, specific embodiment only of the present utility model, but protection domain of the present utility model does not limit to
In this, protection domain of the present utility model should be defined by described scope of the claims.
Claims (15)
1. a kind of film layer test structure, including：
Conductive film layer to be tested；
A plurality of test lead-out wire, positioned at different layers and electric with described conductive film layer to be tested respectively with described conductive film layer to be tested
Connect；
Multiple calibrating terminals, multiple described calibrating terminals are electrically connected with described a plurality of test lead-out wire respectively.
2. film layer test structure according to claim 1 is it is characterised in that one end connection of described test lead-out wire is described
Conductive film layer to be tested, the other end connects described calibrating terminal.
3. film layer test structure according to claim 2 is it is characterised in that described test lead-out wire and described calibrating terminal
Integrally formed.
4. the film layer test structure according to Claims 2 or 3 it is characterised in that described test lead-out wire be arranged on described
Above or below conductive film layer to be tested.
5. film layer test structure according to claim 4 is it is characterised in that also include being arranged on described conducting film to be tested
The insulating barrier of layer side, described insulating barrier defines multiple first vias, and described a plurality of test lead-out wire passes through described accordingly
Multiple first vias are electrically connected with described conductive film layer to be tested.
6. film layer test structure according to claim 5 it is characterised in that described first via be arranged on described to be tested
The zone line of conductive film layer.
7. film layer test structure according to claim 6 is it is characterised in that between described first via of arbitrary neighborhood two
Distance equal.
8. film layer test structure according to claim 7 is it is characterised in that described first via is arranged in a linear.
9. film layer test structure according to claim 7 is it is characterised in that the number of described first via is 4, and 4
Individual described first via arrangement becomes equilateral tetragon.
10. the film layer test structure according to any one of claim 5-9 is it is characterised in that the plurality of calibrating terminal
It is located at same layer but insulated from each other with described conductive film layer to be tested, or be located at same layer simultaneously with described a plurality of test lead-out wire
It is electrically connected to each other.
11. film layer test structures according to claim 10 are it is characterised in that the plurality of calibrating terminal is to be measured with described
In the case that examination conductive film layer is located at same layer, described insulating barrier also includes multiple second vias, the plurality of calibrating terminal with
Described a plurality of test lead-out wire passes through described second via electrical connection.
A kind of 12. array base paltes are it is characterised in that include the film layer test structure any one of claim 1-11, institute
State conductive film layer to be tested and be located at grid film layer, source-drain electrode film layer or pixel electrode film layer.
13. array base paltes according to claim 12 are it is characterised in that be described grid in described conductive film layer to be tested
In the case of film layer, described a plurality of test lead-out wire is located at described source-drain electrode film layer, and the plurality of calibrating terminal is located at described
Grid film layer or described source-drain electrode film layer.
14. array base paltes according to claim 12 are it is characterised in that be described source and drain in described conductive film layer to be tested
In the case of electrode film layer, described a plurality of test lead-out wire is located at described grid film layer, and the plurality of calibrating terminal is located at described
Grid film layer or described source-drain electrode film layer.
15. array base paltes according to claim 12 are it is characterised in that be described pixel in described conductive film layer to be tested
In the case of electrode film layer, described a plurality of test lead-out wire is located at described source-drain electrode film layer, and the plurality of calibrating terminal is located at
Described source-drain electrode film layer or pixel electrode film layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620956579.3U CN205959980U (en) | 2016-08-26 | 2016-08-26 | Rete test structure and array substrate |
| PCT/CN2017/083195 WO2018036200A1 (en) | 2016-08-26 | 2017-05-05 | Film test structure and array substrate |
| US15/573,067 US10332811B2 (en) | 2016-08-26 | 2017-05-05 | Film test structure and array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620956579.3U CN205959980U (en) | 2016-08-26 | 2016-08-26 | Rete test structure and array substrate |
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| Publication Number | Publication Date |
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| CN205959980U true CN205959980U (en) | 2017-02-15 |
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ID=57980211
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| CN201620956579.3U Active CN205959980U (en) | 2016-08-26 | 2016-08-26 | Rete test structure and array substrate |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US10332811B2 (en) |
| CN (1) | CN205959980U (en) |
| WO (1) | WO2018036200A1 (en) |
Cited By (6)
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|---|---|---|---|---|
| WO2018036200A1 (en) * | 2016-08-26 | 2018-03-01 | 京东方科技集团股份有限公司 | Film test structure and array substrate |
| CN108181741A (en) * | 2018-01-05 | 2018-06-19 | 京东方科技集团股份有限公司 | A kind of test device and its method of display panel film layer stripping position |
| CN109378280A (en) * | 2018-11-21 | 2019-02-22 | 中国科学院上海技术物理研究所 | A kind of test structure for high density face battle array performance verification |
| CN111933066A (en) * | 2020-08-28 | 2020-11-13 | 京东方科技集团股份有限公司 | OLED display substrate, display module and display panel |
| CN112015017A (en) * | 2020-09-15 | 2020-12-01 | 武汉华星光电技术有限公司 | Test circuit and display panel test method |
| CN112599578A (en) * | 2020-12-11 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018036200A1 (en) * | 2016-08-26 | 2018-03-01 | 京东方科技集团股份有限公司 | Film test structure and array substrate |
| US10332811B2 (en) | 2016-08-26 | 2019-06-25 | Boe Technology Group Co., Ltd. | Film test structure and array substrate |
| CN108181741A (en) * | 2018-01-05 | 2018-06-19 | 京东方科技集团股份有限公司 | A kind of test device and its method of display panel film layer stripping position |
| CN109378280A (en) * | 2018-11-21 | 2019-02-22 | 中国科学院上海技术物理研究所 | A kind of test structure for high density face battle array performance verification |
| CN109378280B (en) * | 2018-11-21 | 2023-09-12 | 中国科学院上海技术物理研究所 | Test structure for high-density area array performance verification |
| CN111933066A (en) * | 2020-08-28 | 2020-11-13 | 京东方科技集团股份有限公司 | OLED display substrate, display module and display panel |
| CN112015017A (en) * | 2020-09-15 | 2020-12-01 | 武汉华星光电技术有限公司 | Test circuit and display panel test method |
| CN112599578A (en) * | 2020-12-11 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
| CN112599578B (en) * | 2020-12-11 | 2023-10-17 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2018036200A1 (en) | 2018-03-01 |
| US10332811B2 (en) | 2019-06-25 |
| US20180358273A1 (en) | 2018-12-13 |
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