CN202166811U - Array substrate, liquid crystal panel and display device - Google Patents
Array substrate, liquid crystal panel and display device Download PDFInfo
- Publication number
- CN202166811U CN202166811U CN2011202931461U CN201120293146U CN202166811U CN 202166811 U CN202166811 U CN 202166811U CN 2011202931461 U CN2011202931461 U CN 2011202931461U CN 201120293146 U CN201120293146 U CN 201120293146U CN 202166811 U CN202166811 U CN 202166811U
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- array base
- base palte
- array substrate
- liquid crystal
- peripheral circuit
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Abstract
The utility model provides an array substrate, a liquid crystal panel and a display device. The array substrate comprises gate lines. Test connectors are arranged on the uppermost layer of a peripheral circuit area of the array substrate and electrically connected with the gate lines through conductive through holes. The array substrate comprises the test connectors. When a resistor value of a gate pole in the array substrate needs measuring, a probe of a resistor measuring instrument can be directly connected with the test connectors for measuring the resistor value of the gate pole, and a pad no longer needs to be prepared on the peripheral circuit area of the array substrate so as to save space for the array substrate, make full use of area of the array substrate, improve integrity and resolution factor of the array substrate, meanwhile improve stability and reliability of production technology, improve production efficiency and save cost.
Description
Technical field
The utility model relates to the technical field of array base palte, particularly, relates to a kind of array base palte, liquid crystal panel and display device.
Background technology
Along with the continuous development of lcd technology, more and more demand high resolving power and undersized liquid crystal panel on the market, liquid crystal panel generally includes array base palte, color membrane substrates and the liquid crystal layer between the two.In the production of array base palte, need carry out the test of electrical parameters such as resistance, voltage at array substrate before the array base palte shipment, to guarantee the yield of array base palte.
Fig. 1 is the vertical view of array base palte in the prior art.Of Fig. 1; Array base palte generally includes array region 10 and peripheral circuit area 20; Wherein, The substrate of the array region of array base palte comprises grid, gate insulation, active layer, source-drain electrode, protective seam and pixel electrode successively, and in the peripheral circuit area of array base palte, comprises pad (Pad).
In the prior art; Utilize auto testing instrument (Automatic Test Equipment; ATE) the array substrate carries out the electrical parameter test; Probe on the auto testing instrument is connected with pad (Pad) in the peripheral circuit area, with electrical parameters such as the resistance of each grid in the hot-wire array substrate, curtages.Because the volume of array base palte is more and more littler; Dwindle if bonding pad area is also corresponding; When causing on the hot-wire array substrate electrical parameter such as resistance, the probe on the auto testing instrument is contact pad fully, and the error ratio that causes measuring the grid electrical parameter is bigger; If bonding pad area does not dwindle along with the area of array base palte is corresponding, then can influence the raising of the integrated level and the resolution of array base palte.
The utility model content
For addressing the above problem, the utility model provides a kind of array base palte, liquid crystal panel and display device, is used for solving prior art, influences the integrated level of raising array base palte and the problem of resolution owing to array base palte is provided with pad.
For this reason, the utility model provides a kind of array base palte, comprises grid line, wherein, is provided with test splice in the superiors of the peripheral circuit area of array base palte, and said test splice is electrically connected with said grid line through conductive through hole.
Further, said array base palte also comprises the pixel electrode that is formed on array region, and said test splice is identical with the material of said pixel electrode.
Wherein, the superiors of the peripheral circuit area of array base palte are protective seam; Be followed successively by gate insulation layer and public electrode wire between said grid line in the peripheral circuit area of array base palte and the protective seam.Wherein, the subregion of the protective seam of the peripheral circuit area of array base palte is provided with test splice, and promptly this moment, test splice was positioned on the protective seam; That is to say; At peripheral circuit area, when test splice was not set, protective seam was the superiors; After test splice was set, test splice was positioned at the superiors.
Wherein, in said gate insulation layer, public electrode wire and protective seam, be cavernous structure with the corresponding position of said conductive through hole.
Wherein, the size of the cavernous structure on the said public electrode wire is greater than the size of said conductive through hole.
Wherein, said cavernous structure is circle, ellipse, square, rectangle or polygon.
Wherein, the material of said test splice comprises tin indium oxide or indium zinc oxide.
The utility model also provides a kind of liquid crystal panel, comprises array base palte, color membrane substrates and the liquid crystal between said array base palte and color membrane substrates, and wherein, said array base palte adopts any one above-mentioned structure.
The utility model also provides a kind of display device, wherein, comprises the liquid crystal panel of said structure.
The utlity model has following beneficial effect:
Comprise test splice on the array base palte that the utility model provides; The resistance value of grid in needing the hot-wire array substrate; Can the probe on the resistance meter be connected with test splice and measure, need on the peripheral circuit area of array base palte, not prepare pad again, thereby can save the space of array base palte to obtain the resistance value of grid; Make full use of the area of array base palte; Improve the integrated level and the resolution of array base palte, can improve the stability and the reliability of explained hereafter simultaneously, enhance productivity and save cost.
Liquid crystal panel that the utility model provides and display device also have above-mentioned advantage.
Description of drawings
Fig. 1 is the vertical view of array base palte in the prior art;
Fig. 2 is the structural representation of the utility model array base palte embodiment peripheral circuit area;
Fig. 3 is the structural representation of public electrode wire on the array base palte among Fig. 2.
Embodiment
For making those skilled in the art understand the technical scheme of the utility model better, the array base palte, liquid crystal panel and the display device that the utility model are provided below in conjunction with accompanying drawing are described in detail.
The utility model provides a kind of array base palte, and the superiors of the peripheral circuit area of array base palte (being generally protective seam PVX) are provided with test splice, and this test splice is electrically connected with grid line through conductive via; That is to say that at peripheral circuit area, when test splice was not set, protective seam was the superiors, test splice is set after, test splice is physically located in the superiors.Other structures of the utility model array substrate (like the setting of each layer between protective seam and the grid line) are not done qualification, as long as have the array base palte of aforementioned structure.
For convenience, it is following to enumerate a specific embodiment.Among the array base palte embodiment that the utility model provides, comprise substrate at the array region of array base palte, and the grid, gate insulation layer, active layer, source-drain electrode, protective seam and the pixel electrode that on substrate, form successively, repeat no more at this.
Fig. 2 is the structural representation of the utility model array base palte embodiment peripheral circuit area, and Fig. 3 is the structural representation of public electrode wire on the array base palte among Fig. 2.As shown in Figure 2; In the present embodiment array base palte; The peripheral circuit area of array base palte comprises substrate 101, comprises grid 102, gate insulation layer 103, public electrode wire 104 and protective seam 105 on the substrate 101 successively, at the peripheral circuit area of array base palte; Preparation has test splice 106 on the protective seam 105, and test splice 106 is connected with grid 102 through the conductive material 108 in the conductive through hole 107 of gate insulation layer 103 and protective seam 105.Conductive through hole 107 only is formed in the via hole on gate insulation layer 103 and the protective seam 105, and itself is also non-conductive, is deposited on the conductive material 108 continuity test joints 106 and grid lines 102 in the conductive through hole 107.As shown in Figure 3; Be cavernous structure with conductive through hole 107 corresponding positions on the public electrode wire 104 in the peripheral circuit area; Conductive through hole 107 connects grid 102 and test splice 106 through the cavernous structure on the public electrode wire 104 109; Wherein, the size of conductive through hole 107 is less than the size of the cavernous structure on the public electrode wire 104 109, is electrically connected with between the conductive materials 108 of avoiding deposition in the conductive through hole 107 and the public electrode wire 104.
In needing the hot-wire array substrate during electrical parameters such as resistance value of grid 102; Can the probe on the resistance meter directly be connected with test splice 106; Test splice 106 only is electrically connected with grid 102 through the conductive material 108 in the conductive through hole 107, accurately to measure the electrical parameters such as resistance value of grid 102; And need on the peripheral circuit area of array base palte, not prepare the required pad of electrical parameter that is used to measure grid 102; Thereby can save the space of array base palte; Make full use of the area of array base palte, can improve the integrated level and the resolution of array base palte simultaneously.
In practical application; Test splice 106 on the array base palte peripheral circuit area can be by obtaining through the composition prepared with one deck transparent conductive material with the pixel electrode on the array base palte array region; Transparent conductive material can be tin indium oxide (ITO) or indium zinc oxide (IZO) etc.; Conductive through hole deposits the conductive material 108 that connects grid and test splice for 107 li; Conductive material can adopt the material preparation of test splice to obtain, and the test splice material can be tin indium oxide or indium zinc oxide; In the practical application, when the material of pixel deposition electrode, this material also will deposit to conductive through hole 107, and promptly test splice 106 is identical with the material of pixel electrode, and conductive material 108 be same material with test splice 106, and go on foot in the deposition process one and to form.
The present invention also provides a kind of liquid crystal panel, and liquid crystal panel comprises array base palte, color membrane substrates and liquid crystal layer, and liquid crystal layer is between array base palte and color membrane substrates; Wherein, Array base palte adopts structure shown in Figure 2, when the array substrate carries out the electrical parameter test, can the probe on the resistance meter directly be connected with test splice 106 and measure to obtain the resistance value of grid 102; Need be on the peripheral circuit area of array base palte again preparation be used to measure the pad of the electrical parameter of grid 102; Thereby can save the space of array base palte, make full use of the area of array base palte, can improve the integrated level and the resolution of array base palte simultaneously.
The present invention also provides a kind of display device, comprises above-mentioned liquid crystal panel.Wherein, Array base palte in the liquid crystal panel adopts structure shown in Figure 2; Owing to need on the peripheral circuit area of array base palte, not prepare the required pad of electrical parameter that is used to measure grid 102; Thereby can save the space of array base palte, make full use of the area of array base palte, can improve the integrated level and the resolution of array base palte in the display device simultaneously.
It is understandable that above embodiment only is the illustrative embodiments that adopts for the principle that the utility model is described, yet the utility model is not limited thereto.For the one of ordinary skilled in the art, under the situation of spirit that does not break away from the utility model and essence, can make various modification and improvement, these modification and improvement also are regarded as the protection domain of the utility model.
Claims (9)
1. an array base palte comprises grid line, it is characterized in that, is provided with test splice in the superiors of the peripheral circuit area of array base palte, and said test splice is electrically connected with said grid line through conductive through hole.
2. array base palte according to claim 1 is characterized in that, also comprises the pixel electrode that is formed on array region, and said test splice is identical with the material of said pixel electrode.
3. array base palte according to claim 1 is characterized in that, the superiors of the peripheral circuit area of array base palte are protective seam;
Be followed successively by gate insulation layer and public electrode wire between said grid line in the peripheral circuit area of array base palte and the protective seam.
4. array base palte according to claim 3 is characterized in that, in said gate insulation layer, public electrode wire and protective seam, is cavernous structure with the corresponding position of said conductive through hole.
5. array base palte according to claim 4 is characterized in that the size of the cavernous structure on the said public electrode wire is greater than the size of said conductive through hole.
6. according to claim 4 or 5 described array base paltes, it is characterized in that said cavernous structure is circle, ellipse, square, rectangle or polygon.
7. array base palte according to claim 1 and 2 is characterized in that the material of said test splice comprises tin indium oxide or indium zinc oxide.
8. a liquid crystal panel comprises array base palte, color membrane substrates and the liquid crystal between said array base palte and color membrane substrates, it is characterized in that, said array base palte adopts the arbitrary described structure of claim 1～7.
9. a display device is characterized in that, comprises the described liquid crystal panel of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202931461U CN202166811U (en) | 2011-08-12 | 2011-08-12 | Array substrate, liquid crystal panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202931461U CN202166811U (en) | 2011-08-12 | 2011-08-12 | Array substrate, liquid crystal panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202166811U true CN202166811U (en) | 2012-03-14 |
Family
ID=45802628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011202931461U Expired - Lifetime CN202166811U (en) | 2011-08-12 | 2011-08-12 | Array substrate, liquid crystal panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202166811U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106353937A (en) * | 2016-11-28 | 2017-01-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| WO2018036200A1 (en) * | 2016-08-26 | 2018-03-01 | 京东方科技集团股份有限公司 | Film test structure and array substrate |
| CN108732840A (en) * | 2018-05-31 | 2018-11-02 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
-
2011
- 2011-08-12 CN CN2011202931461U patent/CN202166811U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018036200A1 (en) * | 2016-08-26 | 2018-03-01 | 京东方科技集团股份有限公司 | Film test structure and array substrate |
| US10332811B2 (en) | 2016-08-26 | 2019-06-25 | Boe Technology Group Co., Ltd. | Film test structure and array substrate |
| CN106353937A (en) * | 2016-11-28 | 2017-01-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN108732840A (en) * | 2018-05-31 | 2018-11-02 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120314 |