CN103928530B - Oxide thin film transistor array substrate and manufacturing method thereof - Google Patents
Oxide thin film transistor array substrate and manufacturing method thereof Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 68
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 238000002161 passivation Methods 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 252
- 239000002184 metal Substances 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 238000009413 insulation Methods 0.000 claims description 29
- 230000027455 binding Effects 0.000 claims description 25
- 238000009739 binding Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 24
- 239000001257 hydrogen Substances 0.000 claims description 21
- 229910052739 hydrogen Inorganic materials 0.000 claims description 21
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 9
- 230000005611 electricity Effects 0.000 claims description 5
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical group O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 claims 1
- GRPQBOKWXNIQMF-UHFFFAOYSA-N indium(3+) oxygen(2-) tin(4+) Chemical group [Sn+4].[O-2].[In+3] GRPQBOKWXNIQMF-UHFFFAOYSA-N 0.000 claims 1
- 239000010408 film Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
The embodiment of the invention discloses an oxide thin film transistor array substrate and a manufacturing method thereof, wherein an active layer in a TFT device and a pixel electrode in a pixel region are arranged on the same layer in the TFT array substrate through an oxide semiconductor, the oxide semiconductor of the pixel electrode is processed into a hydrogen-doped oxide semiconductor, the conductivity of the pixel electrode is increased, an etching barrier layer, a source/drain electrode layer and a passivation layer are exposed out of the pixel electrode, the source/drain electrode layer is respectively and electrically connected with the active layer, and the drain electrode is also electrically connected with the pixel electrode.
Description
Technical field
The present invention relates to oxide film transistor array substrates, and in particular, to a kind of oxide thin film transistor battle array
Row substrate and its manufacturing method.
Background technology
Currently, as shown in Figure 1, twisted liquid crystal display device（TN-LCD）Oxide thin film transistor（TFT）Array base
Plate includes TFT devices 1, pixel unit 2 and binding region 3；Wherein,
TFT devices 1 include：Liner plate 11, gate insulation layer 13, the active layer 14 being made of oxide semiconductor, is carved grid 12
Barrier layer 15, metal source/drain electrode layer 16 and passivation layer 17 are lost, metal source and drain electrodes layer 16 includes source electrode 161 and electric leakage
Pole 162, source electrode 161 and drain electrode 162 are electrically connected by via on etching barrier layer 15 and active layer 14 respectively；
Pixel unit 2 includes liner plate 11, gate insulation layer 13, etching barrier layer 15, metal source/drain electrode layer 16, passivation layer
17 and pixel ITO layer 18, pixel ITO layer includes pixel electrode 181, and pixel electrode 181 passes through via on passivation layer 17 and leakage
Electrode 162 is electrically connected；
Binding region 3 includes：Liner plate 11, grid 12, gate insulation layer 13, etching barrier layer 15, passivation layer 17 and ITO bindings
Electrode layer 182, ITO bind electrode and pass through the via and grid on via and gate insulation layer 13, etching barrier layer 15 and passivation layer 17
Pole 12 is electrically connected.
During the work time, the grid 12 being connect with grid line conducts scanning gate signal to tft array substrate shown in FIG. 1, makes
Active layer 14 forms current channel, and active layer 14 conducts the grayscale signal from the source electrode 161 being connect with data line to leakage
Electrode 162, drain electrode 162 conduct grayscale signal to pixel electrode 18 so that are formed between pixel electrode 18 and public electrode
Electric field, control liquid crystal molecule overturning.
But tft array substrate is in actual production shown in Fig. 1, the number of plies is more to cause production cost higher.
Invention content
In view of this, an embodiment of the present invention provides a kind of oxide film transistor array substrates applied to TN-LCD
And its manufacturing method, to solve the oxide film transistor array substrate number of plies in the prior art applied to TN-LCD compared with
Lead to the higher problem of production cost more.
Technical solution of the embodiment of the present invention is as follows：
A kind of oxide thin film transistor tft array substrate, including：TFT devices；The TFT devices include：Substrate；Grid
Pole is formed over the substrate；Gate insulation layer is formed on the grid and the substrate；It is exhausted to be formed in the grid for active layer
In edge layer, it is arranged by oxide semiconductor material and pixel electrode same layer, the pixel electrode is exposed；Wherein, the pixel
The material of electrode is the oxide semiconductor of hydrogen loading；Etching barrier layer is formed on the active layer；Source/drain electrode layer is formed
On the etching barrier layer, including source electrode and drain electrode, the source electrode and the drain electrode pass through the etching respectively
Via on barrier layer is electrically connected with the active layer, and the drain electrode is electrically connected with the pixel electrode；Passivation layer is formed in
In the source/drain electrode layer.
A kind of production method of oxide thin film transistor tft array substrate, including：Grid is formed on substrate；Institute
It states and forms gate insulation layer on substrate and the grid, to cover the grid；It is partly led by oxide on the gate insulation layer
Body material forms active layer and pixel electrode, and the oxide that the oxide semiconductor processing of the pixel electrode is hydrogen loading is partly led
Body；Etching barrier layer is formed on the active layer, and the graphical etching barrier layer exposes the pixel electrode and obtains
Via on the etching barrier layer；Source/drain electrode layer is formed on the etching barrier layer, the graphical source/drain electrode
Layer obtains the source/drain electrode of TFT devices, and exposes the pixel electrode, and the source/drain electrode is hindered by the etching respectively
Via in barrier is electrically connected with the active layer, and the drain electrode is also electrically connected with the pixel electrode；In source/drain electricity
Passivation layer is formed on extremely, to cover the source/drain electrode, and the graphical passivation layer exposes the pixel electrode.
The embodiment of the present invention is by tft array substrate, by the oxide semiconductor material position of level where active layer
Part in pixel region is used as pixel electrode after carrying out hydrogen loading processing, makes active layer in TFT devices and pixel region
Pixel electrode same layer is arranged, and etching barrier layer, source/drain electrode layer and passivation layer expose pixel by patterning process
Electrode, source-drain electrode are electrically connected with active layer respectively, and drain electrode is also electrically connected with pixel electrode, compared with the prior art in oxygen
Compound tft array substrate reduces the manufacturing process of pixel ITO layer, can reduce being produced into for oxide TFT array substrate
This.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.The purpose of the present invention and other advantages can be by the explanations write
Specifically noted structure is realized and is obtained in book, claims and attached drawing.
Description of the drawings
Fig. 1 is the structural schematic diagram of the oxide TFT array substrate of TN-LCD in the prior art；
Fig. 2 is the structural schematic diagram of the oxide TFT array substrate provided in an embodiment of the present invention applied to TN-LCD；
Fig. 3 is the work of the production method of the oxide TFT array substrate provided in an embodiment of the present invention applied to TN-LCD
Make flow chart；
Fig. 4 is that another structure of the oxide TFT array substrate provided in an embodiment of the present invention applied to TN-LCD is shown
It is intended to；
Fig. 5 is the another of the production method of the oxide TFT array substrate provided in an embodiment of the present invention applied to TN-LCD
One work flow diagram；
Fig. 6 is that another structure of the oxide TFT array substrate provided in an embodiment of the present invention applied to TN-LCD is shown
It is intended to.
Specific implementation mode
The embodiment of the present invention is illustrated below in conjunction with attached drawing, it should be understood that embodiment described herein is only used
In the description and interpretation present invention, it is not intended to limit the present invention.
Cause to give birth to for the oxide film transistor array substrate number of plies in the prior art applied to TN-LCD is more
The higher problem of cost is produced, an embodiment of the present invention provides a kind of oxide film transistor array substrates applied to TN-LCD
And its manufacturing method, to solve the problems, such as this.
Embodiment one
Fig. 2 shows the oxide TFT array substrates provided in an embodiment of the present invention applied to TN-LCD, including：TFT devices
The pixel electrode 22 of part 21 and the pixel unit being connect with TFT devices.Wherein, TFT devices 21 include substrate 211, are formed in lining
Grid 212 on bottom 211, is formed on gate insulation layer 213 gate insulation layer 213 being formed on grid 212 and substrate 211
Active layer 214, active layer 214 are arranged by oxide semiconductor material and 22 same layer of pixel electrode, and pixel electrode 22 is exposed, as
The material of plain electrode 22 is the oxide semiconductor of hydrogen loading, increases the electric conductivity of pixel electrode 22；Etching barrier layer 215 is formed
On active layer 214, pixel electrode 22 is exposed；Source/drain electrode layer 216 is formed on etching barrier layer 215, including source electricity
Pole 2161 and drain electrode 2162, source electrode 2161 and drain electrode 2162 respectively by via 2151 on etching barrier layer 215 with
Active layer 214 is electrically connected, and drain electrode 2162 is also electrically connected with pixel electrode 22, and source/drain electrode layer 216 exposes pixel electrode
22；Passivation layer 217 is formed in source/drain electrode layer 216, and exposes pixel electrode 22.
Preferably, increase with the oxide semiconductor that the material of source/drain electrode electrical connections is hydrogen loading in active layer 214
Add the electric conductivity of coupling part.
In structure as shown in Figure 2, grid 212 connects grid line, scanning signal of the conduction from grid line, makes active layer
Current channel is formed in 214, is connected between the source electrode 2161 being connected with active layer 214 and drain electrode 2162, source electrode
The grayscale signal received is conducted to drain electrode 2162, drain electrode 2162 and 22 electricity of pixel electrode by 2161 by active layer 214
Grayscale signal is conducted to pixel electrode 22 by connection, to form electric field between pixel electrode 22 and public electrode, controls liquid
Brilliant molecule overturning, and the oxide semiconductor that the material of pixel electrode 22 is hydrogen loading, the oxide semiconductor of hydrogen loading is with good
Good translucency, thus structure shown in Fig. 2 can realize the function of oxide TFT array substrate.
To according to structure as shown in Figure 2, by oxide semiconductor by the active layer 214 and pixel in TFT devices
22 same layer of pixel electrode in region is arranged, and is the oxide semiconductor of hydrogen loading by the oxide semiconductor processing of pixel electrode 22,
Increase the electric conductivity of pixel electrode, and etching barrier layer 215, source/drain electrode layer 216 and passivation layer 217 expose picture
Plain electrode 22, source electrode 2161 and drain electrode 2162 respectively with active layer 214 be electrically connected, drain electrode 2162 also with pixel electrode 22
Electrical connection, compared with the prior art in oxide TFT array substrate, reduce pixel ITO layer, oxide TFT can be reduced
The production cost of array substrate.
Based on identical inventive concept, the embodiment of the present invention additionally provides a kind of TFT gusts of oxide applied to TN-LCD
The production method of row substrate, as shown in figure 3, this method includes：
Step 301 forms grid 212 on substrate 211；
Step 302 forms gate insulation layer 213 on substrate 211 and grid 212, to cover grid 212 and substrate 211；
Step 303 by oxide semiconductor material forms active layer 214 and pixel electrode 22 on gate insulation layer 213,
By the oxide semiconductor that the oxide semiconductor processing of pixel electrode 22 is hydrogen loading；
Specifically, it is initially formed oxide semiconductor layer on gate insulation layer 213, by hydrogen loading or anoxic process by the oxidation
The part processing that object semiconductor layer is located at pixel unit is the oxide semiconductor of hydrogen loading, the oxide semiconductor part of the hydrogen loading
The as pixel electrode 22 of pixel unit, it is active layer 214 which, which is located at the part in TFT devices,；
Step 304 forms etching barrier layer 215 on active layer 214, and graphical etching barrier layer exposes pixel electrode
22 and obtain the via 2151 on etching barrier layer 215；
Step 305 forms source/drain electrode layer on the etching barrier layer of each TFT devices being connect with pixel unit
216, graphical source/drain electrode layer 216 obtains source/drain electrode 2161,2162, and exposes pixel electrode 22, source/drain electrode
2161,2162 be electrically connected respectively with active layer 214 by the via 2151 on etching barrier layer 215, drain electrode 2162 also with picture
Plain electrode 22 is electrically connected；
Preferably, it can also will be electrically connected with source/drain electrode 216 in active layer 214 by hydrogen loading technique or anoxic process
Part oxide semiconductor processing be hydrogen loading oxide semiconductor, enhance the electric conductivity of coupling part；
Step 306 forms passivation layer 217 in source/drain electrode 216, to cover source/drain electrode 2161,2162, and figure
Change 217 layers of passivation and exposes pixel electrode 22.
According to method as shown in Figure 3, by 22 same layer of pixel electrode of the active layer 214 and pixel region in TFT devices
The oxide semiconductor that the oxide semiconductor processing of pixel electrode 22 is hydrogen loading is increased the electric conductivity of pixel electrode by setting
Can, and so that etching barrier layer 215, source/drain electrode layer 216 and passivation layer 217 is exposed pixel electricity by patterning process
Pole 22, source electrode 2161 and drain electrode 2162 are electrically connected with active layer 214 respectively, and drain electrode 2162 is also electrically connected with pixel electrode 22
Connect, compared with the prior art in oxide TFT array substrate, reduce pixel ITO layer, oxide tft array can be reduced
The production cost of substrate.
Embodiment two
The structure that the TFT devices and pixel unit in oxide tft array are provided in embodiment one, in real oxide
In the specific production process of tft array substrate, TFT devices, pixel unit and binding region are all same in a production process
When construct, Fig. 4 shows the concrete structure of TFT devices 21, pixel unit 23 and binding region 24, structure shown in Fig. 4
In structure shown in Fig. 3, binding region 24 includes：Substrate 211；The grid 212 being formed on substrate 211；It is formed in grid 212
With the gate insulation layer 213 on substrate 211；The etching barrier layer 215 being formed on gate insulation layer 213；It is formed in etching barrier layer
Electrode layer 218 on 215, and electrode layer 218 passes through the via 2152 and grid on etching barrier layer 215 and gate insulation layer 213
The electrical connection of pole 212 is as binding electrode；The passivation layer 217 being formed on electrode layer 218, and expose binding electrode.
By structure as shown in Figure 4, compared with the prior art in oxide TFT array substrate, reduce pixel ITO
Layer, can reduce the production cost of oxide TFT array substrate.
Based on identical inventive concept, the embodiment of the present invention additionally provides a kind of making side of oxide TFT array substrate
Method, as shown in figure 5, this method includes：
Step 501, in the binding region 24 being connect with the pixel region being made of multiple pixel units 23, in substrate
211 and grid 212 on form gate insulation layer 213 after, etching barrier layer 215, graphical etching resistance are formed on gate insulation layer 213
Barrier 215 and gate insulation layer 213 obtain via 2152；
Step 502 forms electrode layer 218 on etching barrier layer 215, and electrode layer 218 passes through etching barrier layer 215 and grid
Via 2152 on insulating layer 213 is electrically connected with grid 212 as binding electrode；
Step 503 forms passivation layer 217 on electrode layer 218, to cover electrode layer 218 and etching barrier layer 215, and
And graphical passivation layer exposes binding electrode.
During specific implementation, method is the same manufacturing process to method shown in Fig. 5 as shown in figure 3, is distinguished
It is the binding electrode also further obtained by method shown in fig. 5 in binding region.
By method as shown in Figure 5, pixel ITO layer in the prior art can be also reduced, oxide TFT can be reduced
The production cost of array substrate.
Embodiment three
Due to 218 generally use metal material of source/drain electrode layer 216 and electrode layer, in skill provided in an embodiment of the present invention
In art scheme, if electrode layer 218 uses metal material, it will lead to the metal problem of oxidation for binding electrode.It is asked for this
Topic, the embodiment of the present invention is made that improvement to source/drain electrode layer 216 and electrode layer 218, as shown in fig. 6, source-drain electrode layer 216
Include metal electrode layer and protective layer with electrode layer 218, the material of protective layer is tin indium oxide, therefore can also claim protective layer
For ITO electrode layer, specifically, source-drain electrode layer 216 includes source/drain metal electrode layer 2163 and protective layer, that is, source/drain ITO electrode
Layer 2164, source and drain ITO electrode layer 2164 is formed on source/drain metal electrode layer 2163, and electrode layer 218 includes metal electrode layer
2181 and protective layer, that is, ITO electrode layer 2182, ITO electrode layer 2182 be located on metal electrode layer 2181.
By structure shown in fig. 6, ITO electrode layer is located on metal electrode layer, metal electrode layer can be avoided to expose
In air, to avoid the problem that metal electrode layer aoxidizes.
Based on identical inventive concept, the process of oxide TFT array substrate as shown in Figure 6 is manufactured, as shown in figure 3 process
Phase region method for distinguishing is：Source/drain metal electrode layer 2163 is formed on etching barrier layer 215, in source/drain metal electrode layer
Source/drain ITO electrode layer 2164 is formed on 2163, graphical source/drain metal electrode layer 2163 and source/drain ITO electrode layer 2164 obtain
To source electrode 2161 and drain electrode 2162；
The process for manufacturing oxide TFT array substrate as shown in Figure 6 is with the method for distinguishing of process phase region shown in Fig. 5：
Metal electrode layer 2181 is formed on etching barrier layer 215, ITO electrode layer 2182 is formed on metal electrode layer 2181, graphically
Metal electrode layer 2181 and ITO electrode layer 2182 obtain source electrode and drain electrode.
In conclusion in tft array substrate provided in an embodiment of the present invention, by oxide semiconductor by TFT devices
In active layer and pixel region the setting of pixel electrode same layer, by the oxygen that the processing of the oxide semiconductor of pixel electrode is hydrogen loading
Compound semiconductor increases the electric conductivity of pixel electrode, and etching barrier layer, source/drain electrode layer and passivation layer expose
Pixel electrode, source-drain electrode are electrically connected with active layer respectively, and drain electrode is also electrically connected with pixel electrode, compared with the prior art in
Oxide TFT array substrate, reduce pixel ITO layer, the production cost of oxide TFT array substrate can be reduced.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (6)
1. a kind of oxide thin film transistor tft array substrate, which is characterized in that including：TFT devices；The TFT devices packet
It includes：
Substrate；
Grid is formed over the substrate；
Gate insulation layer is formed on the grid and the substrate；
Active layer is formed on the gate insulation layer, is arranged by oxide semiconductor material and pixel electrode same layer, the picture
Plain electrode is exposed；Wherein, the material of the pixel electrode is the oxide semiconductor of hydrogen loading；
Etching barrier layer is formed on the active layer；
Source/drain electrode layer is formed on the etching barrier layer, including source electrode and drain electrode, the source electrode and the leakage
Electrode is electrically connected by the via on the etching barrier layer with the active layer respectively, the drain electrode and the pixel electrode
Electrical connection；The source/drain electrode layer includes：Source/drain metal electrode layer and protective layer, the source/drain metal electrode layer are formed in
On the etching barrier layer, the protective layer is formed on the source/drain metal electrode layer, and the material of the protective layer is oxidation
Indium tin；
Passivation layer is formed in the source/drain electrode layer；
Further include the binding region being connect with the pixel region being made of multiple pixel units, the electrode layer in the binding region
Including：
Metal electrode layer and protective layer, the metal electrode layer are formed on the etching barrier layer, and the protective layer is formed in
On the metal electrode layer, the material of the protective layer is tin indium oxide.
2. oxide thin film transistor tft array substrate according to claim 1, which is characterized in that in the active layer
Material with the source/drain electrode electrical connections is the oxide semiconductor of hydrogen loading.
3. oxide thin film transistor tft array substrate according to claim 1, which is characterized in that the binding region
Including：
The substrate；
Grid is formed over the substrate；
The gate insulation layer is formed on the grid and the substrate；
The etching barrier layer is formed on the gate insulation layer；
Electrode layer forms on the etching barrier layer, and passes through the mistake on the etching barrier layer and the gate insulation layer
Hole is electrically connected with the grid as binding electrode；
The passivation layer is formed on the electrode layer, and exposes the binding electrode.
4. a kind of production method of oxide thin film transistor tft array substrate, which is characterized in that including：
Grid is formed on substrate；
Gate insulation layer is formed on the substrate and the grid, to cover the grid and the substrate；
Active layer and pixel electrode are formed by oxide semiconductor material on the gate insulation layer, by the pixel electrode
Oxide semiconductor processing is the oxide semiconductor of hydrogen loading；
Etching barrier layer is formed on the active layer, and the graphical etching barrier layer exposes the pixel electrode and obtains
Via on the etching barrier layer；
Source/drain electrode layer is formed on the etching barrier layer, and the graphical source/drain electrode layer obtains the source/drain of TFT devices
Electrode, and the pixel electrode is exposed, the source/drain electrode has by the via on the etching barrier layer with described respectively
Active layer is electrically connected, and the drain electrode is also electrically connected with the pixel electrode；If the source/drain electrode layer includes：Source/drain metal electricity
Pole layer and protective layer；Then, the graphical source/drain electrode layer obtains source/drain electrode, specifically includes：In the etching barrier layer
It is upper to form the source/drain metal electrode layer, the protective layer is formed on the source/drain metal electrode layer, the graphical source/
Leakage metal electrode layer and the protective layer obtain the source electrode and the drain electrode, and the material of the protective layer is indium oxide
Tin；
Passivation layer is formed in the source/drain electrode, to cover the source/drain electrode, and the graphical passivation layer exposes
The pixel electrode；
In the binding region being connect with the pixel region being made of multiple pixel units, the graphical electrode layer obtains described
Electrode layer in binding region, the electrode layer in the binding region include：Metal electrode layer and protective layer；Wherein, graphically
The electrode layer, specifically includes：The metal electrode layer is formed on the etching barrier layer, the shape on the metal electrode layer
At the protective layer, the material of the protective layer is tin indium oxide.
5. according to the method described in claim 4, it is characterized in that, will be in the active layer by hydrogen loading technique or anoxic process
The oxide semiconductor part processing being electrically connected with the source/drain electrode is the oxide semiconductor of hydrogen loading.
6. according to the method described in claim 4, it is characterized in that, the method further includes：
In the binding region being connect with the pixel region being made of multiple pixel units, the shape on the substrate and the grid
After the gate insulation layer, the etching barrier layer is formed on the gate insulation layer, the graphical etching barrier layer and institute
It states gate insulation layer and obtains via；
Electrode layer is formed on the etching barrier layer, and the electrode layer passes through on the etching barrier layer and the gate insulation layer
Via be electrically connected with the grid as binding electrode；
The passivation layer is formed on the electrode layer, to cover the electrode layer and the etching barrier layer, and it is graphical
The passivation layer exposes the binding electrode.
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| CN104795401A (en) * | 2015-04-09 | 2015-07-22 | 深圳市华星光电技术有限公司 | Thin-film transistor array substrate and method for manufacturing same |
| CN105655291B (en) * | 2016-01-07 | 2019-03-22 | 京东方科技集团股份有限公司 | A kind of production method of array substrate, array substrate and display panel |
| US9576984B1 (en) * | 2016-01-14 | 2017-02-21 | Hon Hai Precision Industry Co., Ltd. | Thin film transistor array panel and conducting structure |
| CN105845694A (en) * | 2016-03-28 | 2016-08-10 | 深圳市华星光电技术有限公司 | Film transistor, manufacturing method of film transistor and liquid crystal display panel |
| CN106783889B (en) * | 2017-01-13 | 2020-01-07 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display device |
| CN112599535A (en) * | 2020-12-10 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
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