CN103928530B - Oxide thin film transistor array substrate and manufacturing method - Google Patents

Oxide thin film transistor array substrate and manufacturing method Download PDF

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CN103928530B
CN103928530B CN201310170052.9A CN201310170052A CN103928530B CN 103928530 B CN103928530 B CN 103928530B CN 201310170052 A CN201310170052 A CN 201310170052A CN 103928530 B CN103928530 B CN 103928530B
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layer
electrode
source
formed
etch stop
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CN103928530A (en
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楼均辉
霍思涛
姜文鑫
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上海天马微电子有限公司
天马微电子股份有限公司
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Abstract

本发明实施例公开了种氧化物薄膜晶体管阵列基板及其制造方法,本发明实施例通过在TFT阵列基板中,通过氧化物半导体将TFT器件中的有源层和像素区域的像素电极同层设置,将像素电极的氧化物半导体处理为掺氢的氧化物半导体,增加像素电极的导电性能,并且刻蚀阻挡层、源/漏电极层和钝化层均暴露出像素电极,源漏电极分别和有源层电连接,漏电极还与像素电极电连接,相比于现有技术中的氧化物TFT阵列基板,减少了像素ITO层,能够降低氧化物TFT阵列基板的生产成本。 Examples of the types disclosed embodiments oxide thin film transistor array substrate and a manufacturing method of the present invention, for example, by the TFT array substrate, the pixel electrode by an oxide semiconductor layer and the active region of the pixel TFT device in the embodiment of the present invention is provided with the layer the pixel electrode is an oxide semiconductor hydrogen doping process is an oxide semiconductor, to increase the conductivity of the pixel electrode, and the etch stop layer, source / drain electrode layer and the passivation layer to expose each pixel electrode, the source and drain electrodes, respectively, an active layer electrically connected to the drain electrode is also electrically connected to the pixel electrode, the TFT array substrate as compared to the oxide of the prior art, reducing the pixel ITO layer, the production cost can be reduced oxide TFT array substrate.

Description

氧化物薄膜晶体管阵列基板及其制造方法 Oxide thin film transistor array substrate and manufacturing method

技术领域 FIELD

[0001]本发明涉及氧化物薄膜晶体管阵列基板,具体地,涉及一种氧化物薄膜晶体管阵列基板及其制造方法。 [0001] The present invention relates to an oxide thin film transistor array substrate, in particular, it relates to an oxide thin film transistor array substrate and a manufacturing method thereof.

背景技术 Background technique

[0002]目前,如图1所示,扭曲液晶显示器件(TN-LCD)的氧化物薄膜晶体管(TFT)阵列基板包括TFT器件1、像素单元2和绑定区域3;其中, [0002] Currently, shown in Figure 1, oxide thin film transistor twisted liquid crystal display device (TN-LCD) of the (TFT) device includes a TFT array substrate 1, the pixel section 2 and the binding region 3; wherein,

[0003] TFT器件1包括:衬板11、栅极12、栅绝缘层13、由氧化物半导体构成的有源层14、刻蚀阻挡层15、金属源/漏电极层16和钝化层17,金属源漏电极层16中包括源电极161和漏电极162,源电极161和漏电极162分别通过刻蚀阻挡层15上的过孔和有源层14电连接; [0003] TFT device 1 comprising: a backing plate 11, the gate 12, the gate insulating layer 13, an active layer 14 made of an oxide semiconductor, an etch stop layer 15, the metal source / drain electrode layer 16 and the passivation layer 17 , source-drain metal electrode layer 16 includes a source electrode 161 and drain electrode 162, source electrode 161 and drain electrode 162 respectively via hole etch stop layer 15 on the active layer 14 and the electrical connector;

[0004]像素单元2包括衬板11、栅绝缘层13、刻蚀阻挡层15、金属源/漏电极层16、钝化层17和像素ITO层18,像素ITO层包括像素电极181,像素电极181通过钝化层17上的过孔与漏电极162电连接; [0004] The pixel unit 2 includes a backing plate 11, the gate insulating layer 13, etch stop layer 15, the metal source / drain electrode layer 16, passivation layer 17 and the pixel ITO layer 18, the pixel ITO layer 181 includes a pixel electrode, the pixel electrode 181 electrode 162 is electrically connected through a via hole on the passivation layer 17 and the drain;

[0005]绑定区域3包括:衬板11、栅极12、栅绝缘层13、刻蚀阻挡层15、钝化层17和ITO绑定电极层182, ITO绑定电极通过过孔与栅绝缘层13、刻蚀阻挡层15和钝化层17上的过孔与栅极12电连接。 [0005] 3 binding region comprising: a backing plate 11, the gate 12, the gate insulating layer 13, etch stop layer 15, passivation layer 17 and the ITO electrode layer 182 binding, binding ITO electrode through the via hole and the gate insulating layer 13, the etch stop layer is electrically connected to the through hole 12 on the gate electrode 15 and the passivation layer 17.

[0006]图1所示的TFT阵列基板在工作过程中,与栅线连接的栅极12传导栅扫描信号,使有源层14形成电流通道,有源层14将来自与数据线连接的源电极161的灰阶信号传导至漏电极162,漏电极162将灰阶信号传导至像素电极18,使得像素电极18与公共电极之间形成电场,控制液晶分子翻转。 The TFT array substrate shown in [0006] FIG. 1 during operation, the gate scanning signal pass-gate 12 is connected to the gate line, the active layer 14 forms a current path from the active layer 14, a source connected to the data line grayscale signal conductive electrode 161 to the drain electrode 162, drain electrode 162 grayscale signal to the pixel electrode 18 conductive, so that the electric field is formed between the pixel electrode 18 and the common electrode, liquid crystal molecules inverted.

[0007] 但是,图1所示TFT阵列基板在实际生产中,层数较多导致生产成本较高。 [0007] However, the TFT array substrate shown in FIG. 1 the actual production, resulting in higher production costs more layers.

发明内容 SUMMARY

[0008] 有鉴于此,本发明实施例提供了一种应用于TN-LCD的氧化物薄膜晶体管阵列基板及其制造方法,用以解决现有技术中的应用于TN-LCD的氧化物薄膜晶体管阵列基板层数较多导致生产成本较高的问题。 [0008] In view of this, the embodiment provides an oxide thin film transistor array substrate and manufacturing method is applied to a TN-LCD of the present invention to solve the TN-LCD is applied to an oxide thin film transistor of the prior art the array substrate layers more leads to higher production costs.

[0009] 本发明实施例技术方案如下: [0009] Embodiments of the present invention is as follows:

[0010] 一种氧化物薄膜晶体管TFT阵列基板,包括:TFT器件;所述TFT器件包括:衬底;栅极,形成在所述衬底上;栅绝缘层,形成在所述栅极和所述衬底上;有源层,形成在所述栅绝缘层上,通过氧化物半导体材质与像素电极同层设置,所述像素电极裸露;其中,所述像素电极的材质为掺氢的氧化物半导体;刻蚀阻挡层,形成在所述有源层上;源/漏电极层,形成在所述刻蚀阻挡层上,包括源电极和漏电极,所述源电极和所述漏电极分别通过所述刻蚀阻挡层上的过孔与所述有源层电连接,所述漏电极与所述像素电极电连接•,钝化层,形成在所述源/漏电极层上。 [0010] An oxide thin film transistor TFT array substrate, comprising: a TFT device; the TFT device comprising: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode and the said substrate; an active layer formed on the gate insulating layer, the oxide semiconductor material in the same layer as the pixel electrode, the pixel electrode is exposed; wherein the pixel electrode is made of a hydrogen-doped oxide the semiconductor; etch stop layer, is formed on the active layer; source / drain electrode layer is formed on the etch stop layer including a source electrode and a drain electrode, said source electrode and the drain electrode respectively the electrically active layer is etched through the hole blocking layer and the connection, • the drain electrode is connected to the pixel electrode, a passivation layer formed on the source / drain electrode layer.

[0011] 一种氧化物薄膜晶体管TFT阵列基板的制作方法,包括:在衬底上形成栅极;在所述衬底和所述栅极上形成栅绝缘层,以覆盖所述栅极;在所述栅绝缘层上通过氧化物半导体材质形成有源层和像素电极,将所述像素电极的氧化物半导体处理为掺氢的氧化物半导体;在所述有源层上形成刻蚀阻挡层,图形化所述刻蚀阻挡层暴露出所述像素电极并得到所述刻蚀阻挡层上的过孔;在所述刻蚀阻挡层上形成源/漏电极层,图形化所述源/漏电极层得到TFT器件的源/漏电极,并暴露出所述像素电极,所述源/漏电极分别通过所述刻蚀阻挡层上的过孔与所述有源层电连接,所述漏电极还与所述像素电极电连接;在所述源/漏电极上形成钝化层,以覆盖所述源/漏电极,并图形化所述钝化层暴露出所述像素电极。 [0011] The manufacturing method of the TFT array substrate of an oxide thin film transistor comprising: a gate electrode formed on a substrate; forming a gate insulating layer on the substrate and the gate to cover the gate electrode; the on the gate insulating layer is formed by an oxide semiconductor material of the active layer and the pixel electrode, an oxide semiconductor of the pixel electrode is an oxide semiconductor hydrogen doping process; forming an etch stop layer on the active layer, exposing the patterning said etch stop layer and the pixel electrode through the hole obtained on said etch stop layer; forming a source / drain electrode layer on the etch stop layer, patterning the source / drain electrodes layer obtained TFT device source / drain electrode, and exposing the pixel electrode, the source / drain electrodes are electrically connected to said active layer through a via hole on said etch stop layer, said further drain electrode connected to the pixel electrode; is formed on the source / drain electrode passivation layer to cover the source / drain electrode, and patterning the passivation layer to expose the pixel electrode.

[0012]本发明实施例通过在TFT阵列基板中,将有源层所在层面的氧化物半导体材质位于像素区域中的部分进行掺氢处理后作为像素电极,使TFT器件中的有源层和像素区域的像素电极同层设置,并且刻蚀阻挡层、源/漏电极层和钝化层均通过图形化工艺暴露出像素电极,源漏电极分别和有源层电连接,漏电极还与像素电极电连接,相比于现有技术中的氧化物TFT阵列基板,减少了像素ITO层的制造工艺,能够降低氧化物TFT阵列基板的生产成本。 [0012] In the embodiment illustrated by the TFT array substrate, the dimension of the part of the pixel region where the oxide semiconductor active layer material located hydrogen doping process for the present invention as a pixel electrode, and a pixel TFT of the active layer of the device a pixel electrode region disposed in the same layer, and the etch stop layer, source / drain electrode layer and the passivation layer by a patterning process to expose each pixel electrode, the source and drain electrodes are respectively electrically connected to the active layer, the drain electrode and the pixel electrode is also electrically connected, the oxide TFT array substrate as compared to the prior art, reduces the manufacturing process of the pixel ITO layer, it is possible to reduce production costs oxide TFT array substrate.

[0013] 本发明的其它特征和优点将在随后的说明书中阐述,并且,部分地从说明书中变得显而易见,或者通过实施本发明而了解。 [0013] Other features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or learned by practice of the present invention. 本发明的目的和其他优点可通过在所写的说明书、权利要求书、以及附图中所特别指出的结构来实现和获得。 The objectives and other advantages of the invention may be realized and attained by the written description, claims, and drawings structure particularly pointed out.

附图说明 BRIEF DESCRIPTION

[0014] 图1为现有技术中TN-LCD的氧化物TFT阵列基板的结构示意图; [0014] Figure 1 is a schematic view of an oxide TFT array substrate structure of TN-LCD of the prior art;

[0015] 图2为本发明实施例提供的应用于TN-LCD的氧化物TFT阵列基板的结构示意图; [0015] Fig 2 a schematic view of the structure of TN-LCD is applied to an oxide TFT array substrate according to an embodiment of the present invention;

[0016] 图3为本发明实施例提供的应用于TN-LCD的氧化物TFT阵列基板的制作方法的工作流程图; _ [0016] The flow chart of FIG. 3 used in the production method of an oxide TFT array substrate of the TN-LCD according to an embodiment of the present invention; _

[0017] 图4为本发明实施例提供的应用于TN-LCD的氧化物TFT阵列基板的另一种结构示意图; [0017] Fig 4 a schematic view of another structure of TN-LCD is applied to the oxide TFT array substrate according to an embodiment of the present invention;

[0018] 图5为本发明实施例提供的应用于TN-LCD的氧化物TFT阵列基板的制作方法的另一工作流程图; [0018] FIG. 5 a flowchart of another method of manufacturing an oxide TFT array substrate is applied to the TN-LCD according to an embodiment of the present invention;

[0019] 图6为本发明实施例提供的应用于TN-LCD的氧化物TFT阵列基板的另一种结构示意图。 [0019] Fig 6 a schematic view of another structure of TN-LCD is applied to the oxide TFT array substrate according to an embodiment of the present invention.

具体实施方式 Detailed ways

[0020] 以下结合附图对本发明的实施例进行说明,应当理解,此处所描述的实施例仅用于说明和解释本发明,并不用于限定本发明。 [0020] The following embodiments in conjunction with the accompanying drawings of embodiments of the present invention will be described, it should be understood that the embodiments described herein only to illustrate and explain the present invention and are not intended to limit the present invention.

[0021] 针对现有技术中的应用于TN-LCD的氧化物薄膜晶体管阵列基板层数较多导致生产成本较高的问题,本发明实施例提供了一种应用于TN-LCD的氧化物薄膜晶体管阵列基板及其制造方法,用以解决该问题。 [0021] For the prior art TN-LCD is applied to a thin film transistor array substrate oxide layers resulting in higher production costs more problems, embodiments of the present invention provides a TN-LCD is applied to an oxide film transistor array substrate and a manufacturing method to solve the problem.

[0022] 实施例一 [0022] Example a

[0023]图2示出了本发明实施例提供的应用于TN-LCD的氧化物TFT阵列基板,包括:TFT器件21和与TFT器件连接的像素单元的像素电极22。 [0023] FIG. 2 shows a TN-LCD of the present invention is applied to an oxide TFT array substrate according to an embodiment includes: a pixel unit and the pixel electrode 21 connected to the TFT device 22 TFT device. 其中,TFT器件21包括衬底211、形成在衬底211上的栅极212、形成在栅极212和衬底211上的栅绝缘层213、形成在栅绝缘层213上的有源层214,有源层214通过氧化物半导体材质与像素电极22同层设置,像素电极22裸露,像素电极22的材质为掺氢的氧化物半导体,增加像素电极22的导电性;刻蚀阻挡层215,形成在有源层214上,暴露出像素电极22;源/漏电极层216,形成在刻蚀阻挡层215上,包括源电极2161和漏电极2162,源电极2161和漏电极2162分别通过刻蚀阻挡层215上的过孔2151与有源层214电连接,漏电极2162还与像素电极22电连接,源/漏电极层216暴露出像素电极22;钝化层217,形成在源/漏电极层216上,并暴露出像素电极22。 Wherein, the TFT device 21 comprises a substrate 211, a gate 212 formed on a substrate 211, a gate is formed on the gate electrode 212 and the substrate 211 insulating layer 213, the active layer 214 is formed on the gate insulating layer 213, the active layer 214 by the oxide semiconductor layer 22 with the material of the pixel electrodes, the pixel electrode 22 is exposed, the material of the pixel electrode 22 is hydrogen-doped oxide semiconductor, to increase the conductivity of the pixel electrode 22; etch stop layer 215 is formed on the active layer 214, to expose the pixel electrode 22; source / drain electrode layer 216 is formed on the etch stop layer 215, including a source electrode 2161 and drain electrode 2162, the source electrode 2161 and drain electrode 2162 by etching stopper, respectively layer via hole connected electrically 2,152,151 active layer 214, the drain electrode 2162 is also electrically connected to the pixel electrode 22, the source / drain electrode layer 216 to expose the pixel electrode 22; the passivation layer 217, formed on the source / drain electrode layer 216, and exposes the pixel electrode 22.

[0024] 优选地,有源层214中与源/漏电极电连接部分的材质为掺氢的氧化物半导体,增加连接部分的导电性。 [0024] Preferably, the active layer 214 and the source / drain electrode material portion is electrically connected to a hydrogen-doped oxide semiconductor, increasing the conductive connection portion.

[0025]在如图2所示的结构中,栅极212连接栅线、传导来自栅线的扫描信号,使有源层214中形成电流通道,与有源层214相连接的源电极2161和漏电极2162之间导通,源电极21W将接收到的灰阶信号通过有源层214传导给漏电极2162,漏电极2162与像素电极22电连接、将灰阶信号传导给像素电极22,从而在像素电极22和公共电极之间形成电场,控制液晶分子翻转,并且像素电极22的材质为掺氢的氧化物半导体,掺氢的氧化物半导体具有良好的透光性,因而图2所示的结构能够实现氧化物TFT阵列基板的功能。 [0025] In the configuration shown in Figure 2, the gate connected to the gate line 212, a scanning signal from the gate conduction line, the active layer 214 is formed in the current path, the source electrode 2161 and the active layer 214 and connected to conduction between the drain electrode 2162, the source electrode 21W grayscale received signal 214 is conducted through the active layer to the drain electrode 2162, the drain electrode 2162 is electrically connected to the pixel electrode 22, the gray level signaling to the pixel electrode 22, thereby 22 is formed between the pixel electrode and the common electrode electric field, liquid crystal molecules inverted, and the pixel electrode 22 made of an oxide semiconductor is doped with hydrogen, hydrogen-doped semiconductor oxide has good transparency, and therefore shown in FIG. 2 configuration to perform functions of the oxide TFT array substrate.

[0026] 从而,根据如图2所示的结构,通过氧化物半导体将TFT器件中的有源层214和像素区域的像素电极22同层设置,将像素电极22的氧化物半导体处理为掺氢的氧化物半导体, 增加像素电极的导电性能,并且刻蚀阻挡层215、源/漏电极层216和钝化层217均暴露出像素电极22,源电极21价和漏电极21似分别和有源层214电连接,漏电极2162还与像素电极22 电连接,相比于现有技术中的氧化物TFT阵列基板,减少了像素IT0层,能够降低氧化物TFT 阵列基板的生产成本。 [0026] Thus, the configuration shown in FIG. 2, an oxide semiconductor by the pixel electrode 214 and the pixel region of the active layer of a TFT device 22 is disposed in the same layer, the pixel electrode 22 is processed into an oxide semiconductor Hydrogen an oxide semiconductor, to increase the conductivity of the pixel electrode, and the etch stop layer 215, the source / drain electrode layer 216 and the passivation layer to expose the pixel electrode 217 was 22, the source electrode 21 and drain electrode 21 similar monovalent and are active layer 214 is electrically connected to the drain electrode 2162 is also electrically connected to the pixel electrode 22, the oxide TFT array substrate as compared to the prior art, reducing the pixel IT0 layer, the production cost can be reduced oxide TFT array substrate.

[0027] 基于相同的发明构思,本发明实施例还提供了一种应用于TN-LCD的氧化物TFT阵列基板的制作方法,如图3所示,该方法包括: [0027] Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing a TN-LCD is applied to an oxide TFT array substrate shown in Figure 3, the method comprising:

[0028] 步骤301、在衬底211上形成栅极212; [0028] Step 301, the gate electrode 212 is formed on a substrate 211;

[0029]步骤302、在衬底211和栅极212上形成栅绝缘层213,以覆盖栅极212和衬底211; [0030]步骤303、在栅绝缘层213上通过氧化物半导体材质形成有源层214和像素电极22, 将像素电极22的氧化物半导体处理为掺氢的氧化物半导体; [0029] Step 302, the gate insulating layer 213 is formed on the substrate 211 and the gate 212, to cover the gate 212 and substrate 211; [0030] Step 303, formed by an oxide semiconductor material on the gate insulating layer 213 have source layer 214 and the pixel electrode 22, the pixel electrode 22 is processed into an oxide semiconductor is an oxide semiconductor doped hydrogen;

[0031]具体地,在栅绝缘层213上先形成氧化物半导体层,通过掺氢或缺氧工艺将该氧化物半导体层位于像素单元的部分处理为掺氢的氧化物半导体,该掺氢的氧化物半导体部分即为像素单元的像素电极22,该氧化物半导体层位于TFT器件中的部分即为有源层214; [0032]步骤304、在有源层214上形成刻蚀阻挡层215,图形化刻蚀阻挡层暴露出像素电极22并得到刻蚀阻挡层215上的过孔2151; [0031] Specifically, on the gate insulating layer 213 is formed before the oxide semiconductor layer, a pixel portion of the processing unit by the hydrogen doping process, or hypoxia of the oxide semiconductor layer is doped with hydrogen in the oxide semiconductor, the hydrogen doping the oxide semiconductor portion of the pixel electrode is the pixel units 22, the oxide semiconductor layer is disposed in the TFT device portion is the active layer 214; [0032] step 304, etch stop layer 215 is formed on the active layer 214, patterning the etch stop layer to expose the pixel electrode 22 and the obtained etch stop layer 215 on the via hole 2151;

[0033]步骤3〇5、在每个与像素单元连接的TFT器件的刻蚀阻挡层上形成源/漏电极层216,图形化源/漏电极层216得到源/漏电极2161、2162,并暴露出像素电极22,源/漏电极2161、2162分别通过刻蚀阻挡层215上的过孔2151与有源层214电连接,漏电极2162还与像素电极22电连接; [0033] Step 3〇5, is formed on the etch stop layer of each TFT device is connected to the pixel unit of the source / drain electrode layer 216, patterning the source / drain electrode layer 216 to obtain the source / drain electrodes 2161, 2162, and exposing the pixel electrode 22, the source / drain electrodes 2161, 2162 are electrically connected by through holes 2151 etched in the active layer 215 and the barrier layer 214, the drain electrode 2162 is also electrically connected to the pixel electrode 22;

[0034]优选地,还可以通过掺氢工艺或缺氧工艺将有源层214中与源/漏电极216电连接的部分的氧化物半导体处理为掺氢的氧化物半导体,增强连接部分的导电性; [0034] Preferably, also through hydrogen doping process or a process hypoxia active layer 214 and the source / drain electrode 216 is electrically connected to the oxide semiconductor portion of the hydrogen doping process is an oxide semiconductor, conductive connection reinforcing portion sex;

[0035]步骤306、在源/漏电极216上形成钝化层217,以覆盖源/漏电极2161、2162,并图形化钝化217层暴露出像素电极22。 [0035] Step 306, the source / drain electrode is formed on the passivation layer 217 is 216 to cover the source / drain electrodes 2161, 2162, and patterned passivation layer 22 to expose the pixel electrode 217.

[00¾]根据如图3所示的方法,将TFT器件中的有源层214和像素区域的像素电极22同层设置,将像素电极22的氧化物半导体处理为掺氢的氧化物半导体,增加像素电极的导电性能,并且通过图形化工艺使刻蚀阻挡层215、源/漏电极层216和钝化层217均暴露出像素电极22,源电极2161和漏电极2162分别和有源层214电连接,漏电极2162还与像素电极22电连接,相比于现有技术中的氧化物TFT阵列基板,减少了像素I TO层,能够降低氧化物TFT阵列基板的生产成本。 [00¾] The method shown in FIG. 3, the pixel electrode 214 and the pixel region of the active layer of a TFT device 22 is disposed in the same layer, the pixel electrode 22 is processed into an oxide semiconductor is an oxide semiconductor hydrogen doping, increased conductivity of the pixel electrode, and the etch stop layer 215 by a patterning process, the source / drain electrode layer 216 and the passivation layer to expose the pixel electrode 217 was 22, the source electrode 2161 and drain electrode 2162 are electrically active layer 214 and connections, the drain electrode 2162 is also electrically connected to the pixel electrode 22, the oxide TFT array substrate as compared to the prior art, reducing the pixel I tO layer, the production cost can be reduced oxide TFT array substrate.

[0037] 实施例二 [0037] Second Embodiment

[0038]实施例一中提供了氧化物TFT阵列中的TFT器件和像素单元的结构,在实氧化物TFT阵列基板的具体生产过程中,TFT器件、像素单元和绑定区域都是在一个生产过程中同时构造出来的,图4示出了TFT器件21、像素单元23和绑定区域24的具体结构,图4所示结构在图3所示结构上,绑定区域24包括:衬底211;形成在衬底211上的栅极212;形成在栅极212 和衬底211上的栅绝缘层213;形成在栅绝缘层213上的刻蚀阻挡层215;形成在刻蚀阻挡层215上的电极层218,并且电极层218通过刻蚀阻挡层215和栅绝缘层213上的过孔2152与栅极212电连接作为绑定电极;形成在电极层218上的钝化层217,并暴露出绑定电极。 [0038] Example embodiments provide a device structure of the TFT and the pixel unit TFT array oxides, in particular the production process of the solid oxide TFT array substrate, TFT devices, pixel unit and are bound in a production area during the same time out of the structure, Figure 4 shows a TFT device 21, the specific structure of the pixel unit 23 and the binding area 24, the structure shown in FIG. 4 in the structure shown in FIG. 3, the binding region 24 comprises: a substrate 211 ; gate electrode 211 formed on the substrate 212; the gate insulating layer 213 is formed on the gate electrode 212 and the substrate 211; etch stop layer 215 is formed on the gate insulating layer 213; is formed on the etch stop layer 215 electrode layer 218 and the layer 215 via a gate insulating layer 213 and the gate electrode 2152 connecting electrodes 212 by etching the barrier layer 218 as an electrode binding; a passivation layer 218 is formed on the electrode layer 217, and exposed the binding electrode.

[0039] 通过如图4所示的结构,相比于现有技术中的氧化物TFT阵列基板,减少了像素IT0 层,能够降低氧化物TFT阵列基板的生产成本。 [0039] By the structure shown in Figure 4, the oxide TFT array substrate as compared to the prior art, reducing the pixel IT0 layer, the production cost can be reduced oxide TFT array substrate.

[0040] 基于相同的发明构思,本发明实施例还提供了一种氧化物TFT阵列基板的制作方法,如图5所示,该方法包括: [0040] Based on the same inventive concept, an embodiment of the present invention further provides a method of manufacturing an oxide TFT array substrate shown in Figure 5, the method comprising:

[0041] 步骤501、在与由多个像素单元23组成的像素区域连接的绑定区域24上,在衬底211和栅极212上形成栅绝缘层213后,在栅绝缘层213上形成刻蚀阻挡层215,图形化刻蚀阻挡层215和栅绝缘层213得到过孔2152; After 213 [0041] Step 501, in the binding region of the pixel region is connected by a plurality of pixel units 23 24, a gate insulating layer is formed on the substrate 211 and the gate 212 formed on the gate insulating layer engraved 213 etch barrier layer 215, patterning the etch stop layer 215 and the holes 2152 213 obtained through the gate insulating layer;

[0042] 步骤502、在刻蚀阻挡层215上形成电极层218,电极层218通过刻蚀阻挡层215和栅绝缘层213上的过孔2152与栅极212电连接作为绑定电极; [0042] Step 502, the electrode layer 218 is formed on the etch stop layer 215, the electrode 218 by an etch stop layer via hole 2152 and the gate electrode 212 is connected as the binding layer 215 and the gate insulating layer 213;

[0043] 步骤503、在电极层218上形成纯化层217,以覆盖电极层218和刻蚀阻挡层215,并且图形化钝化层暴露出绑定电极。 [0043] In step 503, passivation layer 217 is formed on the electrode layer 218 to cover the electrode layer 218 and the etch stop layer 215, and patterning the passivation layer to expose the electrode binding.

[0044]在具体实现的过程中,图5所示方法与图3所示方法是同一个制造过程,相区别的是通过图5所示的方法还进一步得到绑定区域中的绑定电极。 [0044] In the specific implementation process, the method and the method shown in FIG. 3 shown in FIG. 5 are the same manufacturing process, is distinguished by the method shown in FIG. 5 further electrodes further bound binding region.

[0045] 通过如图5所示的方法,也能够减少现有技术中的像素IT0层,能够降低氧化物TFT 阵列基板的生产成本。 [0045] by the method shown in FIG. 5, a pixel can be reduced IT0 layer of the prior art, the production cost can be reduced oxide TFT array substrate.

[0046] 实施例三 [0046] Example three

[0047] 由于源/漏电极层216和电极层218通常采用金属材料,在本发明实施例提供的技术方案中,如果电极层218采用金属材料,将会导致绑定电极的金属氧化问题。 [0047] Since the source / drain electrode layer 216 and the electrode layer 218 is typically made of metal, the technical solutions provided in embodiments of the present invention, if the electrode layer 218 made of metal and metal oxide will cause problems binding electrode. 针对这一问题,本发明实施例对源/漏电极层216和电极层218做出了改进,如图6所示,源漏电极层216 和电极层218均包括金属电极层和保护层,保护层的材质为氧化铟锡,因此也可以称保护层为IT0电极层,具体地,源漏电极层216包括源/漏金属电极层2163和保护层即源/漏IT0电极层2164,源漏IT0电极层2164形成在源/漏金属电极层2163之上,电极层218包括金属电极层2181和保护层即IT0电极层2182,IT0电极层2182位于金属电极层2181之上。 To solve this problem, embodiments of the present invention the source / drain electrode layer 216 and the electrode layer 218 made improvements, shown in Figure 6, the source electrode layer 216 and the drain electrode layer 218 includes a metal electrode layer and the protective layer, a protective the material layer is indium tin oxide, and therefore can also be called protective layer IT0 electrode layer, in particular, the source and drain electrode layer 216 includes a source / drain metal electrode layer 2163 and the protective layer, i.e., the source / drain IT0 electrode layer 2164, the source-drain IT0 electrode layer 2164 is formed on the source / drain metal electrode layer 2163, an electrode layer 218 comprising a metal electrode layer 2181 and the protective layer, i.e. IT0 electrode layers 2182, 2182 IT0 electrode layer located over the metal electrode layer 2181.

[0048] 通过图6所示的结构,IT0电极层位于金属电极层之上,能够避免金属电极层暴露在空气中,从而避免金属电极层氧化的问题。 [0048] By the structure shown in FIG. 6, IT0 electrode layer is disposed on the metal electrode layer, the metal electrode layer can be prevented exposed to air, thereby avoiding the problem of oxidation of the metal electrode layer. _ _

[0049] 基于相同的发明构思,制造如图6所示氧化物TFT阵列基板的过程,与图3所示过程相区别的方法在于:在刻蚀阻挡层215上形成源/漏金属电极层2163,在源/漏金属电极层2163上形成源/漏ITO电极层2164,图形化源/漏金属电极层2163和源/漏ITO电极层2164得到源电极2161和漏电极2162; [0049] Based on the same inventive concept, the process of manufacturing the oxide TFT array substrate as shown in FIG. 6, the process shown in FIG. 3 is a method to distinguish wherein: forming the source / drain metal electrode layer on the etch stop layer 2163 215 is formed on the source / drain metal electrode layer 2163 of the source / drain electrode ITO layer 2164, patterning the source / drain metal electrode layer 2163 and the source / drain electrode layer of ITO to obtain the source electrode 2164 and drain electrode 2161 2162;

[0050] 制造如图6所示氧化物TFT阵列基板的过程,与图5所示过程相区别的方法在于:在刻蚀阻挡层215上形成金属电极层2181,在金属电极层2181上形成ITO电极层2182,图形化金属电极层2181和ITO电极层2182得到源电极和漏电极。 [0050] The process of the oxide TFT array substrate manufactured as shown in FIG. 6, the process shown in FIG. 5 that the phase difference method: forming a metal electrode layer on the etch stop layer 215 is 2181, ITO is formed on the metal electrode layer 2181 electrode layers 2182, 2181 patterned metal electrode layer and the ITO layer 2182 to obtain the source electrode and the drain electrode.

[0051] 综上所述,在本发明实施例提供的TFT阵列基板中,通过氧化物半导体将TFT器件中的有源层和像素区域的像素电极同层设置,将像素电极的氧化物半导体处理为掺氢的氧化物半导体,增加像素电极的导电性能,并且刻蚀阻挡层、源/漏电极层和钝化层均暴露出像素电极,源漏电极分别和有源层电连接,漏电极还与像素电极电连接,相比于现有技术中的氧化物TFT阵列基板,减少了像素ITO层,能够降低氧化物TFT阵列基板的生产成本。 [0051] As described above, the TFT array substrate according to an embodiment of the present invention, the oxide semiconductor layer and the pixel electrode of the active pixel region of the TFT device in the same layer, the pixel electrode of the oxide semiconductor processing hydrogen is an oxide semiconductor, to increase the conductivity of the pixel electrode, and the etch stop layer, source / drain electrode layer and the passivation layer to expose each pixel electrode, the source and drain electrodes are respectively electrically connected to the active layer, a drain electrode further is electrically connected to the pixel electrode, the TFT array substrate as compared to the oxide of the prior art, reducing the pixel ITO layer, the production cost can be reduced oxide TFT array substrate.

[0052] 显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。 [0052] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. 这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。 Thus, if these modifications and variations of the present invention fall within the claims of the invention and the scope of equivalents thereof, the present invention intends to include these modifications and variations.

Claims (6)

1. 一种氧化物薄膜晶体管TFT阵列基板,其特征在于,包括:TFT器件;所述TFT器件包括: 衬底; 栅极,形成在所述衬底上; 栅绝缘层,形成在所述栅极和所述衬底上; 有源层,形成在所述栅绝缘层上,通过氧化物半导体材质与像素电极同层设置,所述像素电极裸露;其中,所述像素电极的材质为掺氢的氧化物半导体; 刻蚀阻挡层,形成在所述有源层上; 源/漏电极层,形成在所述刻蚀阻挡层上,包括源电极和漏电极,所述源电极和所述漏电极分别通过所述刻蚀阻挡层上的过孔与所述有源层电连接,所述漏电极与所述像素电极电连接;所述源/漏电极层包括:源/漏金属电极层和保护层,所述源/漏金属电极层形成在所述刻蚀阻挡层上,所述保护层形成在所述源/漏金属电极层上,所述保护层的材质为氧化铟锡; 钝化层,形成在所述源/漏电极层上; 还包括与由 An oxide thin film transistor TFT array substrate, wherein, comprising: a TFT device; the TFT device comprising: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate upper electrode and the substrate; an active layer formed on the gate insulating layer, the oxide semiconductor material in the same layer as the pixel electrode, the pixel electrode is exposed; wherein the pixel electrode is made of doped hydrogen an oxide semiconductor; etch stop layer, is formed on the active layer; source / drain electrode layer is formed on the etch stop layer including a source electrode and a drain electrode, said source electrode and the drain through the via hole electrode, respectively, on said etch stop layer electrically connected to said active layer, a drain electrode connected to the pixel electrode; the source / drain electrode layer comprising: a source / drain electrode layer and the metal the protective layer, the source / drain metal electrode layer is formed on the etch stop layer, the protective layer is formed on the source / drain metal electrode layer, a material of the protective layer is indium tin oxide; passivating layer, is formed on the source / drain electrode layer; and further comprising a 多个像素单元组成的像素区域连接的绑定区域,所述绑定区域中的电极层包括: 金属电极层和保护层,所述金属电极层形成在所述刻蚀阻挡层上,所述保护层形成在所述金属电极层上,所述保护层的材质为氧化铟锡。 Binding region of the pixel connected regions composed of a plurality of pixel units, the binding region of the electrode layer comprises: a metal electrode layer and the protective layer, the metal electrode layer is formed on the etch stop layer, said protective layer is formed on the metal electrode layer, a material of the protective layer is indium tin oxide.
2. 根据权利要求1所述的氧化物薄膜晶体管TFT阵列基板,其特征在于,所述有源层中与所述源/漏电极电连接部分的材质为掺氢的氧化物半导体。 The oxide thin film transistor TFT array substrate according to claim 1, wherein a material of the active layer to the connecting portion of the source / drain electrode of an oxide semiconductor is doped with hydrogen.
3. 根据权利要求1所述的氧化物薄膜晶体管TFT阵列基板,其特征在于,所述绑定区域包括: 所述衬底; 栅极,形成在所述衬底上; 所述栅绝缘层,形成在所述栅极和所述衬底上; 所述刻蚀阻挡层,形成在所述栅绝缘层上; 电极层,形成在所述刻蚀阻挡层上,并且通过所述刻蚀阻挡层和所述栅绝缘层上的过孔与所述栅极电连接作为绑定电极; 所述钝化层,形成在所述电极层上,并暴露出所述绑定电极。 The oxide thin film transistor TFT array substrate according to claim 1, wherein the binding region comprises: a substrate; a gate electrode formed on said substrate; said gate insulating layer, is formed on the gate electrode and the substrate; said etch stop layer, is formed on the gate insulating layer; electrode layer formed on said etch stop layer, said etch stop layer and by and the gate vias electrically insulating layer on the gate electrode connected to a binding; the passivation layer, is formed on the electrode layer, and exposing the electrode binding.
4. 一种氧化物薄膜晶体管TFT阵列基板的制作方法,其特征在于,包括: 在衬底上形成栅极; 在所述衬底和所述栅极上形成栅绝缘层,以覆盖所述栅极和所述衬底; 在所述栅绝缘层上通过氧化物半导体材质形成有源层和像素电极,将所述像素电极的氧化物半导体处理为掺氢的氧化物半导体; 在所述有源层上形成刻蚀阻挡层,图形化所述刻蚀阻挡层暴露出所述像素电极并得到所述刻蚀阻挡层上的过孔; 在所述刻蚀阻挡层上形成源/漏电极层,图形化所述源/漏电极层得到TFT器件的源/漏电极,并暴露出所述像素电极,所述源/漏电极分别通过所述刻蚀阻挡层上的过孔与所述有源层电连接,所述漏电极还与所述像素电极电连接;若所述源/漏电极层包括:源/漏金属电极层和保护层;则,图形化所述源/漏电极层得到源/漏电极,具体包括:在所述刻蚀阻挡层上形成 Manufacturing method of the TFT array substrate 4. An oxide thin film transistor, characterized by comprising: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate and the gate to cover the gate electrode and the substrate; a gate insulating layer on the active layer and the pixel electrode is formed by an oxide semiconductor material, the oxide semiconductor of the pixel electrode hydrogen doping process is an oxide semiconductor; in the active layer is formed on the etch stop layer, patterning the etch stop layer to expose the pixel electrode and through hole obtained on said etch stop layer; forming a source / drain electrode layer on the etch stop layer, patterning the source / drain electrode layer of the obtained TFT device source / drain electrode, and exposing the pixel electrode, the source / drain electrode through the via hole, respectively, on said etch stop layer and the active layer electrically connected to said further drain electrode connected to the pixel electrode; if the source / drain electrode layer comprising: a source / drain metal electrode layer and the protective layer; then, patterning the source / drain electrode layer to obtain source / a drain electrode comprises: forming on said etch stop layer 所述源/漏金属电极层,在所述源/漏金属电极层上形成所述保护层,图形化所述源/ 漏金属电极层和所述保护层得到所述源电极和所述漏电极,所述保护层的材质为氧化铟锡; 在所述源/漏电极上形成钝化层,以覆盖所述源/漏电极,并图形化所述钝化层暴露出所述像素电极; 在与由多个像素单元组成的像素区域连接的绑定区域上,图形化所述电极层得到所述绑定区域中的电极层,所述绑定区域中的电极层包括:金属电极层和保护层;其中,图形化所述电极层,具体包括:在所述刻蚀阻挡层上形成所述金属电极层,在所述金属电极层上形成所述保护层,所述保护层的材质为氧化铟锡。 The source / drain metal electrode layer, the protective layer is formed on the source / drain metal electrode layer, patterning the source / drain metal electrode layer and the protective layer to obtain the source electrode and the drain electrode material of the protective layer is indium tin oxide; forming a passivation layer on the source / drain electrode to cover the source / drain electrode, and patterning the passivation layer to expose the pixel electrode; in binding region connected to the pixel region composed of a plurality of pixel units, and patterning the electrode layer to obtain an electrode layer of the binding region, the electrode layer comprises the binding region: the metal electrode layer and the protective layer; wherein patterning the electrode layer comprises: forming the metal electrode layer on the etch stop layer, forming a protective layer on the metal electrode layer, a material of the protective oxide layer indium tin.
5. 根据权利要求4所述的方法,其特征在于,通过掺氢工艺或缺氧工艺将所述有源层中与所述源/漏电极电连接的氧化物半导体部分处理为掺氢的氧化物半导体。 The method according to claim 4, characterized in that, by hydrogen doping process or anoxic process the portion of the oxide semiconductor active layer is connected to the source / drain electrode of the hydrogen doping process for the oxidation of semiconductor.
6. 根据权利要求4所述的方法,其特征在于,所述方法还包括: 在与由多个像素单元组成的像素区域连接的绑定区域上,在所述衬底和所述栅极上形成所述栅绝缘层后,在所述栅绝缘层上形成所述刻蚀阻挡层,图形化所述刻蚀阻挡层和所述栅绝缘层得到过孔; 在所述刻蚀阻挡层上形成电极层,所述电极层通过所述刻蚀阻挡层和所述栅绝缘层上的过孔与所述栅极电连接作为绑定电极; 在所述电极层上形成所述钝化层,以覆盖所述电极层和所述刻蚀阻挡层,并且图形化所述钝化层暴露出所述绑定电极。 6. The method as claimed in claim 4, wherein said method further comprises: in the binding region connected to the pixel region composed of a plurality of pixel units, on the substrate and the gate after forming the gate insulating layer, the etch stop layer is formed on the gate insulating layer, patterning the etch stop layer and the gate insulating layer is obtained through the aperture; is formed on the etch stop layer electrode layer, the electrode layer through the etch stop layer and the gate via the gate insulating layer electrically connected to the electrode as the binding; the passivation layer is formed on the electrode layer to covering the electrode layer and the etch stop layer, and patterning the passivation layer to expose the electrode binding.
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