CN108417579A - A kind of display base plate and its manufacturing method - Google Patents
A kind of display base plate and its manufacturing method Download PDFInfo
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- CN108417579A CN108417579A CN201810051792.3A CN201810051792A CN108417579A CN 108417579 A CN108417579 A CN 108417579A CN 201810051792 A CN201810051792 A CN 201810051792A CN 108417579 A CN108417579 A CN 108417579A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 132
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 239000002184 metal Substances 0.000 claims abstract description 77
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 238000009413 insulation Methods 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims description 74
- 230000004888 barrier function Effects 0.000 claims description 57
- 239000012780 transparent material Substances 0.000 claims description 20
- 230000005611 electricity Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 22
- 238000000137 annealing Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 28
- 229910052802 copper Inorganic materials 0.000 description 28
- 239000010949 copper Substances 0.000 description 28
- 239000012528 membrane Substances 0.000 description 23
- 238000010586 diagram Methods 0.000 description 20
- 239000004973 liquid crystal related substance Substances 0.000 description 19
- 239000007788 liquid Substances 0.000 description 11
- 229910044991 metal oxide Inorganic materials 0.000 description 11
- 150000004706 metal oxides Chemical group 0.000 description 11
- 238000001039 wet etching Methods 0.000 description 8
- 239000002253 acid Substances 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 150000002739 metals Chemical class 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 125000001153 fluoro group Chemical group F* 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- MVOSNYGTDFGKIB-UHFFFAOYSA-N [F].[Cu] Chemical compound [F].[Cu] MVOSNYGTDFGKIB-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
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- Liquid Crystal (AREA)
Abstract
The invention discloses a kind of display base plates, crisscross scan line and data line including substrate, on substrate, interlocked pixel region, the pixel electrode in pixel region, the source layer being connect with data line, semiconductor layer and the first insulating film layer limited by scan line and data line, semiconductor layer is electrically connected with source layer and pixel electrode, and source layer is electrically connected by source contact openings and semiconductor layer.First insulating film layer is equipped with the second pixel electrode contact hole, and pixel electrode is electrically connected by the second pixel electrode contact hole and semiconductor layer.Compared to traditional display base plate, invention removes drain electrode structures, it is directly electrically connected with semiconductor layer using pixel electrode, in manufacturing process, pixel electrode is formed in after organic insulation film layer, it is aoxidized in the exposed of annealing process metal layer to solve, leads to poor contact, the problems such as group's bright spot occur.
Description
Technical field
The present invention relates to a kind of technical field of liquid crystal display more particularly to a kind of display base plate display base plate and its manufacturers
Method.
Background technology
Currently, flat-panel monitor has already taken up the leading position of monitor market, and towards large scale, high-resolution
Direction develop, small with its using display base plate as the liquid crystal display device of driving unit, light-weight a, system such as quality height
It shows and is a little rapidly developed, and become mainstream information display terminal.
As shown in Figure 1, for TN (twisted nematic) display substrate structure schematic diagram in the prior art, including substrate 1,
It is sequentially formed at grid 2 on substrate, gate insulating layer 3, semiconductor layer 4, etching barrier layer 5, source layer 6, drain electrode layer 14,
One insulating film layer 7, organic insulation film layer 8, pixel electrode 9, source layer 6 and drain electrode layer 14 are formed simultaneously, and are formed through over etching, are
Saving mask plate, simplification of flowsheet is cost-effective, the pixel electricity formed in organic insulation film layer 8 and the first insulating film layer 7
Pole contact hole etches simultaneously, but this method can cause 14 upper layer metallic copper of drain electrode layer in annealing process because of exposed and by oxygen
Change, leads to pixel electrode 9 and 14 poor contact of source electrode and drain electrode layer so that data voltage can not be filled with pixel electrode 9, cause
Now the types such as group's bright spot is bad.
Invention content
The display base plate and its manufacturing method being directly electrically connected with semiconductor layer the present invention provides a kind of pixel electrode,
To solve to be aoxidized in the exposed of annealing process metal layer copper, there is the problems such as poor contact and group's bright spot.
A kind of display base plate, including crisscross scan line and data line, pixel electrode, the source electrode being connect with data line
Layer and semiconductor layer, semiconductor layer are electrically connected with the source layer and pixel electrode.
Preferably, display base plate further includes the first insulating film layer, and the setting of the first insulating film layer is in semiconductor layer and pixel electricity
Between pole, the second pixel electrode contact hole is provided on the first insulating film layer, pixel electrode passes through the second pixel electrode contact hole
It is electrically connected with semiconductor layer.
Preferably, semiconductor layer is metal oxide, and display base plate further includes：Etching barrier layer, etching barrier layer setting
Between semiconductor layer and source layer, etching barrier layer is equipped with source contact openings and the first pixel electrode contact hole, source layer
It is electrically connected by the source contact openings and semiconductor layer of etching barrier layer, the pixel electrode is contacted by the first pixel electrode
Hole and the second pixel electrode contact hole are electrically connected with semiconductor layer.
Preferably, display base plate further includes：Organic insulation film layer, organic insulation film layer setting the first insulating film layer it
On, organic insulation film layer includes third pixel electrode contact hole, and pixel electrode is arranged in organic insulation film layer, and pixel electrode is logical
It crosses the first pixel electrode contact hole, the second pixel electrode contact hole and third pixel electrode contact hole and semiconductor layer electrically connects
It connects.
Preferably, display base plate further includes：Second insulating film layer, public electrode, the setting of the second insulating film layer is in pixel electricity
On extremely, touch-control metal layer is located on the second insulating film layer.
Preferably, display base plate further includes：Second insulating film layer, public electrode, touch-control metal layer and third insulating film layer,
Second insulating film layer is arranged on the pixel electrode, and touch-control metal layer is located on the second insulating film layer, and third insulating film layer, which is located at, to be touched
It controls on metal layer, public electrode is located on third insulating film layer, and third insulating film layer includes common electrode contact hole, public
Electrode is electrically connected by common electrode contact hole and touch-control metal layer.
Preferably, metal oxide is indium gallium zinc oxide (IGZO).
Preferably, pixel electrode, public electrode are transparent metal oxide.
Preferably, grid, source layer, touch-control metal layer using single copper at or copper and other metals composition bilayer
Metal is constituted, and if upper layer metal is copper, lower metal is titanium.
Preferably, the first insulating film layer, the second insulating film layer and third insulating film layer are inorganic insulation layer.
The invention also discloses a kind of manufacturing methods of display base plate, include the following steps：
S1：Scan line and grid are formed on substrate by the first metal；
S2：Form the gate insulating layer being covered on the first metal；
S3：Semiconductor layer is formed on gate insulating layer；
S4：The source layer that the data line crisscross with scan line is formed by the second metal and is connect with data line, source
Pole layer is contacted with semiconductor layer；
S5：The first insulating film layer is formed, forms the second pixel electrode being located on semiconductor layer on the first insulating film layer
Contact hole；
S6：Deposited semiconductor transparent material, which is located on the first insulating film layer, forms pixel electrode, and semiconductor transparent material
It is contacted with semiconductor layer by the second pixel electrode contact hole.
Preferably, S3-S6 the specific steps are：
S31：Semiconductor layer is formed on gate insulating layer；
S32：Etching barrier layer is formed on the semiconductor layer, and source contact openings are formed on etching barrier layer；
S4：It is formed and the crisscross data line of scan line, and the source layer that is connect with data line, source by the second metal
Pole layer is contacted by source contact openings with semiconductor layer；
S5：The first insulating film layer is formed, forms the second pixel electrode being located on semiconductor layer on the first insulating film layer
Contact hole forms the first pixel electrode contact hole being located on semiconductor layer, the contact of the first pixel electrode on etching barrier layer
Hole and the second pixel electrode contact hole are a through-hole；
S6：Deposited semiconductor transparent material, which is located on the first insulating film layer, forms pixel electrode, and semiconductor transparent material
It is contacted with semiconductor layer by the first pixel electrode contact hole and the second pixel electrode contact hole.
Preferably, it needs to perform etching out figure after forming source layer in step S4, the lithographic method of use is wet etching, institute
It is floride-free copper acid to state wet etching etching liquid.
It is preferred that step S3-S6 the specific steps are：
S31：Semiconductor layer is formed on gate insulating layer；
S32：Etching barrier layer is formed on the semiconductor layer, and source contact openings and the first pixel are formed on etching barrier layer
Electrode contact hole；
S4：It is formed and the crisscross data line of scan line, and the source layer that is connect with data line, source by the second metal
Pole layer is contacted by source contact openings with semiconductor layer；
S5：The first insulating film layer is formed, forms the second pixel electrode being located on semiconductor layer on the first insulating film layer
Contact hole, the first pixel electrode contact hole and the second pixel electrode contact hole are a through-hole；
S6：Deposited semiconductor transparent material, which is located on the first insulating film layer, forms pixel electrode, and semiconductor transparent material
It is contacted with semiconductor layer by the first pixel electrode contact hole and the second pixel electrode contact hole.
Preferably, it needs to perform etching out figure after forming source layer in step S4, the lithographic method of use is wet etching, institute
It is fluorine-containing copper acid to state wet etching etching liquid.
Preferably, S5-S6 the specific steps are：
S51：The first insulating film layer is formed, forms the second pixel electrode being located on semiconductor layer on the first insulating film layer
Contact hole；
S52：Organic insulation film layer is formed, forms the third pixel electrode being located on semiconductor layer in organic insulation film layer
Contact hole, third pixel electrode contact hole and the second pixel electrode contact hole are a through-hole；
S6：Deposited semiconductor transparent material, which is located in organic insulation film layer, forms pixel electrode, and semiconductor transparent material
It is contacted with semiconductor layer by the second pixel electrode contact hole and third pixel electrode contact hole.
Preferably, step S6 further comprises：
S7：Form the second insulating film layer；
S8：The touch-control metal layer formed on the second insulating film layer by third metal；
S9：Third insulating film layer is formed, the public electrode being located on touch-control metal layer is formed on third insulating film layer and connects
Contact hole；
S10：Public electrode is formed on third insulating film layer, public electrode passes through common electrode contact hole and touch-control metal
Layer contact.
Compared with prior art, the present invention can at least be brought with the next item down technique effect：
The design for eliminating source-drain electrode in the prior art only forms source electrode in source-drain electrode layer, does not form drain electrode, allows pixel
Electrode is directly connect with semiconductor layer, and in manufacturing process, pixel electrode is formed in after organic insulation film layer, is carrying out lehr attendant
When skill, only has semiconductor layer in pixel electrode contact hole, without metal, therefore be not in the drain electrode in pixel electrode contact hole
Metallic copper causes data voltage that can not be filled with pixel electrode, group's bright spot is like bad by the dioxygen oxidation phenomenon in air.
When carrying out the Patternized technique of source layer, mask plate used is more simple, facilitates processing, reduces production
Cost improves economic benefit.
Description of the drawings
Fig. 1 is prior art display substrate structure schematic diagram；
Fig. 2 is TN of the present invention (twisted nematic) pattern display substrate structure schematic diagram；
Fig. 3 is TN (twisted nematic) pattern display substrate structure schematic diagram of narrow frame of the present invention；
Fig. 4 is FFS of the present invention (in-plane switching) pattern display substrate structure schematic diagram；
Fig. 5 is that touch panel function (is embedded into liquid crystal pixel) control mode touch mode display base plate by present invention reality in-cell
Structural schematic diagram；
Fig. 6 is Fig. 5 structure A-A cross section views；
Fig. 7-13 is TN of the present invention (twisted nematic) pattern display base plate the first manufacturing method schematic diagrames；
Figure 14-16 is TN of the present invention (twisted nematic) pattern display base plate the second manufacturing method schematic diagrames；
Figure 17-18 is TN (twisted nematic) pattern display substrate manufacturing method schematic diagram of narrow frame of the present invention；Figure 19
For FFS of the present invention (in-plane switching) pattern display substrate manufacturing method schematic diagram；
Touch panel function (is embedded into liquid crystal pixel) control mode touch mode for present invention reality in-cell and shown by Figure 20-23
Manufacture of substrates schematic diagram.
Reference numerals list：1- substrates, 2- grids, 3- gate insulating layers, 4- semiconductor layers, 5- etching barrier layers, the sources 6-
Pole layer, the first insulating film layers of 7-, 8- organic insulation film layers, 9- pixel electrodes, the second insulating film layers of 10-, 11- touch-control metal layers,
12- third insulating film layers, 13- public electrodes, 14- drain electrode layers.
Specific implementation mode
In the following with reference to the drawings and specific embodiments, the present invention is furture elucidated, it should be understood that these embodiments are merely to illustrate
It the present invention rather than limits the scope of the invention, after having read the present invention, those skilled in the art are to of the invention each
The modification of kind equivalent form falls within the application range as defined in the appended claims.
To make simplified form, part related to the present invention is only schematically shown in each figure, they are not represented
Its practical structures as product.In addition, so that simplified form is easy to understand, there is identical structure or function in some figures
Component only symbolically depicts one of those, or has only marked one of those.Herein, "one" is not only indicated
" only this ", can also indicate the situation of " more than one ".
The present invention provides a kind of display base plates, including crisscross scan line and data line, pixel electrode and data
The source layer and semiconductor layer of line connection, semiconductor layer are electrically connected with the source layer and pixel electrode.
Preferably, display base plate further includes the first insulating film layer, and the setting of the first insulating film layer is in semiconductor layer and pixel electricity
Between pole, the second pixel electrode contact hole is provided on the first insulating film layer, pixel electrode passes through the second pixel electrode contact hole
It is electrically connected with semiconductor layer.
Preferably, semiconductor layer is metal oxide, and display base plate further includes：Etching barrier layer, etching barrier layer setting
Between semiconductor layer and source layer, etching barrier layer is equipped with source contact openings and the first pixel electrode contact hole, source layer
It is electrically connected by the source contact openings and semiconductor layer of etching barrier layer, the pixel electrode is contacted by the first pixel electrode
Hole and the second pixel electrode contact hole are electrically connected with semiconductor layer.
Preferably, display base plate further includes：Organic insulation film layer, organic insulation film layer setting the first insulating film layer it
On, organic insulation film layer includes third pixel electrode contact hole, and pixel electrode is arranged in organic insulation film layer, and pixel electrode is logical
It crosses the first pixel electrode contact hole, the second pixel electrode contact hole and third pixel electrode contact hole and semiconductor layer electrically connects
It connects.
Preferably, display base plate further includes：Second insulating film layer, public electrode, the setting of the second insulating film layer is in pixel electricity
On extremely, touch-control metal layer is located on the second insulating film layer.
Preferably, display base plate further includes：Second insulating film layer, public electrode, touch-control metal layer and third insulating film layer,
Second insulating film layer is arranged on the pixel electrode, and touch-control metal layer is located on the second insulating film layer, and third insulating film layer, which is located at, to be touched
It controls on metal layer, public electrode is located on third insulating film layer, and third insulating film layer includes common electrode contact hole, public
Electrode is electrically connected by common electrode contact hole and touch-control metal layer.
Specifically, the first insulating film layer, the second insulating film layer, third insulating film layer are inorganic insulation layer.
Specifically, semiconductor layer is metal oxide.
Specifically, metal oxide is indium gallium zinc oxide (IGZO).
Specifically, pixel electrode, public electrode are transparent metal oxide.
Specifically, grid, source layer, touch-control metal layer using single copper at or copper and other metals composition bilayer
Metal is constituted, and if upper layer metal is copper, lower metal is titanium.
Embodiment one：
Fig. 2 show first embodiment of the present invention structural schematic diagram, as shown in Fig. 2, a kind of display base plate, including substrate
1, the crisscross scan line and data line on substrate 1, interlocked the pixel region limited, position by scan line and data line
In in pixel region pixel electrode 9, connect with data line source layer 6, semiconductor layer 4, the etching on semiconductor layer 4
Barrier layer 5 and the first insulating film layer 7, etching barrier layer 5 are equipped with source contact openings and the first pixel electrode contact hole, source
Pole layer 6 is electrically connected by source contact openings and semiconductor layer 4.First insulating film layer 7 is equipped with the second pixel electrode contact hole,
Second pixel electrode contact hole passes through the first pixel electrode contact hole, pixel electrode 9 to pass through the first pixel electrode contact hole and the
Two pixel electrode contact holes are electrically connected with semiconductor layer 4.
Scan line, data line and source layer 6 by single copper at or the double-level-metal structure that forms of copper and other metals
At if upper layer metal is copper, lower metal is titanium.
Wherein, the first pixel electrode contact hole and the second pixel electrode contact hole can be formed simultaneously, can not also be simultaneously
It is formed.When being formed simultaneously, the first pixel electrode contact hole and the hole that the second pixel electrode contact hole is a connection pass through quarter
Etching technique runs through etching barrier layer 5 and the first insulating film layer 7 simultaneously；When not being formed simultaneously, the first pixel electrode contact hole with
Source contact openings are formed simultaneously, the second pixel electrode contact hole when forming the first insulating film layer 7 or formed the first insulating film layer 7
It is formed later.
Wherein, the first insulating film layer 7 is inorganic insulation layer.
The present embodiment only forms source electrode in source-drain electrode layer 6, does not form drain electrode, allows pixel electrode 9 directly and semiconductor
Layer 4 connects, and in manufacturing process, pixel electrode 9 is formed in after the first insulating film layer 7, when carrying out annealing process, pixel electrode
Only have semiconductor layer 4 in contact hole, without drain metal layer, therefore is not in the drain metal copper in pixel electrode contact hole
By the dioxygen oxidation phenomenon in air, cause data voltage that can not be filled with pixel electrode 9, group's bright spot etc. is bad.
When carrying out the Patternized technique of source layer 6, mask plate used is more simple, facilitates processing, reduces life
Cost is produced, economic benefit is improved.
This first embodiment is TN (twisted nematic) pattern display base plate, and display base plate of the present invention is array substrate, is shown
Show that panel includes the display base plate as array substrate, color membrane substrates and the liquid between display base plate and color membrane substrates
Crystalline substance has pixel electrode 9 on display base plate, has public electrode on color membrane substrates, have between pixel electrode 9 and public electrode
Drive the electric field of liquid crystal.
When semiconductor layer 4 is metal oxide (when such as IGZO), according to the needs of design, may be used etching barrier layer 5,
Or do not use etching barrier layer 5；When semiconductor layer 4 is polysilicon or amorphous, it may not be necessary to etching barrier layer 5.
Embodiment two：
Fig. 3 show second embodiment of the present invention structural schematic diagram, as shown in figure 3, a kind of display base plate, including substrate
1, the crisscross scan line and data line on substrate 1, interlocked the pixel region limited, position by scan line and data line
In in pixel region pixel electrode 9, connect with data line source layer 6, semiconductor layer 4, the etching on semiconductor layer 4
Barrier layer 5 and the first insulating film layer 7, organic insulation film layer 8, etching barrier layer 5 are equipped with source contact openings and the first pixel
Electrode contact hole, source layer 6 are electrically connected by source contact openings and semiconductor layer 4, and the first insulating film layer 7 is equipped with the second picture
Plain electrode contact hole, organic insulation film layer 8 are equipped with third pixel electrode contact hole, and the second pixel electrode contact hole passes through first
Pixel electrode contact hole, third pixel electrode contact hole pass through the first pixel electrode contact hole and the second pixel electrode contact hole,
Pixel electrode 9 by the first pixel electrode contact hole, the second pixel electrode contact hole and third pixel electrode contact hole with partly lead
4 layers of electric connection of body.
Wherein, the first pixel electrode contact hole, the second pixel electrode contact hole and third pixel electrode contact hole can be same
When formed, can not also be formed simultaneously.When being formed simultaneously, the first pixel electrode contact hole, the second pixel electrode contact hole and
Third pixel electrode contact hole is the hole of a connection, by etching technics simultaneously through etching barrier layer 5, the first insulating film layer
7 and organic insulation film layer；When not being formed simultaneously, the first pixel electrode contact hole is formed simultaneously with source contact openings, the second picture
Plain electrode contact hole is formed when forming the first insulating film layer or after the first insulating film layer of formation, third pixel electrode contact hole
It is formed when forming organic insulation film layer or after formation organic insulation film layer.
Wherein, the first insulating film layer 7 is inorganic insulation layer.
Scan line, data line and source layer 6 by single copper at or the double-level-metal structure that forms of copper and other metals
At if upper layer metal is copper, lower metal is titanium.
On the basis of embodiment one, the present embodiment may be such that pixel electrode 9 by increasing organic insulation film layer 8
It is more flat, while the parasitic capacitance problems between pixel electrode 9 and wiring can be effectively reduced.
This second embodiment is TN (twisted nematic) pattern display base plate of narrow frame, and display base plate of the present invention is array
Substrate, display panel include the display base plate as array substrate, color membrane substrates and positioned at display base plate and color membrane substrates it
Between liquid crystal, there is on display base plate pixel electrode 9, there is public electrode on color membrane substrates, pixel electrode 9 and public electrode it
Between have driving liquid crystal electric field, realize narrow frame show.
When semiconductor layer 4 is metal oxide (when such as IGZO), according to the needs of design, may be used etching barrier layer 5,
Or do not use etching barrier layer 5；When semiconductor layer 4 is polysilicon or amorphous, it may not be necessary to etching barrier layer 5.
Embodiment three：
Fig. 4 show third embodiment of the present invention structural schematic diagram, as shown in figure 4, a kind of display base plate, including substrate
1, the crisscross scan line and data line on substrate 1, interlocked the pixel region limited, position by scan line and data line
In in pixel region pixel electrode 9, connect with data line source layer 6, semiconductor layer 4, the etching on semiconductor layer 4
Barrier layer 5 and the first insulating film layer 7, organic insulation film layer 8, the second insulating film layer 10, public electrode 13, etching barrier layer 5
Be equipped with source contact openings and the first pixel electrode contact hole, source layer 6 by the source contact openings of etching barrier layer 5 with partly lead
Body layer 4 is electrically connected, and the first insulating film layer 7 is equipped with the second pixel electrode contact hole, and organic insulation film layer 8 is equipped with third picture
Plain electrode contact hole, the second pixel electrode contact hole pass through the first pixel electrode contact hole, third pixel electrode contact hole to pass through
First pixel electrode contact hole and the second pixel electrode contact hole, pixel electrode 9 is by passing through the first pixel electrode contact hole,
Two pixel electrode contact holes and third pixel electrode contact hole are electrically connected with semiconductor layer 4.
Wherein, the first pixel electrode contact hole, the second pixel electrode contact hole and third pixel electrode contact hole can be same
When formed, can not also be formed simultaneously.When being formed simultaneously, the first pixel electrode contact hole, the second pixel electrode contact hole and
Third pixel electrode contact hole is the hole of a connection, by etching technics simultaneously through etching barrier layer 5, the first insulating film layer
7 and organic insulation film layer；When not being formed simultaneously, the first pixel electrode contact hole is formed simultaneously with source contact openings, the second picture
Plain electrode contact hole is formed when forming the first insulating film layer or after the first insulating film layer of formation, third pixel electrode contact hole
It is formed when forming organic insulation film layer or after formation organic insulation film layer.
Wherein, the first insulating film layer 7 and the second insulating film layer 10 are inorganic insulation layer.
Scan line, data line and source layer 6 by single copper at or the double-level-metal structure that forms of copper and other metals
At if upper layer metal is copper, lower metal is titanium.
On the basis of embodiment two, public electrode 13 is accomplished 9 top of pixel electrode by the present embodiment, and passes through second
Insulating film layer 10 is completely cut off, and display view angle can be improved.
This third embodiment is FFS (in-plane switching) pattern display base plate, and display base plate of the present invention is array substrate, is shown
Show that panel includes the display base plate as array substrate, color membrane substrates and the liquid between display base plate and color membrane substrates
Crystalline substance has pixel electrode 9 and public electrode 13 on display base plate, forms fringe field, drives the liquid crystal of top.
When semiconductor layer 4 is metal oxide (when such as IGZO), according to the needs of design, may be used etching barrier layer 5,
Or do not use etching barrier layer 5；When semiconductor layer 4 is polysilicon or amorphous, it may not be necessary to etching barrier layer 5.
Example IV：
Fig. 5 and Fig. 6 show fourth embodiment of the present invention structural schematic diagram, as shown in figure 5, a kind of display base plate, packet
It includes：Substrate 1 sequentially forms grid 2, gate insulating layer 3, semiconductor layer 4, etching barrier layer 5, source layer on the substrate
6, the first insulating film layer 7, organic insulation film layer 8, pixel electrode 9, the second insulating film layer 10, touch-control metal layer 11, third insulation
Film layer 12, public electrode 13, etching barrier layer 5 is equipped with source contact openings and the first pixel electrode contact hole, source layer 6 pass through
The source contact openings of etching barrier layer 5 are electrically connected with semiconductor layer 4, and the first insulating film layer 7 connects equipped with the second pixel electrode
Contact hole, organic insulation film layer 8 are equipped with third pixel electrode contact hole, and the second pixel electrode contact hole passes through the first pixel electrode
Contact hole, third pixel electrode contact hole pass through the first pixel electrode contact hole and the second pixel electrode contact hole, pixel electrode 9
It is electrical by the first pixel electrode contact hole, the second pixel electrode contact hole and third pixel electrode contact hole and semiconductor layer 4
Connection, third insulating film layer 12 are equipped with common electrode contact hole, and public electrode 13 passes through common electrode contact hole and touch-control gold
Belong to layer 11 to be electrically connected.
Wherein, the first pixel electrode contact hole, the second pixel electrode contact hole and third pixel electrode contact hole can be same
When formed, can not also be formed simultaneously.When being formed simultaneously, the first pixel electrode contact hole, the second pixel electrode contact hole and
Third pixel electrode contact hole is the hole of a connection, by etching technics simultaneously through etching barrier layer 5, the first insulating film layer
7 and organic insulation film layer；When not being formed simultaneously, the first pixel electrode contact hole is formed simultaneously with source contact openings, the second picture
Plain electrode contact hole is formed when forming the first insulating film layer or after the first insulating film layer of formation, third pixel electrode contact hole
It is formed when forming organic insulation film layer or after formation organic insulation film layer.
Wherein, the first insulating film layer 7, the second insulating film layer 10 and third insulating film layer 12 are inorganic insulation layer.
Scan line, data line and source layer 6 by single copper at or the double-level-metal structure that forms of copper and other metals
At if upper layer metal is copper, lower metal is titanium.
This fourth embodiment is the display base plate that touch panel function (is embedded into liquid crystal pixel) touch-control by in-cell,
Display base plate of the present invention is array substrate, and display panel includes the display base plate as array substrate, color membrane substrates and is located at
Liquid crystal between display base plate and color membrane substrates has pixel electrode and public electrode on display base plate, forms fringe field, drives
The liquid crystal of dynamic top, while among touch-control metal layer 11 is integrated into display base plate, completing touch function.
When semiconductor layer 4 is metal oxide (when such as IGZO), according to the needs of design, may be used etching barrier layer 5,
Or do not use etching barrier layer 5；When semiconductor layer 4 is polysilicon or amorphous, it may not be necessary to etching barrier layer 5.
On the basis of embodiment three, embodiment adds touch-control metal layers 11, by public electrode 13 and touch-control metal
Layer 11 is electrically connected, so as to realize the touch function of display panel.
It is the first manufacturing method schematic diagram of one display base plate of the embodiment of the present invention as illustrated in figures 7 to 13, this method includes
Following steps：
It is illustrated in figure 7 step S1：Scan line and grid 2 are formed by the first metal on substrate 1；
It is illustrated in figure 8 step S2：Form the gate insulating layer 3 being covered on the first metal；
It is illustrated in figure 9 step S3：Semiconductor layer 4 is formed on gate insulating layer 3；
It is step S32 as shown in Figure 10：Etching barrier layer 5 is formed on semiconductor layer 4, is formed on etching barrier layer 5
Source contact openings and the first pixel electrode contact hole；
It is step S4 as shown in figure 11：It is formed and the crisscross data line of scan line and and data line by the second metal
The source layer 6 of connection, source layer 6 are contacted by source contact openings with semiconductor layer 4；
It is step S5 as shown in figure 12：The first insulating film layer 7 is formed, is formed on the first insulating film layer 7 and is located at semiconductor
The second pixel electrode contact hole on layer 4, the second pixel electrode contact hole pass through the first pixel electrode contact hole；
It is step S6 as shown in figure 13：Deposited semiconductor transparent material, which is located on the first insulating film layer 7, forms pixel electrode
9, and semiconductor transparent material is contacted by the second pixel electrode contact hole and the first pixel electrode contact hole with semiconductor layer.
Preferably, it needs to perform etching out figure after forming source layer in step S4, the lithographic method of use is wet etching, institute
It is fluorine-containing copper acid to state wet etching etching liquid.It, can be when being performed etching to source layer 6 using floride-free copper acid, it will not be because of quarter
Erosion liquid causes semiconductor layer 4 to be contacted with etching liquid and generates chemical reaction by pixel electrode contact hole, leads to semiconductor layer 4
Performance decline.
The present embodiment manufacture is TN (twisted nematic) pattern display base plate, and display base plate of the present invention is array substrate,
Display panel includes the display base plate as array substrate, color membrane substrates and the liquid between display base plate and color membrane substrates
Crystalline substance has pixel electrode 9 on display base plate, has public electrode on color membrane substrates, have between pixel electrode 9 and public electrode
Drive the electric field of liquid crystal.
It is the second manufacturing method schematic diagram of one display base plate of the embodiment of the present invention, this method phase as illustrated in figures 14-16
Than in above-mentioned manufacturing method, step S32-S5 is followed successively by：
It is step S32 as shown in figure 14：Etching barrier layer 5 is formed on semiconductor layer 4, is formed on etching barrier layer 5
Source contact openings；
It is step S4 as shown in figure 15：It is formed and the crisscross data line of scan line and and data line by the second metal
The source layer 6 of connection, source layer 6 are contacted by source contact openings with semiconductor layer 4；
It is step S5 as shown in figure 16：The first insulating film layer 7 is formed, is formed on the first insulating film layer 7 and is located at semiconductor
The second pixel electrode contact hole on layer 4, the first pixel electrode formed on semiconductor layer 4 on etching barrier layer 5 connect
Contact hole, the first pixel electrode contact hole and the second pixel electrode contact hole are a through-hole；
Preferably, it needs to perform etching out figure after forming source layer in step S4, the lithographic method of use is wet etching, institute
It is fluorine-containing copper acid to state wet etching etching liquid.By changing the etching sequence of the first pixel electrode contact hole of etching barrier layer 5, quarter is allowed
The first pixel electrode contact hole on barrier layer 5 is lost after the etching of source layer 6, can prevent the etching solution and half of source layer 6
Conductor layer 4 contacts, and is chemically reacted with semiconductor layer 4, and the performance of caused semiconductor layer declines, therefore may be used and contain
Fluorine copper acid, compared to, using floride-free copper acid, cost is lower, and economic benefit is more preferable in said program.
The present embodiment manufacture is TN (twisted nematic) pattern display base plate, and display base plate of the present invention is array substrate,
Display panel includes the display base plate as array substrate, color membrane substrates and the liquid between display base plate and color membrane substrates
Crystalline substance has pixel electrode 9 on display base plate, has public electrode on color membrane substrates, have between pixel electrode 9 and public electrode
Drive the electric field of liquid crystal.
It is the first manufacturing method schematic diagram of two display base plate of the embodiment of the present invention, this method phase as shown in figs. 17-18
Than in above-mentioned manufacturing method, step S5-S6 is followed successively by：
It is step S51 as shown in figure 17：The first insulating film layer 7 is formed, is formed on the first insulating film layer 7 and is located at semiconductor
The second pixel electrode contact hole on layer 4；
S52：Organic insulation film layer 8 is formed, forms the third pixel being located on semiconductor layer 4 in organic insulation film layer 8
Electrode contact hole, third pixel electrode contact hole, the second pixel electrode contact hole and the first pixel electrode contact hole are a through-hole；
It is step S7 as shown in figure 18：Deposited semiconductor transparent material, which is located in organic insulation film layer 8, forms pixel electrode
9, and semiconductor transparent material is contacted by the first pixel electrode contact hole, the second pixel electrode contact hole and third pixel electrode
Hole is contacted with semiconductor layer.
The pixel electrode 9 for the display base plate made with this solution is more flat, while can effectively reduce
Parasitic capacitance problems between pixel electrode 9 and wiring.
What the present embodiment manufactured is TN (twisted nematic) pattern display base plate of narrow frame, and display base plate of the present invention is battle array
Row substrate, display panel include the display base plate as array substrate, color membrane substrates and be located at display base plate and color membrane substrates
Between liquid crystal, there is on display base plate pixel electrode 9, there is public electrode, pixel electrode 9 and public electrode on color membrane substrates
Between have driving liquid crystal electric field, realize narrow frame show.
Method schematic diagram is made for three display base plate of the embodiment of the present invention as shown in figure 19, this method is compared to above-mentioned system
Method is made, is further comprised the steps after step S6：
It is step S7 as shown in figure 19：The second insulating film layer 10 and public electrode 13 are formed on pixel electrode 9.
The present embodiment manufacture is FFS (in-plane switching) pattern display base plate, and display base plate of the present invention is array substrate,
Display panel includes the display base plate as array substrate, color membrane substrates and the liquid between display base plate and color membrane substrates
Crystalline substance has pixel electrode and public electrode on display base plate, forms fringe field, drives the liquid crystal of top.Pass through the technical side
The display base plate that case is produced has better visual angle.
Method schematic diagram is made for four display base plate of the embodiment of the present invention as depicted in figs. 20-23, this method is compared to upper
Manufacturing method is stated, step S6 further comprises：
It is step S7 as shown in figure 20：The second insulating film layer 10 is formed on pixel electrode 9；
It is step S8 as shown in figure 21：The touch-control metal layer 11 formed on the second insulating film layer 10 by third metal；
It is step S9 as shown in figure 22：Third insulating film layer 12 is formed, is formed on third insulating film layer 12 and is located at touch-control
Common electrode contact hole on metal layer 11；
It is step S10 as shown in figure 23：Public electrode 13 is formed on third insulating film layer 12, public electrode 13 passes through public affairs
Common electrode contact hole is contacted with touch-control metal layer 11.
What the present embodiment manufactured is the display base that touch panel function (is embedded into liquid crystal pixel) touch-control by in-cell
Plate, display base plate of the present invention are array substrate, and display panel includes the display base plate, color membrane substrates and position as array substrate
Liquid crystal between display base plate and color membrane substrates has pixel electrode and public electrode on display base plate, forms fringe field,
The liquid crystal of top is driven, while among touch-control metal layer 11 is integrated into display base plate, completes touch function.
During the preferred embodiment of the present invention has been described above in detail, but present invention is not limited to the embodiments described above
Detail can carry out technical scheme of the present invention a variety of equivalents (in full within the scope of the technical concept of the present invention
Amount, shape, position etc.), these equivalents all belong to the scope of protection of the present invention.
Claims (10)
1. a kind of display base plate, including crisscross scan line and data line, pixel electrode, the source layer being connect with data line
And semiconductor layer, it is characterised in that：The semiconductor layer is electrically connected with the source layer and pixel electrode.
2. display base plate according to claim 1, it is characterised in that：The display base plate further includes the first insulating film layer,
First insulating film layer is arranged between semiconductor layer and pixel electrode, and the second pixel is provided on first insulating film layer
Electrode contact hole, the pixel electrode are electrically connected by the second pixel electrode contact hole and semiconductor layer.
3. display base plate according to claim 2, it is characterised in that：The display base plate further includes：Etching barrier layer, institute
It states etching barrier layer to be arranged between semiconductor layer and source layer, the etching barrier layer is equipped with source contact openings and the first picture
Plain electrode contact hole, the source layer are electrically connected by the source contact openings of etching barrier layer with semiconductor layer, the pixel
Electrode is electrically connected by the first pixel electrode contact hole and the second pixel electrode contact hole with semiconductor layer.
4. display base plate according to claim 2 or 3, it is characterised in that：The display base plate further includes：Organic insulating film
Layer, the organic insulation film layer are arranged in the first insulating film layer and pixel electrode, and the organic insulation film layer includes third pixel
Electrode contact hole, the pixel electrode pass through the second pixel electrode contact hole and third pixel electrode contact hole and semiconductor layer electricity
Property connection.
5. display base plate according to claim 4, it is characterised in that：The display base plate further includes：Second insulating film layer,
Public electrode, touch-control metal layer and third insulating film layer, second insulating film layer are arranged on the pixel electrode, the common electrical
Pole is arranged on the second insulating film layer, and on the pixel electrode, the touch-control metal layer is located at for the second insulating film layer setting
On second insulating film layer, the third insulating film layer is located on touch-control metal layer, and the public electrode is located at third insulating film
On layer, the third insulating film layer includes common electrode contact hole, and the public electrode is by common electrode contact hole and touches
Metal layer is controlled to be electrically connected.
6. a kind of manufacturing method of display base plate, which is characterized in that include the following steps：
S1：Scan line and grid are formed on substrate by the first metal；
S2：Form the gate insulating layer being covered on the first metal；
S3：Semiconductor layer is formed on gate insulating layer；
S4：The source layer that the data line crisscross with scan line is formed by the second metal and is connect with data line, source layer
It is contacted with semiconductor layer；
S5：The first insulating film layer is formed, forms the second pixel electrode contact being located on semiconductor layer on the first insulating film layer
Hole；
S6：Deposited semiconductor transparent material, which is located on the first insulating film layer, forms pixel electrode, and semiconductor transparent material passes through
Second pixel electrode contact hole is contacted with semiconductor layer.
7. display substrate manufacturing method as claimed in claim 6, it is characterised in that：The step S3-S6 the specific steps are：
S31：Semiconductor layer is formed on gate insulating layer；
S32：Etching barrier layer is formed on the semiconductor layer, and source contact openings are formed on etching barrier layer；
S4：It is formed and the crisscross data line of scan line, and the source layer that is connect with data line, source layer by the second metal
It is contacted with semiconductor layer by source contact openings；
S5：The first insulating film layer is formed, forms the second pixel electrode contact being located on semiconductor layer on the first insulating film layer
Hole, on etching barrier layer formed be located at semiconductor layer on the first pixel electrode contact hole, the first pixel electrode contact hole and
Second pixel electrode contact hole is a through-hole；
S6：Deposited semiconductor transparent material, which is located on the first insulating film layer, forms pixel electrode, and semiconductor transparent material passes through
First pixel electrode contact hole and the second pixel electrode contact hole are contacted with semiconductor layer.
8. display substrate manufacturing method as claimed in claim 6, it is characterised in that：The step S3-S6 the specific steps are：
S31：Semiconductor layer is formed on gate insulating layer；
S32：Etching barrier layer is formed on the semiconductor layer, and source contact openings and the first pixel electrode are formed on etching barrier layer
Contact hole；
S4：It is formed and the crisscross data line of scan line, and the source layer that is connect with data line, source layer by the second metal
It is contacted with semiconductor layer by source contact openings；
S5：The first insulating film layer is formed, forms the second pixel electrode contact being located on semiconductor layer on the first insulating film layer
Hole, the first pixel electrode contact hole and the second pixel electrode contact hole are a through-hole；
S6：Deposited semiconductor transparent material, which is located on the first insulating film layer, forms pixel electrode, and semiconductor transparent material passes through
First pixel electrode contact hole and the second pixel electrode contact hole are contacted with semiconductor layer.
9. display substrate manufacturing method as claimed in claim 6, it is characterised in that：The step S5-S6 the specific steps are：
S51：The first insulating film layer is formed, forms the second pixel electrode contact being located on semiconductor layer on the first insulating film layer
Hole；
S52：Organic insulation film layer is formed, forms the third pixel electrode contact being located on semiconductor layer in organic insulation film layer
Hole, third pixel electrode contact hole and the second pixel electrode contact hole are a through-hole；
S6：Deposited semiconductor transparent material, which is located in organic insulation film layer, forms pixel electrode, and semiconductor transparent material passes through
Second pixel electrode contact hole and third pixel electrode contact hole are contacted with semiconductor layer.
10. display substrate manufacturing method as claimed in claim 9, it is characterised in that：The step S6 further comprises：
S7：Form the second insulating film layer；
S8：The touch-control metal layer formed on the second insulating film layer by third metal；
S9：Third insulating film layer is formed, forms the common electrode contact hole being located on touch-control metal layer on third insulating film layer；
S10：Public electrode is formed on third insulating film layer, public electrode is connect by common electrode contact hole and touch-control metal layer
It touches.
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