CN109116198B - Breakdown test structure, display panel and breakdown test method - Google Patents
Breakdown test structure, display panel and breakdown test method Download PDFInfo
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- CN109116198B CN109116198B CN201810995027.7A CN201810995027A CN109116198B CN 109116198 B CN109116198 B CN 109116198B CN 201810995027 A CN201810995027 A CN 201810995027A CN 109116198 B CN109116198 B CN 109116198B
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- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/1227—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials
- G01R31/1263—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation
- G01R31/129—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing of components, parts or materials of solid or fluid materials, e.g. insulation films, bulk material; of semiconductors or LV electronic components or parts; of cable, line or wire insulation of components or parts made of semiconducting materials; of LV components or parts
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Abstract
The invention provides a breakdown test structure, a display panel and a breakdown test method. The structure includes: a substrate; an active layer disposed on the substrate; the gate insulating layer is arranged on the active layer, the region of the gate insulating layer corresponding to the edge of the active layer is a climbing region, and the region positioned in the climbing region is a plane region; the gate layer, the gate layer sets up on the gate insulation layer, including first gate portion and the second gate portion that meets, first gate portion covers the plane area, second gate portion covers the climbing area, first gate portion and/or second gate portion are the fretwork pattern in order to expose the gate insulation layer. According to the embodiment of the invention, when the breakdown voltage of the gate insulating layer is tested, which one of the planar area and the climbing area is broken down and which one is broken down first can be determined according to the breakdown position, and the film condition of the gate insulating layer can be accurately known according to the breakdown phenomenon.
Description
Technical Field
The invention relates to the technical field of display, in particular to a breakdown testing structure, a display panel and a breakdown testing method.
Background
In recent years, with the development of OLED (Organic Light-Emitting Diode) products, the process of the OLED products becomes more and more complex, and the quality of the front layer process directly affects the subsequent process, even the whole process flow. With this trend, the process of measuring each layer becomes more and more important.
Fig. 1a and 1b show a structure for currently testing a GI (Gate Insulation) breakdown voltage, where fig. 1a is a plan view of a TFT (Thin Film Transistor), and fig. 1b is a cross-sectional view of fig. 1a at a dotted line, and a voltage is applied to the source/drain electrodes 11 and the Gate electrode 13 to obtain a breakdown voltage of the Gate Insulation layer 12. However, when the gate insulating layer 12 is broken down, it cannot be determined whether the planar region 121 is broken down or the ramp region 122 is broken down, and therefore the test result of the gate insulating layer film condition is inaccurate.
Disclosure of Invention
The invention provides a breakdown test structure, a display panel and a breakdown test method, and aims to solve the problem that the test result of the conventional test structure on the film condition is inaccurate.
In order to solve the above problems, the present invention discloses a breakdown testing structure, which includes:
substrate
An active layer disposed on the substrate;
the gate insulating layer is arranged on the active layer, the region of the gate insulating layer corresponding to the edge of the active layer is a climbing region, and the region positioned in the climbing region is a plane region;
the gate layer, the gate layer sets up on the gate insulation layer, including first gate portion and the second gate portion that meets, first gate portion covers the plane area, second gate portion covers the climbing area, first gate portion and/or second gate portion are the fretwork pattern in order to expose the gate insulation layer.
Optionally, the hollow pattern is a comb-shaped pattern.
Optionally, a first signal transmission line disposed on the same layer as the active layer and connected to the active layer;
a second signal transmission line disposed on the same layer as the gate layer and connected to the second gate portion;
the first signal transmission line and the second signal transmission line each have an end portion, and the end portions of the first signal transmission line and the second signal transmission line each expose an upper surface.
Optionally, the active layer and the first signal transmission line are both polysilicon layers doped with P-type impurities;
the concentration of the P-type impurity in the first signal transmission line is higher than that in the active layer covered by the gate layer.
Optionally, the gate insulating layer is a silicon oxide layer;
the gate layer is a metal layer.
The embodiment of the invention also provides a display panel, which comprises the breakdown testing structure.
The embodiment of the present invention further provides a breakdown testing method applied to the breakdown testing structure, where the breakdown testing structure includes a substrate, an active layer, a gate insulating layer and a gate layer, the gate insulating layer includes a ramp region and a planar region, the gate layer includes a first gate portion and a second gate portion, the first gate portion and/or the second gate portion are/is a hollow pattern, and the method includes:
applying a voltage across the active layer and the gate layer, wherein the voltage gradually increases;
determining a breakdown voltage when the gate insulating layer is broken down;
determining that the planar area is broken down according to the fact that the breakdown position is located in the first grid part; and determining that the climbing region is broken down according to the fact that the breakdown position is located in the second grid part.
Optionally, the hollow pattern is a comb-shaped pattern.
Optionally, the breakdown test structure further includes a first signal transmission line and a second signal transmission line, the first signal transmission line is connected to the active layer, the second signal transmission line is connected to the second gate, and both the first signal transmission line and the second signal transmission line have ends; the method further comprises the following steps:
a voltage is applied to an end of the first signal transmission line and an end of the second signal transmission line.
Compared with the prior art, the invention has the following advantages:
the breakdown test structure comprises a substrate, an active layer, a gate insulating layer and a gate electrode layer; the area of the gate insulating layer corresponding to the edge of the active layer is a climbing area, and the area inside the climbing area is a plane area; the grid layer comprises a first grid part and a second grid part, the first grid part covers the plane area, the second grid part covers the climbing area, and the first grid part and/or the second grid part are/is hollow patterns to expose the grid insulating layer. Because the first grid part and/or the second grid part are/is hollow patterns, the climbing area and the plane area of the grid insulating layer can be determined according to the first grid part and the second grid part, and then when the breakdown voltage of the grid insulating layer is tested, which of the plane area and the climbing area is broken down and which is broken down first can be determined according to the breakdown position, and the film condition of the grid insulating layer can be accurately known according to the breakdown phenomenon.
Drawings
FIG. 1a shows a plan view of a prior art breakdown test structure;
FIG. 1b shows a cross-sectional view of a prior art breakdown test structure;
FIG. 2a shows one of the plan views of a breakdown test structure according to the first embodiment of the present invention;
FIG. 2b is a cross-sectional view of a breakdown test structure according to a first embodiment of the present invention;
FIG. 3 is a second plan view of a breakdown test structure according to a first embodiment of the present invention;
fig. 4a shows a layered plan view of an active layer and a gate layer according to a first embodiment of the present invention;
fig. 4b shows a stacked plan view of an active layer and a gate layer according to a first embodiment of the present invention;
fig. 5 is a flowchart illustrating steps of a breakdown testing method according to a third embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example one
Referring to fig. 2a, a plan view of a breakdown testing structure according to an embodiment of the present invention and a cross-sectional view of the breakdown testing structure shown in fig. 2b, the structure includes:
a substrate 20;
an active layer 21, the active layer 21 being disposed on the substrate 20;
the gate insulating layer 22 is arranged on the active layer 21, a region of the gate insulating layer 22 corresponding to the edge of the active layer 21 is a climbing region 222, and a region located inside the climbing region is a planar region 221;
the gate layer 23 is disposed on the gate insulating layer 22, and referring to a plan view of the breakdown test structure shown in fig. 3, the breakdown test structure includes a first gate portion 231 and a second gate portion 232 which are connected to each other, the first gate portion 231 covers the planar region 221, the second gate portion 232 covers the climbing region 222, and the first gate portion 231 and/or the second gate portion 232 are/is a hollow pattern to expose the gate insulating layer 22.
In this embodiment, fig. 2a is a plan view of a breakdown test structure, fig. 2b is a cross-sectional view of the broken line in fig. 2a, and referring to fig. 2b, an active layer 21 is disposed on a substrate 20, a gate insulating layer 22 is disposed on the active layer 21, and a gate electrode layer 23 is disposed on the gate insulating layer 22. The region of the gate insulating layer 22 covering the edge of the active layer 21 is a climbing region 222, and covers the active layer 21, and the region inside the climbing region 222 is a planar region 221. Referring to fig. 3, the gate layer 23 includes a first gate portion 231 and a second gate portion 232 connected to each other, and both the first gate portion 231 and the second gate portion 232 may be hollow patterns; or the first grid part 231 is a non-hollow pattern, and the second grid part 232 is a hollow pattern; the first gate 231 may be a hollow pattern, and the second gate 232 may be a non-hollow pattern, wherein the hollow pattern exposes a portion of the gate insulating layer 22. The planar region 221 and the climbing region 222 of the gate insulating layer 22 may be determined from the first gate portion 231 and the second gate portion 232, and further, when the breakdown voltage of the gate insulating layer 22 is tested, whether the breakdown position is the planar region or the climbing region, and which of the planar region and the climbing region is broken first may be determined from the first gate portion 231 and the second gate portion 232.
Optionally, the hollow pattern is a comb-shaped pattern.
In this embodiment, the non-hollow pattern may be a rectangle, as shown in fig. 3, or a square or a circle, which is not limited in detail in this embodiment of the present invention and may be set according to actual situations. The hollow pattern can be a comb-shaped pattern which is composed of a plurality of strip-shaped structures arranged in parallel. In fig. 3, when the film thickness of the gate insulating layer 22 is uniform, the breakdown at the comb teeth is relatively uniform; when the film thickness of the gate insulating layer 22 is not uniform, part of the comb teeth is broken down and part of the comb teeth is not broken down. That is, the film condition of the gate insulating layer 22 can be determined according to the breakdown phenomenon at the comb teeth.
Alternatively, refer to a layered plan view of the active layer and the gate layer shown in fig. 4a, and a stacked plan view of the active layer and the gate layer shown in fig. 4 b;
a first signal transmission line 24 disposed on the same layer as the active layer 21 and connected to the active layer 21;
a second signal transmission line 25 disposed on the same layer as the gate layer 23 and connected to the second gate portion 232;
the first signal transmission line 24 and the second signal transmission line 25 each have an end, and the end 241 of the first signal transmission line 24 and the end 251 of the second signal transmission line 25 each have an exposed upper surface.
In this embodiment, the first signal transmission line 24 is disposed on the same layer as the active layer 21 and connected to the active layer 21; the second signal transmission line 25 is disposed at the same layer as the gate layer 23 and connected to the second gate portion 232. The end portion 241 of the first signal transmission line 24 and the end portion 251 of the second signal transmission line 25 are exposed at the upper surface, and a voltage may be applied to the end portion 241 of the first signal transmission line 24 and the end portion 251 of the second signal transmission line 25 when testing the breakdown voltage of the gate insulating layer 22.
Optionally, the active layer 21 and the first signal transmission line 24 are both polysilicon layers doped with P-type impurities;
the P-type impurity concentration in the first signal transmission line 24 is higher than the P-type impurity concentration in the active layer 21 covered by the orthographic projection of the gate layer 23.
In this embodiment, polysilicon may be deposited on the substrate 20 and doped with P-type impurities; the polysilicon is patterned through a patterning process to form the active layer 21 and the first signal transmission line 24. After the gate layer 23 is formed, the gate layer 23 covers a portion of the active layer 21, but does not cover the first signal transmission line 24, and the P-type impurity is doped again, so that the concentration of the P-type impurity in the first signal transmission line 24 is higher than that in the active layer 21 covered by the gate layer 23. The high concentration of P-type impurities can reduce the resistance of the first signal transmission line 24 and avoid the resistance of the first signal transmission line 24 from affecting the breakdown voltage. The P-type impurity may be a boron ion, which is not limited in detail in the embodiment of the present invention and may be selected according to actual situations.
Optionally, the gate insulating layer 22 is a silicon oxide layer;
the gate layer 23 is a metal layer.
In the present embodiment, the gate insulating layer 22 may be a silicon oxide layer, such as a silicon dioxide layer; the gate layer 23 may be a metal layer, such as a molybdenum metal layer; the substrate 20 may include a glass substrate and a buffer layer. The embodiment of the present invention is not limited in detail, and may be selected according to actual situations.
In summary, in the embodiments of the invention, the breakdown test structure includes a substrate, an active layer, a gate insulating layer and a gate layer, where an area of the gate insulating layer corresponding to an edge of the active layer is a climbing area, an area inside the climbing area is a planar area, the gate layer includes a first gate portion and a second gate portion, the first gate portion covers the planar area, the second gate portion covers the climbing area, and the first gate portion and/or the second gate portion are/is a hollow pattern to expose the gate insulating layer. Because the first grid part and/or the second grid part are/is hollow patterns, the climbing area and the plane area of the grid insulating layer can be determined according to the first grid part and the second grid part, and then when the breakdown voltage of the grid insulating layer is tested, which of the plane area and the climbing area is broken down and which is broken down first can be determined according to the breakdown position, and the film condition of the grid insulating layer can be accurately known according to the breakdown phenomenon.
Example two
The embodiment of the invention provides a display panel. The display panel comprises the breakdown testing structure according to the first embodiment. The breakdown test structure includes:
a substrate 20;
an active layer 21, the active layer 21 being disposed on the substrate 20;
the gate insulating layer 22 is arranged on the active layer 21, a region of the gate insulating layer 22 corresponding to the edge of the active layer 21 is a climbing region 222, and a region located inside the climbing region 222 is a planar region 221;
the gate layer 23 is disposed on the gate insulating layer 22 and includes a first gate portion 231 and a second gate portion 232 connected to each other, the first gate portion 231 covers the planar region 221, the second gate portion 232 covers the climbing region 222, and the first gate portion 231 and/or the second gate portion 232 are/is a hollow pattern to expose the gate insulating layer 22.
In this embodiment, the breakdown voltage of the gate insulating layer 22 is tested by using the breakdown testing structure, and since the first gate 231 and/or the second gate 232 are/is a hollow pattern, the planar region 221 and the climbing region 222 of the gate insulating layer 22 can be determined according to the first gate 231 and the second gate 232. Further, when testing the breakdown voltage of the gate insulating layer 22, it is possible to determine whether the breakdown position is a planar region or a climbing region, and which of the planar region and the climbing region is broken first, from the first gate portion 231 and the second gate portion 232. And the breakdown test structure is independently arranged in the display panel, so that the on-line measurement of the gate insulating layer can be realized, the timeliness is better, and other devices are not influenced.
In summary, in the embodiments of the invention, the display panel includes the breakdown test structure, so that the film condition of the gate insulating layer can be accurately obtained according to the breakdown phenomenon, and the on-line measurement can be realized, and the timeliness is good.
EXAMPLE III
Referring to fig. 5, a flowchart illustrating steps of a breakdown testing method according to an embodiment of the present invention is shown. The breakdown testing structure applied to the first embodiment includes a substrate 20, an active layer 21, a gate insulating layer 22, and a gate layer 23, where the gate insulating layer 22 includes a ramp region 222 and a planar region 221, the gate layer 23 includes a first gate portion 231 and a second gate portion 232, and the first gate portion 231 and/or the second gate portion 232 are/is a hollow pattern, and the method includes:
In this embodiment, the active layer 21 and the gate electrode layer 23 are disposed on both sides of the gate insulating layer 22 as two electrodes for testing the breakdown voltage of the gate insulating layer 22, and gradually increasing voltages are applied to the active layer 21 and the gate electrode layer 23, so that the withstand voltage of the gate insulating layer 22 can be tested.
Optionally, the breakdown testing structure further includes a first signal transmission line 24 and a second signal transmission line 25, the first signal transmission line 24 is connected to the active layer 21, the second signal transmission line 25 is connected to the second gate portion 232, the first signal transmission line 24 and the second signal transmission line 25 each have an end, and a voltage is applied to the end 241 of the first signal transmission line 24 and the end 251 of the second signal transmission line.
Specifically, the first signal transmission line 24 is connected to the active layer 21, the second signal transmission line 25 is connected to the second gate portion 232, and a voltage is applied to the active layer 21 and the gate layer 23 by applying a voltage to an end portion 251 of the first signal transmission line 24 and an end portion 251 of the second signal transmission line 25.
In this embodiment, the breakdown test structure may be observed with a microscope, and as the voltage gradually increases, a breakdown phenomenon will be observed, and the voltage at which the gate insulating layer 22 is broken down is determined as the breakdown voltage.
In this embodiment, since the first gate 231 and/or the second gate 232 are/is a hollow pattern, the planar region 221 and the climbing region 222 of the gate insulating layer 22 can be determined according to the first gate 231 and the second gate 232. When the breakdown position is at the first gate portion 231, it can be determined that the planar region 221 is broken down; when the breakdown position is at the second gate portion 232, it can be determined that the ramp region is broken down. It is also possible to determine which of the planar region and the ramp region is broken down first, according to the order in which the breakdown phenomenon occurs in the first gate 231 and the second gate 232.
Optionally, the hollow pattern is a comb-shaped pattern.
In this embodiment, the film condition of the gate insulating layer 22 may be determined according to the distribution of the breakdown positions in the hollow pattern. Specifically, when the film thickness of the gate insulating layer 22 is uniform, the breakdown at the comb teeth in the hollow pattern is relatively uniform; when the film thickness of the gate insulating layer 22 is not uniform, part of the hollow pattern is broken through at the comb teeth, and part of the comb teeth is not broken through, that is, the thickness uniformity of the gate insulating layer 22 can be determined according to the breakdown phenomenon at the comb teeth.
In summary, in the embodiments of the invention, the active layer and the gate layer are applied with gradually increasing voltages; determining a breakdown voltage when the gate insulating layer is broken down; determining that the planar area is broken down according to the position of the breakdown at the first grid part; and determining that the climbing region is broken down according to the fact that the breakdown position is located in the second grid part. By the embodiment of the invention, which one of the climbing area and the plane area of the gate insulating layer is broken down and which one is broken down first can be accurately obtained, and the breakdown voltages of the plane area and the climbing area and the film layer condition of the gate insulating layer can be accurately obtained.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The breakdown testing structure, the display panel and the breakdown testing method provided by the invention are described in detail, specific examples are applied in the description to explain the principle and the implementation mode of the invention, and the description of the examples is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A breakdown testing structure, comprising:
a substrate;
an active layer disposed on the substrate;
the gate insulating layer is arranged on the active layer, the region of the gate insulating layer corresponding to the edge of the active layer is a climbing region, and the region positioned in the climbing region is a plane region;
the gate layer is arranged on the gate insulating layer and comprises a first gate part and a second gate part which are connected, the first gate part covers the plane area, the second gate part covers the climbing area, and the first gate part and/or the second gate part are/is hollow patterns to expose the gate insulating layer;
the first signal transmission line is arranged on the same layer as the active layer and is connected with the active layer;
a second signal transmission line disposed on the same layer as the gate layer and connected to the second gate portion;
the first signal transmission line and the second signal transmission line each have an end portion, and the end portions of the first signal transmission line and the second signal transmission line each expose an upper surface.
2. The structure of claim 1, wherein the hollow pattern is a comb-like pattern.
3. The structure of claim 1, wherein the active layer and the first signal transmission line are each a polysilicon layer doped with P-type impurities;
the concentration of the P-type impurity in the first signal transmission line is higher than that in the active layer covered by the gate layer.
4. The structure of claim 1, wherein the gate insulating layer is a silicon oxide layer;
the gate layer is a metal layer.
5. A display panel comprising the breakdown test structure of any one of claims 1-4.
6. A breakdown testing method applied to the breakdown testing structure of any one of claims 1 to 5, wherein the breakdown testing structure comprises a substrate, an active layer, a gate insulating layer and a gate layer, the gate insulating layer comprises a ramp region and a planar region, the gate layer comprises a first gate portion and a second gate portion, and the first gate portion and/or the second gate portion are/is a hollow pattern, the method comprising:
applying a voltage across the active layer and the gate layer, wherein the voltage gradually increases;
determining a breakdown voltage when the gate insulating layer is broken down;
determining that the planar area is broken down according to the fact that the breakdown position is located in the first grid part; and determining that the climbing region is broken down according to the fact that the breakdown position is located in the second grid part.
7. The method of claim 6, wherein the cut-out pattern is a comb pattern.
8. The method of claim 6, wherein the breakdown test structure further comprises a first signal transmission line and a second signal transmission line, the first signal transmission line coupled to the active layer, the second signal transmission line coupled to the second gate portion, the first signal transmission line and the second signal transmission line each having an end; the method further comprises the following steps:
a voltage is applied to an end of the first signal transmission line and an end of the second signal transmission line.
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