CN104091804B - A kind of array base palte and preparation method thereof, display device - Google Patents
A kind of array base palte and preparation method thereof, display device Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract 2
- 238000012360 testing method Methods 0.000 claims abstract description 168
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000010409 thin film Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 95
- 238000004519 manufacturing process Methods 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims description 10
- 150000004706 metal oxides Chemical class 0.000 claims description 10
- 238000005984 hydrogenation reaction Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000000523 sample Substances 0.000 description 14
- 230000007547 defect Effects 0.000 description 11
- 239000004973 liquid crystal related substance Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- 230000005684 electric field Effects 0.000 description 6
- 238000002161 passivation Methods 0.000 description 5
- 101100489577 Solanum lycopersicum TFT10 gene Proteins 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910007541 Zn O Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display device, relates to Display Technique field, it is possible to directly test pixel electrode.This array base palte, including viewing area, this viewing area includes multiple pixel cell, and pixel cell includes again first area and second area, and first area includes that thin film transistor (TFT), second area include pixel electrode.Wherein, at least one in multiple first areas is test zone, and in the case, first area can also include the test layer being positioned at thin film transistor (TFT) drain surface.In the testing time, test layer electrically connects with pixel electrode；At non-testing time, test layer insulate with pixel electrode.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display device.
Background
A TFT-LCD (thin film transistor-liquid crystal display) is used as a flat panel display device, and is increasingly applied to the field of high performance display because of its characteristics of small size, low power consumption, no radiation, relatively low manufacturing cost, and the like.
The TFT-LCD is composed of an array substrate and a color film substrate. Liquid crystal is filled in the array substrate and the color film substrate, the control of the light intensity is realized by controlling the deflection of the liquid crystal, and then the color image display is realized by the filtering effect of the color film substrate. The Array substrate is manufactured by an Array (Array substrate manufacturing) process. In the actual production process, the array substrate may have Mura (speckle), dark spots, color difference and other adverse phenomena due to the influence of factors such as the manufacturing environment or the process level, thereby seriously affecting the display effect of the display device.
Therefore, when the above-described defective phenomenon occurs, the pixel electrode on the array substrate can be detected by the probe. However, when the pixel electrode is not located at the uppermost end of each hierarchical structure of the array substrate, the probe cannot directly test the pixel electrode. In the prior art, a test port located in a peripheral area of a display panel may be tested. However, the data obtained by the test port cannot directly and truly reflect the actual defect state of the array substrate, so that the test precision is reduced, and the quality and the display effect of the display device are adversely affected.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a manufacturing method thereof and a display device, which can be used for directly testing a pixel electrode.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in one aspect of the embodiments of the present invention, an array substrate is provided, including a display area, where the display area includes a plurality of pixel units, where each pixel unit includes a first area and a second area, where the first area includes a thin film transistor, and the second area includes a pixel electrode; at least one of the first regions is a test region, in this case, the first region further comprises a test layer on the surface of the drain electrode of the thin film transistor;
wherein, at a test time, the test layer is electrically connected with the pixel electrode;
the test layer is insulated from the pixel electrode at a non-test time.
In another aspect of the embodiments of the present invention, there is provided a display device including a method of forming a display region; the display area comprises a plurality of pixel units, each pixel unit comprises a first area and a second area, the first area comprises a thin film transistor, and the second area comprises a pixel electrode; wherein when at least one of the plurality of first regions is a test region, the method of forming the first region includes:
forming a test layer on the surface of the drain electrode of the thin film transistor;
electrically connecting the test layer with the pixel electrode at a test time;
insulating the test layer from the pixel electrode at a non-test time.
The embodiment of the invention provides an array substrate, a manufacturing method thereof and a display device. In this case, the first region may further include a test layer on a surface of the drain electrode of the thin film transistor. In the testing time, the testing layer is electrically connected with the pixel electrode so as to test the characteristics of the array substrate; at non-test time, the test layer is insulated from the pixel electrode. Therefore, the pixel electrodes on the array substrate can be directly tested through the test probes on the premise of not influencing the normal use of the array substrate, so that the test accuracy can be ensured, and the test precision, the quality of a display product and the display effect are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a TFT according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention;
fig. 6 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
An embodiment of the invention provides an array substrate, as shown in fig. 1, which includes a display area 200(active area, AA area for short, i.e., effective display area), where the display area 200 includes a plurality of pixel units 201 (defined by crossing gate lines 2001 and data lines 2002 that cross in a horizontal direction and a vertical direction), and the pixel units 201 include a first area 211 and a second area 212. The first region 211 includes the thin film transistor TFT10, and the second region 212 includes the pixel electrode 30. Wherein at least one of the plurality of first regions 211 is a test region 213 (shown in fig. 2), in which case the first region 211 further comprises a test layer 40 at the surface of the drain 101 of the TFT 10.
Wherein the test layer 40 is electrically connected to the pixel electrode 30 during the test time. In this way, the test probe can contact the test layer 40 through the via hole 50 on the surface of the passivation layer 20 and perform a test on the pixel electrode 30.
The test layer 40 is insulated from the pixel electrode 30 during non-test time
The test time is specifically required to detect characteristics of the TFT Array substrate during or after the Array process in order to timely detect various defects in the manufacture of the Array substrate and ensure the quality of the Array substrate. Specifically, the pixel electrodes on the array substrate may be tested using test probes. Therefore, the test time is the time for the test probe to perform the characteristic test on the array substrate. The defects of the TFT substrate, such as Mura (Mura) and dark spots, can be detected through the test, so that the quality of the display device and the display effect of the display device are improved. When the testing process is finished, the array substrate will enter the subsequent manufacturing process to finally form the display panel, and the testing layer 40 can be insulated from the pixel electrode 30 to ensure that the array substrate can be used normally, so that the time other than the testing time is a non-testing time in the manufacturing process.
It should be noted that the TFT may include a gate electrode 102, a gate insulating layer 103, a semiconductor active layer 104, and a doped semiconductor layer 105, which are sequentially located on a surface of a transparent substrate 01, and a source electrode 106 located on a surface of the doped semiconductor layer 105, as shown in fig. 3. Of course, the above description is only an illustration of the TFT structure, and other types of TFT structures are not described in detail here, but all should fall within the scope of the present invention.
The embodiment of the invention provides an array substrate, which comprises a display area, wherein the display area comprises a plurality of pixel units, each pixel unit comprises a first area and a second area, the first area comprises a thin film transistor, and the second area comprises a pixel electrode. In this case, the first region may further include a test layer on a surface of the drain electrode of the thin film transistor. In the testing time, the testing layer is electrically connected with the pixel electrode so as to test the characteristics of the array substrate; at non-test time, the test layer is insulated from the pixel electrode. Therefore, the pixel electrodes on the array substrate can be directly tested through the test probes on the premise of not influencing the normal use of the array substrate, so that the test accuracy can be ensured, and the test precision, the quality of a display product and the display effect are improved.
Note that, as shown in fig. 2, the pixel electrode 30 connected to the drain electrode 101 of the TFT may be located on a surface of the drain electrode 101 of the TFT10 on a side away from the passivation layer 20. Thus, the thin film layer at the connection between the pixel electrode 30 and the drain electrode 101 of the TFT10 has a small difference, and the thin film layer can be prevented from being easily broken due to a large difference in the thin film layer.
Example two
A plurality of the test regions 213 may be uniformly distributed on the array substrate. For example, 16 test regions 213 are uniformly distributed on the array substrate, each test region 213 corresponds to the first region 211 of one pixel unit 201, and the first region 211 includes the test layer 40 on the surface of the drain 101 of the TFT 10. The other first regions 101 where the test layer 40 is not disposed have no test function. In this way, the pixel electrodes 30 in the corresponding pixel units 201 can be tested through the 16 test areas, the test results can be compared and analyzed, and the defects on the array substrate can be confirmed according to the distinguishing features between the test results. Since the test regions 213 are uniformly distributed, the characteristics of the entire array substrate can be better grasped. In addition, through the test method, the position where the defect is easy to appear on the array substrate can be found after a plurality of tests, so that the processing conditions such as the production process, the environment and the like can be improved in a targeted manner.
EXAMPLE III
The test regions 213 may be distributed at four corners of the array substrate. It should be noted that, the four corners of the array substrate specifically refer to the four corners of a rectangle, assuming that the array substrate is a rectangle. Each corner of the array substrate is located in an area corresponding to at least one pixel unit 201. Thus, for some array substrates which are easy to have defects at corner positions, only the positions which are easy to have defects can be tested, and the whole array substrate does not need to be tested. Therefore, the testing time and procedures can be reduced, and the production efficiency can be improved.
Or,
the test region 213 may be located in a central region of the array substrate. The central area is only an area located at the central position of the entire array substrate, and the central area includes at least one pixel unit 201. In the display panel including the array substrate, the line of sight of the user often stays at the center of the display panel during the display process. Therefore, the display defect at the center position greatly reduces the display effect. It is possible to detect defects occurring at the above-mentioned positions by disposing the test region 213 in the central region of the array substrate.
Of course, the above description is only an example of the distribution of the plurality of test regions 213 on the array substrate, and other distribution manners are not described in detail here, but all shall fall within the scope of the present invention.
Further, the test layer 40 may be made of a metal oxide semiconductor material such as: IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), ITGO (In-Sn-Ga-O), Zn0N, ZnO and the like. The metal oxide semiconductor material can be a conductor after hydrogenation treatment and can be an insulator after oxidation treatment. Therefore, in the case where the test layer 40 is made of a metal oxide semiconductor material, when the array substrate is tested, the test layer 40 may be subjected to a hydrogenation process to make the test layer 40 have a conductive property, so that the test layer may be electrically connected to the pixel electrode 30 through the drain electrode 101 of the TFT to enable a test probe to directly test the pixel electrode 30. In the non-test time, the test layer 40 may be oxidized, so that the test layer 40 has an insulating property, thereby ensuring that the array substrate can be normally used in the non-test time.
Further, as shown in fig. 4, the common electrode 60 may be positioned on the surface of the passivation layer 20. The common electrode 60 is slit-shaped as shown in the figure, and the pixel electrode 30 is flat, so as to form a HADS (high aperture-super dimensional switching, abbreviated as HADS) type display device. In this way, the common electrode 60 and the pixel electrode 30, which are disposed in parallel to each other on the array substrate, drive the liquid crystal in the panel switching mode by the horizontal electric field between the common electrode 60 and the pixel electrode 30. The horizontal electric field liquid crystal display has an advantage of a wide viewing angle of about 160 °.
Specifically, the HADS mode is a planar electric field wide viewing angle core technology, and the core technical characteristics of the HADS mode are described as follows: the electric field generated by the edge of the slit electrode (common electrode 60) in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer (pixel electrode 30) form a multi-dimensional electric field, so that all oriented liquid crystal molecules between the slit electrodes and above the electrodes in the liquid crystal box can rotate, the working efficiency of the liquid crystal is improved, and the light transmission efficiency is increased. The switching technology of the HADS mode can improve the picture quality of TFT-LCD products and has the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no extrusion water ripple (pushMura) and the like.
An embodiment of the present invention provides a display device, including any one of the array substrates described above. The array substrate has the same advantages as the array substrate provided by the foregoing embodiment of the present invention, and the details of the array substrate are already described in the foregoing embodiment, so the details are not repeated herein.
The display device may specifically include at least a liquid crystal display device and an organic light emitting diode display device, and for example, the display device may be any product or component having a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
The embodiment of the invention provides a display device, which comprises an array substrate. The array substrate comprises a display area, wherein the display area comprises a plurality of pixel units, each pixel unit comprises a first area and a second area, the first area comprises a thin film transistor, and the second area comprises a pixel electrode. In this case, the first region may further include a test layer on a surface of the drain electrode of the thin film transistor. In the testing time, the testing layer is electrically connected with the pixel electrode so as to test the characteristics of the array substrate; at non-test time, the test layer is insulated from the pixel electrode. Therefore, the pixel electrodes on the array substrate can be directly tested through the test probes on the premise of not influencing the normal use of the array substrate, so that the test accuracy can be ensured, and the test precision, the quality of a display product and the display effect are improved.
The embodiment of the invention provides a manufacturing method of an array substrate, which comprises a method for forming a display area 200. The display region 200 includes a plurality of pixel cells 201 (defined by crossing gate lines 2001 and data lines 2002 that cross in the horizontal and vertical directions). The pixel unit 201 includes a first region 211 and a second region 212. The first region 211 includes the thin film transistor TFT10, and the second region 212 includes the pixel electrode 30. When at least one of the plurality of first regions 211 is the test region 213, as shown in fig. 5, the method for forming the first region 211 includes:
and S101, forming a test layer 40 on the surface of the TFT drain 101.
S102, electrically connecting the testing layer 40 with the pixel electrode 30 at testing time; so that the test probe can test the pixel electrode 30.
S103, insulating the test layer 40 from the pixel electrode 30 during the non-test time.
The test time is specifically required to detect characteristics of the TFT Array substrate during or after the Array process in order to timely detect various defects in the manufacture of the Array substrate and ensure the quality of the Array substrate. Specifically, the pixel electrodes on the array substrate may be tested using test probes. Therefore, the test time is the time for the test probe to perform the characteristic test on the array substrate. The defects of the TFT substrate, such as Mura (Mura) and dark spots, can be detected through the test, so that the quality of the display device and the display effect of the display device are improved. When the testing process is finished, the array substrate will enter the subsequent manufacturing process to finally form the display panel, and the testing layer 40 can be insulated from the pixel electrode 30 to ensure that the array substrate can be used normally, so that the time other than the testing time is a non-testing time in the manufacturing process. Therefore, in the manufacturing process, the other time than the above-described test time is a non-test time. Therefore, the order of the steps S102 and S103 can be adjusted by those skilled in the art according to the requirement of the actual production process.
After the test layer 40 is formed in the step S101 and before the test process is performed, the method for manufacturing the array substrate may include, as shown in fig. 6:
s201, forming a pattern of the passivation layer 20 on the surface of the substrate with the test layer 40 pattern.
And S202, forming a via hole 50 on the surface of the passivation layer 20 pattern corresponding to the position of the test layer 40 pattern through a patterning process.
It should be noted that, in the present invention, the patterning process may refer to a process including a photolithography process, or a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, ink-jetting, etc.; the photolithography process refers to a process of forming a pattern by using a photoresist, a mask plate, an exposure machine, and the like, including processes of film formation, exposure, development, and the like. The corresponding patterning process may be selected according to the structure formed in the present invention.
The embodiment of the invention provides a manufacturing method of an array substrate, which comprises a method for forming a Thin Film Transistor (TFT) and a method for forming a display area. The display area includes a plurality of pixel units. The pixel unit includes a first region and a second region. The first region includes a thin film transistor, and the second region includes a pixel electrode. When at least one of the plurality of first regions is a test region, the method for forming the first region comprises the following steps: and forming a test layer on the surface of the drain electrode of the thin film transistor. Electrically connecting the test layer with the pixel electrode during the test time to test the characteristics of the array substrate; the test layer is insulated from the pixel electrode at a non-test time. Therefore, the pixel electrodes on the array substrate can be directly tested through the test probes on the premise of not influencing the normal use of the array substrate, so that the test accuracy can be ensured, and the test precision, the quality of a display product and the display effect are improved.
Further, the test layer 40 is made of a metal oxide semiconductor material such as: IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), ITGO (In-Sn-Ga-O), Zn0N, ZnO and the like. In this way, the metal oxide semiconductor material can be a conductor by hydrogenation treatment and can be an insulator by oxidation treatment. Therefore, the corresponding process treatment can be carried out on the metal oxide semiconductor material at different manufacturing stages (testing time or non-testing time) so as to meet the manufacturing requirement.
Further, when the test layer 40 is made of a metal oxide semiconductor material, the step S102 may include:
the test layer 40 is subjected to a hydrogenation process to make the test layer 40 have a conductive property so that it can be electrically connected to the pixel electrode 30 through the drain electrode 101 of the TFT to enable a test probe to directly test the pixel electrode 30.
Further, when the test layer 40 is made of a metal oxide semiconductor material, the step S103 may include:
the test layer 40 is oxidized, so that the test layer 40 has an insulating property, and the array substrate can be normally used in a non-test time.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. An array substrate comprises a display area, wherein the display area comprises a plurality of pixel units, each pixel unit comprises a first area and a second area, the first area comprises a thin film transistor, and the second area comprises a pixel electrode; at least one of the first regions is a test region, in this case, the first region further comprises a test layer on the surface of the drain electrode of the thin film transistor;
wherein, at a test time, the test layer is electrically connected with the pixel electrode;
the test layer is insulated from the pixel electrode at a non-test time.
2. The array substrate of claim 1, wherein the plurality of test areas are evenly distributed.
3. The array substrate of claim 1, wherein the test areas are distributed at four corners of the array substrate.
4. The array substrate of claim 1 or 3, wherein the test area is located in a central region of the array substrate.
5. The array substrate of claim 1, wherein the test layer is comprised of a metal oxide semiconductor material.
6. A display device comprising the array substrate according to any one of claims 1 to 5.
7. A manufacturing method of an array substrate comprises a method for forming a display area; the display area comprises a plurality of pixel units, each pixel unit comprises a first area and a second area, the first area comprises a thin film transistor, and the second area comprises a pixel electrode; wherein when at least one of the plurality of first regions is a test region, the method of forming the first region includes:
forming a test layer on the surface of the drain electrode of the thin film transistor;
electrically connecting the test layer with the pixel electrode at a test time;
insulating the test layer from the pixel electrode at a non-test time.
8. The method for manufacturing the array substrate according to claim 7, wherein the test layer is made of a metal oxide semiconductor material.
9. The method for manufacturing the array substrate according to claim 8, wherein the method for electrically connecting the test layer and the pixel electrode at the test time comprises:
the test layer is subjected to a hydrogenation treatment to impart conductivity properties to the test layer.
10. The method for manufacturing the array substrate according to claim 8, wherein the method for insulating the test layer from the pixel electrode at the non-test time comprises:
and carrying out oxidation treatment on the test layer so as to enable the test layer to have insulating property.
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| CN113823593B (en) * | 2021-08-19 | 2023-07-25 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of TFT backboard |
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| CN103021942A (en) * | 2012-12-14 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display device |
| CN103199114A (en) * | 2013-03-25 | 2013-07-10 | 合肥京东方光电科技有限公司 | Thin film transistor and manufacturing method thereof and array substrate and display device |
| CN103197478A (en) * | 2013-03-20 | 2013-07-10 | 合肥京东方光电科技有限公司 | Array substrate and liquid crystal display device |
| CN103700671A (en) * | 2013-12-24 | 2014-04-02 | 华映视讯（吴江）有限公司 | Pixel array substrate and display panel |
| WO2014071634A1 (en) * | 2012-11-12 | 2014-05-15 | 深圳市柔宇科技有限公司 | Self-aligned metal oxide thin film transistor device and manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014071634A1 (en) * | 2012-11-12 | 2014-05-15 | 深圳市柔宇科技有限公司 | Self-aligned metal oxide thin film transistor device and manufacturing method |
| CN103021942A (en) * | 2012-12-14 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display device |
| CN103197478A (en) * | 2013-03-20 | 2013-07-10 | 合肥京东方光电科技有限公司 | Array substrate and liquid crystal display device |
| CN103199114A (en) * | 2013-03-25 | 2013-07-10 | 合肥京东方光电科技有限公司 | Thin film transistor and manufacturing method thereof and array substrate and display device |
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