CN205609509U - 高良率贴装整流器件 - Google Patents

高良率贴装整流器件 Download PDF

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CN205609509U
CN205609509U CN201620293156.8U CN201620293156U CN205609509U CN 205609509 U CN205609509 U CN 205609509U CN 201620293156 U CN201620293156 U CN 201620293156U CN 205609509 U CN205609509 U CN 205609509U
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曹士中
曹春明
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Suzhou De Yao Electronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/8485Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract

本实用新型一种高良率贴装整流器件,包括位于环氧封装体内的第一引线条、第二引线条、连接片和二极管芯片,第二引线条一端是与所述连接片的第一焊接端连接的焊接区,该第二引线条另一端为引脚区,该第二引线条的引脚区作为所述整流器的电流传输端;所述连接片第二焊接端与二极管芯片另一端通过焊锡膏电连接;连接片的第二焊接端为由若干个波峰面和波谷面交替排列组成的波浪形表面,该波浪形表面通过焊锡膏层与二极管芯片电连接,所述连接片的波浪形表面末端位于U形凹槽正上方。本实用新型高良率贴装整流器件增加了接触面积,连接片与引线接触区将增加了65%以上,二极管器件与PCB焊接强度提高。

Description

高良率贴装整流器件
技术领域
本实用新型涉及一种整流器件,尤其涉及一种高良率贴装整流器件。
背景技术
高良率贴装整流器件是一种具有单向传导电流的电子器件,现有高良率贴装整流器件主要存以下技术问题:一方面,器件的内部材料连接方式主要是通过焊片在高温下融化将芯片与引线牢固的连接在一起,但铜质引线与焊锡很难做到100%的融合,通常芯片与连接片有效焊接面积为85%,而引线这一端只有60%左右,导致在大电流通过时,电流分布不均匀,降低了产品承受浪涌的能力。
“焊接”是整流器件生产的关键工艺,特别是二极管类整流器件,设计到芯片与导电引线位置是否工整、焊片是否重复摆放、炉温温度设计是否合理等等,焊接产生的不良品占不良品总量达到80%以上,焊接环节是否处理得当直接影响产品的最终品质,本项目即在整流器件产品设计和生产工艺进行一系列的改良。生产出新一代二极管整流器件。
发明内容
本实用新型目的是提供一种高良率贴装整流器件,该高良率贴装整流器件增加了接触面积,连接片与引线接触区将增加了65%以上,二极管器件与PCB焊接强度提高,从而提高了拉伸强度,电性能改善了。
为达到上述目的,本实用新型采用的技术方案是:一种高良率贴装整流器件,包括位于环氧封装体内的第一引线条、第二引线条、连接片和二极管芯片,该第一引线条一端是与二极管芯片连接的支撑区,所述二极管芯片一端通过焊锡膏与该支撑区电连接,第一引线条另一端是引脚区,该第一引线条的引脚区作为所述整流器的电流传输端;
所述第二引线条一端是与所述连接片的第一焊接端连接的焊接区,该第二引线条另一端为引脚区,该第二引线条的引脚区作为所述整流器的电流传输端;所述连接片第二焊接端与二极管芯片另一端通过焊锡膏电连接;
其特征在于:所述连接片的第二焊接端为由若干个波峰面和波谷面交替排列组成的波浪形表面,该波浪形表面通过焊锡膏层与二极管芯片电连接,所述连接片的波浪形表面末端位于U形凹槽正上方。
上述技术方案中进一步改进的方案如下:
1. 上述方案中,所述第一引线条的支撑区与引脚区之间区域设有一第一折弯处,从而使得第一引线条的支撑区低于引脚区;
所述第二引线条的焊接区与引脚区之间区域设有一第二折弯处,从而使得第二引线条的焊接区低于引脚区;
所述连接片的第一焊接端和第二焊接端之间设有第三折弯处,从而使得第一焊接端低于第二焊接端。
2. 上述方案中,所述第二引线条的焊接区的面积大于所述第一焊接端的面积。
由于上述技术方案运用,本实用新型与现有技术相比具有下列优点和效果:
本实用新型高良率贴装整流器件,其连接片的第二焊接端为由若干个波峰面和波谷面交替排列组成的波浪形表面,该波浪形表面通过所述焊锡膏与二极管芯片电连接,所述连接片的波浪形表面末端位于U形凹槽正上方,根据产品的规格不同可以设计3~6个纹路,在焊接过程中,连接片在高温的作用下变成流动的液体,将填充到波浪区中,增加了接触面积,连接片与引线接触区将增加了65%以上,二极管器件与PCB焊接强度提高,从而提高了拉伸强度,电性能改善了,在不改变引线、芯片以及本体面积的情况下,仅在引线设计时增加10%的引线长度即可解决长期困扰焊接工艺的难题,在仅增加1.3%的成本下创造了产品利润提升了7个百分点;同时由于采用新型的引线焊接点,在采用本工艺,使分立器件关键的焊接工艺水平得到了大幅度的提高,产品在承受不稳定或大电流时,器件始终处于良好的使用状态;其次,其采用本项目设计的新型引线焊接点,能使从外部传递到焊接区的硬拉力逐步被吸收,保证了焊接点免受机械损伤,在生产过程中不会发生任何的内部开裂等不良品,客户对芯片开裂的投诉从每年8件下降到不超过2件。
附图说明
附图1为本实用新型高良率贴装整流器件结构示意图。
以上附图中:1、第一引线条;2、第二引线条;3、连接片;31、第一焊接端;32、第二焊接端;4、二极管芯片;5、支撑区;61、引脚区;62、引脚区;7、焊接区;8、挡块;9、第一折弯处;10、第二折弯处;11、第三折弯处;12、环氧封装体;13、波峰面;14、波谷面;15、焊锡膏层。
具体实施方式
下面结合附图及实施例对本实用新型作进一步描述:
实施例1:一种高良率贴装整流器件,包括位于环氧封装体12内的第一引线条1、第二引线条2、连接片3和二极管芯片4,该第一引线条1一端是与二极管芯片4连接的支撑区5,所述二极管芯片4一端通过焊锡膏与该支撑区5电连接,第一引线条1另一端是引脚区61,该第一引线条1的引脚区61作为所述整流器的电流传输端;
所述第二引线条2一端是与所述连接片3的第一焊接端31连接的焊接区7,该第二引线条2另一端为引脚区62,该第二引线条2的引脚区62作为所述整流器的电流传输端;所述连接片3第二焊接端32与二极管芯片4另一端通过焊锡膏电连接;
所述连接片3的第二焊接端32为由若干个波峰面13和波谷面14交替排列组成的波浪形表面,该波浪形表面通过焊锡膏层15与二极管芯片4电连接,所述连接片3的波浪形表面末端位于U形凹槽48正上方。
上述第一引线条1的支撑区5与引脚区61之间区域设有一第一折弯处9,从而使得第一引线条1的支撑区5低于引脚区61;
上述第二引线条2的焊接区7与引脚区62之间区域设有一第二折弯处10,从而使得第二引线条2的焊接区7低于引脚区62;
上述连接片3的第一焊接端31和第二焊接端32之间设有第三折弯处11,从而使得第一焊接端低于第二焊接端。
实施例2:一种高良率贴装整流器件,包括位于环氧封装体12内的第一引线条1、第二引线条2、连接片3和二极管芯片4,该第一引线条1一端是与二极管芯片4连接的支撑区5,所述二极管芯片4一端通过焊锡膏与该支撑区5电连接,第一引线条1另一端是引脚区61,该第一引线条1的引脚区61作为所述整流器的电流传输端;
所述第二引线条2一端是与所述连接片3的第一焊接端31连接的焊接区7,该第二引线条2另一端为引脚区62,该第二引线条2的引脚区62作为所述整流器的电流传输端;所述连接片3第二焊接端32与二极管芯片4另一端通过焊锡膏电连接;
所述连接片3的第二焊接端32为由若干个波峰面13和波谷面14交替排列组成的波浪形表面,该波浪形表面通过焊锡膏层15与二极管芯片4电连接,所述连接片3的波浪形表面末端位于U形凹槽48正上方。
上述第二引线条2的焊接区7的面积大于所述第一焊接端31的面积。
采用上述高良率贴装整流器件时,其根据产品的规格不同可以设计3~6个纹路,在焊接过程中,连接片在高温的作用下变成流动的液体,将填充到波浪区中,增加了接触面积,连接片与引线接触区将增加了65%以上,二极管器件与PCB焊接强度提高,从而提高了拉伸强度,电性能改善了,在不改变引线、芯片以及本体面积的情况下,仅在引线设计时增加10%的引线长度即可解决长期困扰焊接工艺的难题,在仅增加1.3%的成本下创造了产品利润提升了7个百分点;同时由于采用新型的引线焊接点,在采用本工艺,使分立器件关键的焊接工艺水平得到了大幅度的提高,产品在承受不稳定或大电流时,器件始终处于良好的使用状态;其次,其采用本项目设计的新型引线焊接点,能使从外部传递到焊接区的硬拉力逐步被吸收,保证了焊接点免受机械损伤,在生产过程中不会发生任何的内部开裂等不良品,客户对芯片开裂的投诉从每年8件下降到不超过2件。
上述实施例只为说明本实用新型的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本实用新型的内容并据以实施,并不能以此限制本实用新型的保护范围。凡根据本实用新型精神实质所作的等效变化或修饰,都应涵盖在本实用新型的保护范围之内。

Claims (3)

1. 一种高良率贴装整流器件,包括位于环氧封装体(12)内的第一引线条(1)、第二引线条(2)、连接片(3)和二极管芯片(4),该第一引线条(1)一端是与二极管芯片(4)连接的支撑区(5),所述二极管芯片(4)一端通过焊锡膏与该支撑区(5)电连接,第一引线条(1)另一端是引脚区(61),该第一引线条(1)的引脚区(61)作为所述整流器的电流传输端;
所述第二引线条(2)一端是与所述连接片(3)的第一焊接端(31)连接的焊接区(7),该第二引线条(2)另一端为引脚区(62),该第二引线条(2)的引脚区(62)作为所述整流器的电流传输端;所述连接片(3)第二焊接端(32)与二极管芯片(4)另一端通过焊锡膏电连接;
其特征在于:所述连接片(3)的第二焊接端(32)为由若干个波峰面(13)和波谷面(14)交替排列组成的波浪形表面,该波浪形表面通过焊锡膏层(15)与二极管芯片(4)电连接,所述连接片(3)的波浪形表面末端位于U形凹槽(48)正上方。
2. 根据权利要求1所述高良率贴装整流器件,其特征在于:所述第一引线条(1)的支撑区(5)与引脚区(61)之间区域设有一第一折弯处(9),从而使得第一引线条(1)的支撑区(5)低于引脚区(61);
所述第二引线条(2)的焊接区(7)与引脚区(62)之间区域设有一第二折弯处(10),从而使得第二引线条(2)的焊接区(7)低于引脚区(62);
所述连接片(3)的第一焊接端(31)和第二焊接端(32)之间设有第三折弯处(11),从而使得第一焊接端低于第二焊接端。
3. 根据权利要求1所述高良率贴装整流器件,其特征在于:所述第二引线条(2)的焊接区(7)的面积大于所述第一焊接端(31)的面积。
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CN107293597A (zh) * 2016-04-11 2017-10-24 苏州锝耀电子有限公司 表面贴装整流器件

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CN107293597A (zh) * 2016-04-11 2017-10-24 苏州锝耀电子有限公司 表面贴装整流器件

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