CN205810817U - 三极管 - Google Patents

三极管 Download PDF

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CN205810817U
CN205810817U CN201620768519.9U CN201620768519U CN205810817U CN 205810817 U CN205810817 U CN 205810817U CN 201620768519 U CN201620768519 U CN 201620768519U CN 205810817 U CN205810817 U CN 205810817U
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chip
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林乐
陈孟旭
王官标
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Zhejiang Yizhong Packaging Technology Co ltd
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Zhejiang Qianjiang Motorcycle Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4846Connecting portions with multiple bonds on the same bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)

Abstract

本实用新型提供了三极管,属于电气元件技术领域。它解决了现有三极管产生的热量较多等技术问题。本三极管包括基板和三根引脚,基板上固定有芯片,三个引脚包括直接与基板连接的第一引脚以及位于第一引脚两侧的第二引脚和第三引脚,第二引脚和第三引脚通过固定在基板上的塑封壳与基板固定,芯片的S极通过第一引线与第二引脚连接,芯片的G极通过第二引线与第三引脚连接,第一引线具有三根,每根第一引线的一端均具有固定段一,固定段一的中部具有弯折部,固定段一的两端贴靠在芯片的S极表面,弯折部相对芯片的S极表面凸起,固定段一的两端均通过点焊固定在芯片上。本实用新型具有减少三极管内部产生的热量的优点。

Description

三极管
技术领域
本实用新型属于电气元件技术领域,涉及一种三极管。
背景技术
功率三极管的芯片结构为两个很大区域的S极与一个单独小框的G极构成同一平面,三极管的芯片和引脚通过引线连接,普通焊线方式为在S极的每个区域焊接一根粗铝线,G极焊接一根细铝线来达到与框架联通的目的,通常的焊接方式为在一个区域内焊一个点。
由于功率器件在工作状态下要过大电流,会产生大量热量,引线被塑封在塑封壳内,因减少引线的散热量,避免散热不及时对芯片的伤害。塑封壳内的热量主要来源是电流通过引线时因引线的内阻以及引线与芯片接触处的导通电阻产生的,引线的内阻与引线的长度呈正比,引线和芯片接触处的导通电阻与引线与芯片的接触面积呈反比。
目前引线和芯片通过一个焊点来实现接触,引线与芯片的接触面积较小,导致引线和芯片接触处的导通电阻较大,导致该接触处产生的热量较多。
发明内容
本实用新型的目的是针对现有的技术存在上述问题,提出了一种三极管,本实用新型解决的技术问题是减少三极管内部产生的热量。
本实用新型的目的可通过下列技术方案来实现:
三极管,包括基板和三根引脚,所述基板上固定有具有S极和G极的芯片,三个所述引脚包括直接与基板连接的第一引脚以及位于第一引脚两侧的第二引脚和第三引脚,所述第二引脚和第三引脚通过固定在基板上的塑封壳与基板固定,所述芯片的S极通过第一引线与第二引脚连接,所述芯片的G极通过第二引线与第三引脚连接,其特征在于,所述第一引线具有三根,三根所述第一引线的长度相同,每根所述第一引线的一端均具有固定段一,所述固定段一呈长条形,所述固定段一的中部具有弯折部,所述固定段一的两端贴靠在芯片的S极表面,所述弯折部相对芯片的S极表面凸起,所述固定段一的两端均通过点焊固定在芯片上,每根所述第一引线的另一端均具有固定段二,所述固定段二与第二引脚通过电焊固定。
固定段一的两端通过点焊固定在芯片上形成两个焊点,也就是三根第一引线与芯片固定时形成了六个焊点,三根第一引线形成的六个焊点大大增加了与芯片之间的接触面积,因而能减小芯片与第二引脚之间的导通电阻,从而减小了热量的产生,进而减少三极管内部产生的热量,避免因热量过高烧掉芯片;同时长度相同的三根第一引线内阻均相同,使得三根第一引线产生的热量均相同,确保三极管内部散热均匀。
在上述的三极管中,所述第一引线位于固定段一和固定段二之间的一段为连接段,所述连接段弯折呈弧形。该结构的连接段相对现有弯折呈直角的引线长度更短,更短的第一引线能减少发热,避免烧坏芯片。
在上述的三极管中,所述第一引线和第二引线均采用铝线制成。铝线便于焊接且电阻较低,通电后产热较少,避免烧坏芯片。
在上述的三极管中,所述第一引线的直径为13mil~17mil。三根第一引线的单根长度减少。
在上述的三极管中,所述芯片和基板之间设有焊锡层,所述芯片完全固定在焊锡层上。通过该结构避免出现芯片下少锡的情况,使得芯片和基板之间的电联接稳定。
与现有技术相比,本三极管具有减少三极管内部产生的热量的优点。
附图说明
图1是三极管的结构示意图。
图2是三极管中固定段一与芯片连接的放大结构示意图。
图中,1、基板;2、芯片;21、S极;22、G极;3、焊锡层;4、第一引脚;5、第二引脚;51、第一引线;52、固定段一;521、弯折部;53、固定段二;54、连接段;6、第三引脚;61、第二引线;7、塑封壳。
具体实施方式
以下是本实用新型的具体实施例并结合附图,对本实用新型的技术方案作进一步的描述,但本实用新型并不限于这些实施例。
如图1和图2所示,三极管包括基板1和三根引脚,基板1上固定有具有S极21和G极22的芯片2,芯片2和基板1之间设有焊锡层3,芯片2完全固定在焊锡层3上;三个引脚包括直接与基板1连接的第一引脚4以及位于第一引脚4两侧的第二引脚5和第三引脚6,第二引脚5和第三引脚6通过固定在基板1上的塑封壳7与基板1固定,芯片2的S极21通过第一引线51与第二引脚5连接,芯片2的G极22通过第二引线61与第三引脚6连接,第一引线51和第二引线61均采用铝线制成。
第一引线51的直径为13mil~17mil,作为优选,第一引线51的直径为13mil、15mil和17mil;第一引线51具有三根,三根第一引线51的长度相同,每根第一引线51的一端均具有固定段一52,固定段一52呈长条形,固定段一52的中部具有弯折部521,固定段一52的两端贴靠在芯片2的S极21表面,弯折部521相对芯片2的S极21表面凸起,固定段一52的两端均通过点焊固定在芯片2上,每根第一引线51的另一端均具有固定段二53,固定段二53与第二引脚5通过电焊固定。
第一引线51位于固定段一52和固定段二53之间的一段为连接段54,连接段54弯折呈弧形。该结构的连接段54相对现有弯折呈直角的引线长度更短,更短的第一引线51能减少发热,避免烧坏芯片2。
固定段一52的两端通过点焊固定在芯片2上形成两个焊点,也就是三根第一引线51与芯片2固定时形成了六个焊点,三根第一引线51形成的六个焊点大大增加了与芯片2之间的接触面积,因而能减小芯片2与第二引脚5之间的导通电阻,从而减小了热量的产生,进而减少三极管内部产生的热量,避免因热量过高烧掉芯片2;同时长度相同的三根第一引线51内阻均相同,使得三根第一引线51产生的热量均相同,确保三极管内部散热均匀。
本文中所描述的具体实施例仅仅是对本实用新型精神作举例说明。本实用新型所属技术领域的技术人员可以对所描述的具体实施例做各种各样的修改或补充或采用类似的方式替代,但并不会偏离本实用新型的精神或者超越所附权利要求书所定义的范围。

Claims (5)

1.三极管,包括基板(1)和三根引脚,所述基板(1)上固定有具有S极(21)和G极(22)的芯片(2),三个所述引脚包括直接与基板(1)连接的第一引脚(4)以及位于第一引脚(4)两侧的第二引脚(5)和第三引脚(6),所述第二引脚(5)和第三引脚(6)通过固定在基板(1)上的塑封壳(7)与基板(1)固定,所述芯片(2)的S极(21)通过第一引线(51)与第二引脚(5)连接,所述芯片(2)的G极(22)通过第二引线(61)与第三引脚(6)连接,其特征在于,所述第一引线(51)具有三根,三根所述第一引线(51)的长度相同,每根所述第一引线(51)的一端均具有固定段一(52),所述固定段一(52)呈长条形,所述固定段一(52)的中部具有弯折部(521),所述固定段一(52)的两端贴靠在芯片(2)的S极(21)表面,所述弯折部(521)相对芯片(2)的S极(21)表面凸起,所述固定段一(52)的两端均通过点焊固定在芯片(2)上,每根所述第一引线(51)的另一端均具有固定段二(53),所述固定段二(53)与第二引脚(5)通过电焊固定。
2.根据权利要求1所述的三极管,其特征在于,所述第一引线(51)位于固定段一(52)和固定段二(53)之间的一段为连接段(54),所述连接段(54)弯折呈弧形。
3.根据权利要求1所述的三极管,其特征在于,所述第一引线(51)和第二引线(61)均采用铝线制成。
4.根据权利要求1或2或3所述的三极管,其特征在于,所述第一引线(51)的直径为13mil~17mil。
5.根据权利要求1或2或3所述的三极管,其特征在于,所述芯片(2)和基板(1)之间设有焊锡层(3),所述芯片(2)完全固定在焊锡层(3)上。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035817A (zh) * 2019-12-25 2021-06-25 上海凯虹科技电子有限公司 一种封装体

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113035817A (zh) * 2019-12-25 2021-06-25 上海凯虹科技电子有限公司 一种封装体

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