CN205177852U - HEMT device based on silicon substrate - Google Patents
HEMT device based on silicon substrate Download PDFInfo
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- CN205177852U CN205177852U CN201520849171.1U CN201520849171U CN205177852U CN 205177852 U CN205177852 U CN 205177852U CN 201520849171 U CN201520849171 U CN 201520849171U CN 205177852 U CN205177852 U CN 205177852U
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Abstract
The utility model provides a HEMT device based on silicon substrate forms gaN epitaxial layer, a alxGa (1 -x) N layer, the 2nd alzGa (1 -z) N layer in proper order on the silicon substrate, adopt the epitaxial structure of alGaNAlGaN heterojunction, utilizes the alGaN alloy -layer to compare and wears the characteristic in the resistance that gaN is better, has improved the holistic seal pressure of HEMT device based on silicon substrate.
Description
Technical field
The utility model relates to technical field of manufacturing semiconductors, particularly a kind of HEMT device based on silicon substrate.
Background technology
Compared to first and second semi-conducting material in generation, third generation semi-conducting material gallium nitride (GaN), because have larger energy gap (3.4eV), stronger critical breakdown strength and higher electron transfer rate, obtains the extensive concern of domestic and international researchers.Especially in high-voltage power electronic device and high-frequency power device, there is huge advantage and potential.
Specifically, as third generation semi-conducting material, gallium nitride (GaN) material has the advantage that energy gap is wide, breakdown electric field is high, power output is large, and conducting resistance when GaN material under high pressure works is little, makes GaN base power device also show higher gain.Meanwhile, GaN base power device has very high electron mobility and electron saturation velocities, ensure that this device is in Ka, Q even high-gain of W-waveband.Therefore, High Electron Mobility Transistor (HighElectronMobilityTransistor the is called for short HEMT) technology of GaN base has become the focus of current millimeter wave high power device area research.
Because GaN crystal growth receives the restriction of objective condition, most researchers are selected at foreign substrate material Epitaxial growth GaN film.Conventional substrate comprises silicon (Si), sapphire (Al
2o
3) and carborundum (SiC) etc.Wherein Si material receives the favor of Ge great research institution due to the advantage of the aspects such as its cheap cost, large scale and perfect Si integrated technique.
In high-voltage power electronic device application, breakdown characteristics is one of most important parameter, but practice finds, the breakdown characteristics of traditional HEMT device is not ideal enough.
In addition, the HEMT device based on silicon substrate that routine techniques makes is all adopt AlGaN/GaN heterojunction, due to the modulating action of the polarized electric field of inherence, in AlGaN/GaN heterojunction, a large amount of conduction electronss can be assembled in the side near AlGaN, form two-dimensional electron gas (2DEG).Based on the restriction of epitaxial structure.This electron gas is limited in narrow region, reduces the probability that they are subject to scattering, thus improves its transfer ability, and typical mobility is 1500cm
2/ V.s.The concentration of 2DEG also can up to 1 × 10
13/ cm
2.Owing to there is 2DEG, the HEMT device that routine techniques makes is all conducting when zero is inclined, the namely device of depletion type (open type).But depletion device adds power consumption and design complexity in circuit application.Simultaneously in the application of power electronic, enhancement device can improve the fail safe of circuit working, and when grid lose efficacy, device can realize off state, realizes the function of fail safe, so realizing enhancement mode HEMT device is an important research direction.
Utility model content
The purpose of this utility model is to provide a kind of HEMT device based on silicon substrate, to solve the problem of existing HEMT device poor voltage withstand capability.
For solving the problems of the technologies described above, the utility model provides a kind of HEMT device based on silicon substrate, comprising:
Silicon substrate;
Be formed at the GaN epitaxial layer on described silicon substrate, an Al
xga
(1-x)n layer and the 2nd Al
zga
(1-z)n layer, wherein, 0<x<0.1,0.15≤z≤0.4;
Be formed at described 2nd Al
zga
(1-z)grid on N layer, source electrode and drain electrode.
Optionally, described based in the HEMT device of silicon substrate, also comprise and be formed at a described Al
xga
(1-x)n layer and the 2nd Al
zga
(1-z)the 3rd Al between N layer
yga
(1-y)n layer, wherein, y<x.
Optionally, described based in the HEMT device of silicon substrate, 0.07≤x<0.1,0.05≤y<0.1,0.2≤z≤0.3.
Optionally, described based in the HEMT device of silicon substrate, described grid embeds described 2nd Al
zga
(1-z)in N layer.
Optionally, described based in the HEMT device of silicon substrate, the thickness of described GaN epitaxial layer is 100nm ~ 500nm, a described Al
xga
(1-x)the thickness of N layer is 1 μm ~ 5 μm, described 2nd Al
zga
(1-z)the thickness of N layer is 15nm ~ 40nm, described 3rd Al
yga
(1-y)the thickness of N layer is 100nm-400nm.
Optionally, described based in the HEMT device of silicon substrate, the nucleating layer be formed between described silicon substrate and GaN epitaxial layer is also comprised.Described nucleating layer is AlN layer, and the thickness of described nucleating layer is 80nm ~ 120nm.
Optionally, described based in the HEMT device of silicon substrate, the first resilient coating be formed between described silicon substrate and GaN epitaxial layer is also comprised.
Optionally, described based in the HEMT device of silicon substrate, described first resilient coating is multilayer Al
kga
(1-k)n layer, described multilayer Al
kga
(1-k)the Al component k of N layer successively declines.Described first resilient coating comprises three layers of Al
kga
(1-k)n layer, described three layers of Al
kga
(1-k)in N layer, Al component k is followed successively by 0.7 ~ 0.9,0.45 ~ 0.7 and 0.2 ~ 0.45.
Optionally, described based in the HEMT device of silicon substrate, described first resilient coating is multilayer Al
kga
(1-k)n layer, described multilayer Al
kga
(1-k)the growth thickness of N layer successively increases.Described first resilient coating comprises three layers of Al
kga
(1-k)n layer, described three layers of Al
kga
(1-k)the thickness of N layer is followed successively by 150nm ~ 200nm, 200nm ~ 250nm and 250nm ~ 300nm.
Optionally, described based in the HEMT device of silicon substrate, also comprise and be formed at described GaN epitaxial layer and an Al
xga
(1-x)superlattice layer between N layer.Described superlattice layer is the Al in 5 ~ 15 cycles
mga
(1-m)n/GaN layer, wherein, 0.05≤m<1, the thickness of described superlattice layer is 80nm ~ 240nm.
Optionally, described based in the HEMT device of silicon substrate, also comprise the second resilient coating, described second resilient coating is formed at a described Al
xga
(1-x)n layer and the 3rd Al
yga
(1-y)between N layer.
Optionally, described based in the HEMT device of silicon substrate, the second resilient coating is also comprised, a described Al
xga
(1-x)n layer is formed at twice, and described second resilient coating is inserted into a described Al
xga
(1-x)in N layer.
Optionally, described based in the HEMT device of silicon substrate, described second resilient coating is AlN layer, and the thickness of described second resilient coating is 2nm ~ 10nm.
Optionally, described based in the HEMT device of silicon substrate, also comprise:
Expose the described Al of part
xga
(1-x)the table top of N layer;
Cover described 2nd Al
zga
(1-z)the Al that N layer and described table top expose
xga
(1-x)first passivation layer of N layer;
Run through described first passivation layer and the 2nd Al
zga
(1-z)the gate openings of N layer;
Run through source contact openings and the drain openings of described first passivation layer.
Optionally, described based in the HEMT device of silicon substrate, also comprise:
Be formed at the gate dielectric layer on described first passivation layer and bottom described gate openings;
Be formed at the bottom of described gate openings and the potential barrier barrier layer of sidewall.
Optionally, described based in the HEMT device of silicon substrate, described grid, source electrode and drain electrode are Ti/Al/Ti/TiN alloy, Ti/Al/Ni/Au alloy or Ti/Al/Ni/Cu alloy, and described gate dielectric layer is TiN, AlN or Si
3n
4.
Optionally, described based in the HEMT device of silicon substrate, also comprise:
Cover the second passivation layer of described grid, source electrode, drain electrode and gate dielectric layer;
Run through described second passivation layer to expose the through hole of described grid, source electrode and drain electrode;
The gate pad be electrically connected with described grid, the source pad be electrically connected with described source electrode and with the described drain bonding pad be electrically connected that drains.
The utility model forms GaN epitaxial layer, an Al on a silicon substrate successively
xga
(1-x)n layer and the 2nd Al
zga
(1-z)n layer, by adopting the epitaxial structure of AlGaN/AlGaN heterojunction, make AlGaN layer replace GaN layer simple in prior art as the channel layer of device, utilize AlGaN compared to the better breakdown characteristics of GaN, improve the voltage endurance capability of the HEMT device entirety based on silicon substrate.
Further, the utility model is at an Al
xga
(1-x)n layer and the 2nd Al
zga
(1-z)the 3rd Al is formed between N layer
yga
(1-y)n layer, grid embeds described 2nd Al
zga
(1-z)in N layer and with the 3rd Al
yga
(1-y)n layer contacts, and further, forms the 2nd Al
zga
(1-z)form the first passivation layer after N layer, then adopt deep etching technology to form opening in the first passivation layer, formed and the 2nd Al
zga
(1-z)the source electrode of N layer ohmic contact and drain electrode, at grid and the 3rd Al
yga
(1-y)potential barrier barrier layer and gate dielectric layer is formed between N layer, and by the 2nd Al under gate region
zga
(1-z)n layer etches away, and the density of the two-dimensional electron gas under gate region is reduced, and the transfer characteristic curve of device can move by forward, therefore can realize the HEMT device of the enhancement mode based on silicon substrate.
Accompanying drawing explanation
Fig. 1 is the generalized section of the HEMT device based on silicon substrate of the utility model embodiment one;
Fig. 2 is the generalized section of the HEMT device based on silicon substrate of the utility model embodiment two;
Fig. 3 ~ 15 are device profile schematic diagrames based on each step in the HEMT device manufacture process of silicon substrate of the utility model embodiment two.
Embodiment
For enabling above-mentioned purpose of the present utility model, feature and advantage become apparent more, are described in detail embodiment of the present utility model below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the utility model, but the utility model can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when doing similar popularization without prejudice to when the utility model intension, and therefore the utility model is by the restriction of following public specific embodiment.
Secondly, the utility model is described in detail in conjunction with schematic diagram, when describing the utility model embodiment in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of the utility model protection at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual manufacture.
As described in background, enhancement mode HEMT device voltage endurance capability based on silicon substrate in prior art is not ideal enough, inventor studies discovery, occur that the reason of this problem is, traditional HEMT device adopts GaN layer to be not enough to as the channel layer of device the breakdown characteristics requirement meeting overall device.And for power electronic device, higher puncture voltage is one of most important index of device pursuit always.In order to solve the problems of the technologies described above, the utility model adopts the epitaxial structure of AlGaN/AlGaN heterojunction, utilizes AlGaN compared to the better breakdown characteristics of GaN, improves the voltage endurance capability of overall device.
In addition, traditional AlGaN/GaN heterojunction device, due to piezoelectricity and spontaneous polarization effect, is generally depletion device, and the utility model forms the 2nd Al
zga
(1-z)form the first passivation layer after N layer, then adopt deep etching technology to form opening in the first passivation layer, formed and the 2nd Al
zga
(1-z)the source electrode of N layer ohmic contact and drain electrode, and by the 2nd Al under gate region
zga
(1-z)n layer etches away formation gate openings, and the density of the two-dimensional electron gas under gate region is reduced, and the transfer characteristic curve of device can move by forward, therefore can realize the HEMT device of enhancement mode (normally-off).
Embodiment one
Fig. 1 is the generalized section of the HEMT device based on silicon substrate of the present embodiment.As shown in Figure 1, a kind of HEMT device based on silicon substrate, comprising:
Silicon substrate 100;
Be formed at the GaN epitaxial layer 103 on described silicon substrate 100, an Al
xga
(1-x)n layer 105, the 2nd Al
zga
(1-z)n layer 108, wherein, 0<x<0.1,0.15≤z≤0.4;
Be formed at described 2nd Al
zga
(1-z)grid 1091 on N layer 108, source electrode 1092 and drain electrode 1093, in the present embodiment, described grid 1091 embeds described 2nd Al
zga
(1-z)a described Al is connected in N layer 108
xga
(1-x)n layer 105.
The present embodiment also provides a kind of manufacture method of the HEMT device based on silicon substrate, comprising:
One silicon substrate 100 is provided;
Described silicon substrate 100 is formed GaN epitaxial layer 103, an Al
xga
(1-x)n layer 105, the 2nd Al
zga
(1-z)n layer 108; And
At the 2nd Al
zga
(1-z)n layer 108 is formed source electrode 1092, drain electrode 1093 and grid 1091.
In the present embodiment, before forming GaN epitaxial layer 103, first on described silicon substrate 100, grow into stratum nucleare 101, described nucleating layer 101 is as follow-up nucleation node, described nucleating layer 101 is such as AlN layer, the formation temperature of described nucleating layer 101 is such as 1200 DEG C ~ 1300 DEG C, and its thickness is such as 80nm ~ 120nm.
Due to AlN material with there is lattice between GaN material and not mate and thermal expansion is not mated, therefore, in preferred version, before forming GaN epitaxial layer 103, also on described nucleating layer 101, growing the first resilient coating 102, alleviating owing to not mating the stress caused by inserting described first resilient coating 102.Described first resilient coating 102 is preferably multilayer Al
kga
(1-k)n layer, described multilayer Al
kga
(1-k)in N layer, Al component k successively declines, and along with the reduction of Al component, the lattice structure of described first resilient coating 102, more and more close to the follow-up GaN epitaxial layer 103 formed, so can obtain preferably Lattice Matching effect thereon.As a preferred scheme, described first resilient coating 102 comprises three layers of Al altogether
kga
(1-k)n layer, described three layers of Al
kga
(1-k)the Al component k of N layer is followed successively by 0.7 ~ 0.9,0.45 ~ 0.7 and 0.2 ~ 0.45, and be preferably 0.8,0.45 and 0.2, namely the molar concentration of Al component is respectively 80%, 45%, 20%.As another preferred scheme, described three layers of Al
kga
(1-k)the growth thickness of N layer successively increases, and is followed successively by 150nm ~ 200nm, 200nm ~ 250nm and 250nm ~ 300nm, is preferably 180nm, 230nm and 280nm.Find through experiment, above-mentioned Al component k successively declines and is equipped with the compound mode that growth thickness increases gradually, can obtain best effect.
Described GaN epitaxial layer 103 is in order to realize the object of level and smooth epi-layer surface.If consider, the thickness of GaN epitaxial layer 103 is too thin not easily forms even curface, and Si and GaN lattice constant difference is larger, if the stress that the too thick easy generation of the thickness of GaN epitaxial layer 103 is larger, so the thickness of described GaN epitaxial layer is set between 100nm ~ 500nm by the present embodiment, film quality is better.
After forming GaN epitaxial layer 103, form a described Al
xga
(1-x)before N layer 105, also in GaN epitaxial layer 103, grow superlattice layer 104, described superlattice layer 104 is the Al in 5 ~ 15 cycles
mga
(1-m)n/GaN layer, to reduce the stress of extension accumulation, improves epitaxial film quality.In the present embodiment, described superlattice layer 104 is the Al in 10 cycles
mga
(1-m)n/GaN layer, the Al of described superlattice layer 104
mga
(1-m)in N, 0.05≤m<1, is preferably 0.08.
After forming superlattice layer 104, superlattice layer 104 grows an Al
xga
(1-x)n layer 105, a described Al
xga
(1-x)in N layer 105,0<x<0.1, preferably, 0.07≤x<0.1.A described Al
xga
(1-x)the thickness of N layer 105 is 1 μm ~ 5 μm.Due to a described Al
xga
(1-x)the thickness of N layer 105 is comparatively large, can be formed at twice, twice formation the one Al
xga
(1-x)between N layer, inserting one second resilient coating, alleviating the tensile stress of extension accumulation by inserting described second resilient coating further.Described second resilient coating is such as AlN layer, and compared to nucleating layer 101, the formation temperature of described second resilient coating is lower, such as, be less than 700 DEG C.The thickness of described second resilient coating is 2nm ~ 10nm.For succinctly, the Al formed at twice in the present embodiment
xga
(1-x)n layer all represents with label 105, and not shown the second resilient coating wherein inserted.
Form an Al
xga
(1-x)after N layer 105, at a described Al
xga
(1-x)n layer 105 grows the 2nd Al
zga
(1-z)n layer 108.A described Al
xga
(1-x)n layer 105, as the channel layer of whole HEMT device, is the key of the anti-compression property improving integral material.Described 2nd Al
zga
(1-z)n layer 108 as the barrier functions layer of whole HEMT device, in order to provide polarization charge, wherein, 0.15≤z≤0.4, preferably, 0.2≤z≤0.3.Described 2nd Al
zga
(1-z)the thickness of N layer 108 is 15nm ~ 40nm.
The present embodiment adopts Al
xga
(1-x)n/Al
zga
(1-z)the epitaxial structure of N heterojunction, forms conducting channel.Described grid 1091 embeds described 2nd Al
zga
(1-z)in N layer 108.Adopt AlGaN alloy-layer to replace the channel layer of simple GaN layer as device, utilize AlGaN alloy-layer better breakdown characteristics itself, improve the voltage endurance capability of overall device.
Find through experiment, adopt above-mentioned nucleating layer 101, first resilient coating 102, GaN epitaxial layer 103, superlattice layer 104, an Al
xga
(1-x)n layer 105, the 2nd Al
zga
(1-z)the mode of N layer 108 lamination, the best of epitaxial film quality.Meanwhile, above-mentioned film thickness cooperatively interacts, and effect is especially desirable.
Further, the described HEMT device based on silicon substrate also comprises:
Expose the described Al of part
xga
(1-x)the table top of N layer 105;
Cover described 2nd Al
zga
(1-z)the Al that N layer 108 and described table top expose
xga
(1-x)first passivation layer 110 of N layer;
Run through described first passivation layer 110 and the 2nd Al
zga
(1-z)the gate openings of N layer 108;
Run through source contact openings and the drain openings of described first passivation layer 110;
Be formed on described first passivation layer 110 and the gate dielectric layer 111 of gate openings sidewall;
Be formed at the bottom of described gate openings and the potential barrier barrier layer 112 of sidewall;
Cover the second passivation layer 114 of described grid 1091, source electrode 1092, drain 1093 and gate dielectric layer 111;
Run through described second passivation layer 114 to expose the through hole of described grid 1091, source electrode 1092, drain electrode 1093;
Respectively with described grid 1091, source electrode 1092, drain 1093 gate pad be electrically connected 1161, source pad 1162, drain bonding pad 1163; And
Be formed at the 3rd passivation layer 117 on the second passivation layer 114, described 3rd passivation layer 117 has the opening exposing described gate pad 1161, source pad 1162, drain bonding pad 1163.
Embodiment two
Concrete with reference to shown in Figure 15, the present embodiment and embodiment one difference are, an Al
xga
(1-x)n layer 105 and the 2nd Al
zga
(1-z)the 3rd Al is formed between N layer 108
yga
(1-y)n layer 107, wherein, y<x.Preferably, described 3rd Al
yga
(1-y)the speed of growth of N layer 107 is slower than a described Al
xga
(1-x)the speed of growth of N layer 105.
The HEMT device based on silicon substrate of the present embodiment is further described below in conjunction with Fig. 2 to Figure 15.
Shown in figure 2, provide a silicon substrate 100, described silicon substrate 100 can be 2 inches to 12 inch silicon wafer, but be not limited to this.
Continue with reference to shown in figure 2, described silicon substrate 100 is formed into stratum nucleare 101, first resilient coating 102, GaN epitaxial layer 103, superlattice layer 104, an Al successively
xga
(1-x)n layer 105, second resilient coating 106, the 3rd Al
yga
(1-y)n layer 107, the 2nd Al
zga
(1-z)n layer 108.
Shown in figure 3, etch described 2nd Al
zga
(1-z)n layer 108, the 3rd Al
yga
(1-y)n layer 107 forms a table top 108a, and described table top 108a exposes part the 3rd Al
yga
(1-y)n layer 107, described table top 108a is such as circular table.
Shown in figure 4, form one first passivation layer 110, described first passivation layer 110 covers described 2nd Al
zga
(1-z)3rd Al of N layer 108 and table top 108a exposure place
yga
(1-y)n layer 107, the material of described first passivation layer 110 is such as Si
3n
4, formed by LPCVD or ALD mode.
Shown in figure 5, etch described first passivation layer 110 and the 2nd Al
zga
(1-z)n layer 108 forms gate openings 109a, and described gate openings 109a exposes described 3rd Al
yga
(1-y)n layer 107.
The utility model is by etching first passivation layer 110 and the 2nd Al
zga
(1-z)n layer 108 forms gate openings 109a, by the 2nd Al under gate region
zga
(1-z)n layer 108 etches away, as the 2nd Al
zga
(1-z)when N layer 108 is thinned to a certain degree, under gate region, 2DEG density will be reduced to negligible degree, and source, drain region do not affect by etching, the 2DEG density in these regions maintains original level, and such device saturation current and mutual conductance have good lifting.Thus, the utility model by reducing raceway groove 2DEG density, making in the 2DEG density of grid voltage zero offset situation lower channel little of ignoring, realizing HEMT device enhancement mode characteristic on the basis of D-HEMT (depletion type HEMT device).
In preferred version, deep etching technology is adopted to form described gate openings 109a.In described deep etching technology, preferably adopt ICP (inductively coupled plasma etching) etching machine, the etching gas of employing is Cl
2, etch rate is 1 ~ 3nm/min.Adopt aforesaid way, accurately can control the degree of depth etched, process repeatability can be well controlled.
Shown in figure 6, by LPCVD mode deposit gate dielectric layer 111, and the gate dielectric layer removed on the first passivation layer 110 above the gate dielectric layer 111 of described gate openings 109a sidewall and described table top 108a, only retain the gate dielectric layer 111 on described first passivation layer 110 and bottom gate openings 109a.The material of described gate dielectric layer 111 is such as TiN, AlN or Si
3n
4.
Shown in figure 7, form potential barrier barrier layer 112, described potential barrier barrier layer 112 covers the first passivation layer 110 above described gate dielectric layer 111 and table top 108a.The material on described potential barrier barrier layer 112 is such as titanium nitride.
Shown in figure 8, etch described potential barrier barrier layer 112, gate dielectric layer 111 and the first passivation layer 110 and form source contact openings 109b and drain openings 109c.
Shown in figure 9, sputtering forms the first metal layer 113, the material of described the first metal layer 113 is such as Ti/Al/Ti/TiN alloy, Ti/Al/Ni/Au alloy or Ti/Al/Ni/Cu alloy, the thickness of described Ti/Al/Ti/TiN is such as respectively 20nm, 100nm, 70nm, 200nm, the first metal layer 113 and the 2nd Al
zga
(1-z)n layer 108 forms ohmic contact.
With reference to shown in Figure 10, the first metal layer 113 of the exterior domain of the described source contact openings 109b of etching removal, drain openings 109c and gate openings 109a and potential barrier barrier layer 112, thus form grid 1091, source electrode 1092, drain electrode 1093.
With reference to shown in Figure 11, form the second passivation layer 114, described second passivation layer 114 cover gate 1091, source electrode 1092, drain electrode 1093 and gate dielectric layer 111, the material of described second passivation layer 114 is such as Si
3n
4, formed by LPCVD or ALD mode.
With reference to shown in Figure 12, etch described second passivation layer 114 and form through hole 114a, described through hole 114a expose described source gate 1091,1092, drain electrode 1093.
With reference to shown in Figure 13, sputtering or evaporation formation second metal level 115, the material of described second metal level 115 is such as Al.
With reference to shown in Figure 14, etch described second metal level 115, thus form gate pad 1161, source pad 1162, drain bonding pad 1163.
With reference to shown in Figure 15; after forming gate pad 1161, source pad 1162, drain bonding pad 1163; also the 3rd passivation layer 117 can be formed thereon; described 3rd passivation layer 117 has the opening exposing described weld pad 116; the material of described 3rd passivation layer 117 is such as silicon dioxide, and it is injury-free in order to protection device.
Thus, silicon substrate 100 manufactures the HEMT device of enhancement mode, adopt AlGaN alloy-layer instead of traditional GaN layer as the channel layer of heterojunction, thus the anti-compression property of whole material structure can be improved.
In this specification, each embodiment adopts the mode of going forward one by one to describe, what each embodiment stressed is the difference with other embodiments, device architecture in each embodiment and manufacture method interrelated, and between each embodiment identical similar portion mutually see.
Foregoing description is only the description to the utility model preferred embodiment; any restriction not to the utility model scope; any change that the those of ordinary skill in the utility model field does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (12)
1. based on a HEMT device for silicon substrate, it is characterized in that, comprising:
Silicon substrate;
Be formed at the GaN epitaxial layer on described silicon substrate, an Al
xga
(1-x)n layer and the 2nd Al
zga
(1-z)n layer, wherein, 0<x<0.1,0.15≤z≤0.4;
Be formed at described 2nd Al
zga
(1-z)grid on N layer, source electrode and drain electrode.
2., as claimed in claim 1 based on the HEMT device of silicon substrate, it is characterized in that, also comprise and be formed at a described Al
xga
(1-x)n layer and the 2nd Al
zga
(1-z)the 3rd Al between N layer
yga
(1-y)n layer, wherein, y<x, 0.07≤x<0.1,0.05≤y<0.1,0.2≤z≤0.3.
3. as claimed in claim 1 based on the HEMT device of silicon substrate, it is characterized in that, described grid embeds described 2nd Al
zga
(1-z)in N layer.
4., as claimed in claim 2 based on the HEMT device of silicon substrate, it is characterized in that, the thickness of described GaN epitaxial layer is 100nm ~ 500nm, a described Al
xga
(1-x)the thickness of N layer is 1 μm ~ 5 μm, described 2nd Al
zga
(1-z)the thickness of N layer is 15nm ~ 40nm, described 3rd Al
yga
(1-y)the thickness of N layer is 100nm ~ 400nm.
5., as claimed in claim 1 based on the HEMT device of silicon substrate, it is characterized in that, also comprise the nucleating layer be formed between described silicon substrate and GaN epitaxial layer, described nucleating layer is AlN layer, and the thickness of described nucleating layer is 80nm ~ 120nm.
6., as claimed in claim 1 based on the HEMT device of silicon substrate, it is characterized in that, also comprise the first resilient coating be formed between described silicon substrate and GaN epitaxial layer, described first resilient coating is multilayer Al
kga
(1-k)n layer, wherein, described multilayer Al
kga
(1-k)the Al component k of N layer successively declines, and/or, described multilayer Al
kga
(1-k)the growth thickness of N layer successively increases.
7., as claimed in claim 1 based on the HEMT device of silicon substrate, it is characterized in that, also comprise and be formed at described GaN epitaxial layer and an Al
xga
(1-x)superlattice layer between N layer, described superlattice layer is the Al in 5 ~ 15 cycles
mga
(1-m)n/GaN layer, wherein, 0.05≤m<1, the thickness of described superlattice layer is 80nm ~ 240nm.
8., as claimed in claim 1 based on the HEMT device of silicon substrate, it is characterized in that, also comprise the second resilient coating, described second resilient coating is AlN layer, and the thickness of described second resilient coating is 2nm ~ 10nm, and described second resilient coating is formed at a described Al
xga
(1-x)n layer and the 3rd Al
yga
(1-y)between N layer, or described second resilient coating is formed at twice and is inserted into a described Al
xga
(1-x)in N layer.
9., as claimed in claim 1 based on the HEMT device of silicon substrate, it is characterized in that, also comprise:
Expose the described Al of part
xga
(1-x)the table top of N layer;
Cover described 2nd Al
zga
(1-z)the Al that N layer and described table top expose
xga
(1-x)first passivation layer of N layer;
Run through described first passivation layer and the 2nd Al
zga
(1-z)the gate openings of N layer;
Run through source contact openings and the drain openings of described first passivation layer.
10., as claimed in claim 9 based on the HEMT device of silicon substrate, it is characterized in that, also comprise:
Be formed at the gate dielectric layer on described first passivation layer and bottom described gate openings;
Be formed at the bottom of described gate openings and the potential barrier barrier layer of sidewall.
11. as claimed in claim 10 based on the HEMT device of silicon substrate, it is characterized in that, described source electrode and drain electrode are Ti/Al/Ti/TiN alloy, Ti/Al/Ni/Au alloy or Ti/Al/Ni/Cu alloy, described grid is Ti/Al/Ti/TiN alloy or Ni/Au/Ni alloy, and described gate dielectric layer is TiN, AlN or Si
3n
4.
12., as claimed in claim 10 based on the HEMT device of silicon substrate, is characterized in that, also comprise:
Cover the second passivation layer of described grid, source electrode, drain electrode and gate dielectric layer;
Run through described second passivation layer to expose the through hole of described grid, source electrode and drain electrode;
The gate pad be electrically connected with described grid, the source pad be electrically connected with described source electrode and with the described drain bonding pad be electrically connected that drains.
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| CN201520849171.1U CN205177852U (en) | 2015-10-29 | 2015-10-29 | HEMT device based on silicon substrate |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206664A (en) * | 2015-10-29 | 2015-12-30 | 杭州士兰微电子股份有限公司 | HEMT device based on silicon substrate and manufacturing method of HEMT device |
| CN106711212A (en) * | 2016-12-31 | 2017-05-24 | 华南理工大学 | Enhanced type HEMT (high electron mobility transistor) device based on AlGaN/GaN (aluminium gallium nitride/ gallium nitride) heterojunction of Si (silicon) substrate and manufacturing method thereof |
| WO2018120363A1 (en) * | 2016-12-31 | 2018-07-05 | 华南理工大学 | Gan-based enhanced hemt device based on si substrate and manufacturing method therefor |
-
2015
- 2015-10-29 CN CN201520849171.1U patent/CN205177852U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206664A (en) * | 2015-10-29 | 2015-12-30 | 杭州士兰微电子股份有限公司 | HEMT device based on silicon substrate and manufacturing method of HEMT device |
| CN105206664B (en) * | 2015-10-29 | 2019-05-07 | 杭州士兰微电子股份有限公司 | HEMT device and its manufacturing method based on silicon substrate |
| CN106711212A (en) * | 2016-12-31 | 2017-05-24 | 华南理工大学 | Enhanced type HEMT (high electron mobility transistor) device based on AlGaN/GaN (aluminium gallium nitride/ gallium nitride) heterojunction of Si (silicon) substrate and manufacturing method thereof |
| WO2018120363A1 (en) * | 2016-12-31 | 2018-07-05 | 华南理工大学 | Gan-based enhanced hemt device based on si substrate and manufacturing method therefor |
| US10580879B2 (en) | 2016-12-31 | 2020-03-03 | South China University Of Technology | Enhancement-mode GaN-based HEMT device on Si substrate and manufacturing method thereof |
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