CN204946904U - Semiconductor substrate - Google Patents
Semiconductor substrate Download PDFInfo
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- CN204946904U CN204946904U CN201520758856.5U CN201520758856U CN204946904U CN 204946904 U CN204946904 U CN 204946904U CN 201520758856 U CN201520758856 U CN 201520758856U CN 204946904 U CN204946904 U CN 204946904U
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Abstract
The utility model provides a kind of Semiconductor substrate, the formation open region, edge in the front of described Semiconductor substrate, so, even if there is size disparity or paster process generation alignment error between Semiconductor substrate and liner, open region around the central area of Semiconductor substrate also can not be influenced, can avoid thinning after there is breach, crack in the edge of Semiconductor substrate, to collapse limit etc. abnormal.
Description
Technical field
The utility model belongs to semiconductor fabrication process technical field, particularly relates to a kind of Semiconductor substrate.
Background technology
Along with the development of semiconductor technology, in order to obtain better parameter and function, the ultrathin of chip thickness is a trend of current particular device.The thinning thickness that chip can be made to reach certain, meets the requirement of scribing, pressure welding and packaging technology, removes oxide layer and the diffusion layer at the back side simultaneously, ensures the good contact at back side during chips welding, reduces contact resistance and ghost effect.Usually, in the devices such as VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor), IGBT (insulated gate bipolar transistor), three dimensional integrated circuits (3DIC) and MEMS (micro electro mechanical system) (MEMS), after front side of silicon wafer completes device architecture, in order to obtain suitable conducting resistance, saturation voltage drop, withstand voltage, all need, after silicon chip back side carries out reduction processing to specific thickness, silicon chip carries out other semiconductor technologies thus forms special device architecture.
But in actual process, time below wafer thinning to 100 μm, silicon chip distortion is very serious, cannot process postchannel process.In order to solve the processing problems of superthin section, basic employing Taiko technique and bonding paster technique.When Taiko technique refers to and carries out grinding to silicon chip, retain the marginal portion (about about 3mm) of silicon chip periphery, only carry out grinding slimming in silicon chip, the carrying risk of slim silicon chip can be reduced with this and reduce warpage.But Taiko process equipment is expensive and do not meet the technology and equipment demand of the engineerings such as conventional lithographic, therefore more employing bonding paster technique.
Bonding paster technique, is referred to and is fitted with liner 10 by special adhesive tape 11 by the silicon chip 12 completing front road technique.In order to ensure the matching of equipment in the postchannel process course of processing, size and dimension and the silicon chip 12 of usual liner 10 are completely the same.When the paster process of liner and silicon chip is completely on time, all edges of liner 10 and silicon chip 12 all overlap, as shown in Figure 1.But due to the alignment error in the size disparity that between silicon chip 10 and liner 12, exists itself and paster process, usually cause liner 10 and silicon chip 12 can not complete matching, as shown in Figure 2.In fig. 2, silicon chip 12 is owing to being greater than substrate 10 to inclined or size, silicon chip 12 exceeds liner 10 and is of a size of a, or silicon chip 12 is owing to being less than substrate 10 to inclined or size, and silicon chip 12 does not cover liner 10 and is of a size of b, after there is both of these case, in the processes process in whole rear road, especially after thinning, be very easy at silicon chip 12 edge occur breach, crack, collapse the limit even exception of fragment.
In order to solve in bonding paster technique silicon chip and liner to inclined and that size is not quite identical problem, the size of liner 10 is normally made to be greater than the size of silicon chip 12, as shown in Figure 3, the diameter of silicon chip 12 is c, the diameter of liner 10 is d, and the diameter d of usual liner 10 needs the diameter c at least 0.5mm being greater than silicon chip 12.But because semiconductor manufacturing facility is all design according to silicon chip specific dimensions, the diameter range error of overwhelming majority equipment is less than 0.5mm, particularly for precision equipment concerning, the error range of die size requires less, once the full-size scope that the size of liner is greater than allowed by equipment cannot be processed.
How while realizing device architecture, make the coupling that wafer thinning technology and equipment reaches best at the thickness reached required for device, reducing breach, crack, collapsing the limit even exception of fragment is those skilled in the art's problem demanding prompt solution.
Utility model content
The purpose of this utility model is to provide a kind of Semiconductor substrate, with the coupling making wafer thinning technology and equipment reach best, reduces breach, crack, collapses the limit even exception of fragment.
For solving the problems of the technologies described above, the utility model provides a kind of Semiconductor substrate, and the front of described Semiconductor substrate is formed with device architecture, the formation open region, edge in the front of described Semiconductor substrate.
Optionally, in described Semiconductor substrate, described open region is an annular groove.
Optionally, in described Semiconductor substrate, the width range of described open region is 1 ~ 5mm, and the depth bounds of described open region is 10 ~ 1000 μm.
Optionally, in described Semiconductor substrate, the device architecture in described front is MOSFET, IGBT, MEMS, 3DIC or BJT.
Compared with prior art, the utility model is in the formation open region, edge in the front of Semiconductor substrate, so, when the consistent size of Semiconductor substrate and liner, the two complete matching, there will not be any exception, even if there is size disparity or paster process generation alignment error between Semiconductor substrate and liner, open region around the central area of Semiconductor substrate also can not be influenced, can avoid thinning after there is breach, crack in the edge of Semiconductor substrate, to collapse limit etc. abnormal.
Accompanying drawing explanation
The schematic diagram that Fig. 1 aims at when being liner and paster consistent with die size in traditional bonding paster technique completely;
To inclined schematic diagram when Fig. 2 is liner but paster consistent with die size in traditional bonding paster technique;
Fig. 3 is schematic diagram when liner size is greater than silicon chip in traditional bonding paster technique;
Fig. 4 is the schematic flow sheet of the Semiconductor substrate thining method of the utility model one embodiment;
Fig. 5 is the structural representation of the Semiconductor substrate of the utility model one embodiment;
Fig. 6 is the structural representation after forming photoresist layer in the utility model one embodiment;
Fig. 7 is the structural representation after forming open region in the utility model one embodiment;
Fig. 8 is the structural representation after forming adhesive layer in the utility model one embodiment;
Fig. 9 be in the utility model one embodiment Semiconductor substrate and liner bond after structural representation;
Figure 10 is the structural representation in the utility model one embodiment after Semiconductor substrate thinning back side;
Figure 11 be in the utility model one embodiment Semiconductor substrate be separated with liner after structural representation.
Embodiment
For enabling above-mentioned purpose of the present utility model, feature and advantage become apparent more, are described in detail embodiment of the present utility model below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the utility model.But the utility model can be much different from alternate manner described here to implement, those skilled in the art can when doing similar popularization without prejudice to when the utility model intension, and therefore the utility model is by the restriction of following public concrete enforcement.
Shown in figure 7, the utility model provides a kind of Semiconductor substrate 100, the front of described Semiconductor substrate 100 is formed with device architecture, and formation open region, the edge 100a in the front of described Semiconductor substrate 100, open region 100a is around the central area 100b of Semiconductor substrate 100.
In the present embodiment, the width of described open region 100a is preferably 1 ~ 5mm.The degree of depth T1 of described open region 100a be greater than or equal to Semiconductor substrate thinning after thickness, the degree of depth T1 of described open region 100a is such as 10 ~ 1000 μm.
Formation and the use procedure of Semiconductor substrate of the present utility model is introduced in detail below in conjunction with Fig. 4 ~ 11.
Shown in Figure 4, the utility model embodiment provides a kind of semiconductor structure thining method, comprises the steps:
S11: semi-conductive substrate is provided, the front of described Semiconductor substrate is formed with device architecture;
S12: in the formation open region, edge in the front of Semiconductor substrate;
S13: the front of Semiconductor substrate and a liner are bonded;
S14: by the thinning back side of Semiconductor substrate, the thickness of thinning rear Semiconductor substrate is less than or equal to the degree of depth of open region;
S15: the Semiconductor substrate after thinning is separated with liner.
Below in conjunction with Fig. 4 to Figure 11, semiconductor structure of the present utility model and thining method thereof are described in further detail.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, aid illustration the utility model embodiment lucidly.
As shown in Figure 5, first, the Semiconductor substrate 100 that completes front road technique is provided.Wherein, described Semiconductor substrate 100 can be silicon substrate, germanium silicon substrate, III-group Ⅴ element compound substrate, also can be well known to a person skilled in the art other semiconductive material substrate.What adopt in the present embodiment is silicon substrate, and described silicon substrate has completed the device architecture in front according to semiconductor process flows, and the back side of this silicon substrate is not yet through reduction process.The device architecture in described front can be the devices such as MOSFET (mos field effect transistor), IGBT (insulated gate bipolar transistor), BJT (bipolar transistor), it is formed by techniques such as photoetching, etching, doping, annealing, metal line, passivation, this content be well known to those skilled in the art, repeats no more herein.
As shown in Figure 6, then, spin processes is carried out to form photoresist layer 110 in its front to the front of Semiconductor substrate 100, and the photoresist layer removing Semiconductor substrate 100 front edge region forms window region 110a.The thickness Ke Youhou road etching selection ratio of described photoresist layer 110 determines, in the present embodiment, the thickness of described photoresist layer 110 is 1 ~ 20 μm.Inventor finds, the width of described window region 110a is larger, this Semiconductor substrate 100 follow-up is more not easy to contact with equipment, more be not easy to occur breach, crack, collapse the limit even exception of fragment, but also consider, window region 110a is not suitable for taking device region, and amid all these factors, the width of window region 110a is preferably 1 ~ 5mm.
In the present embodiment, the photoresist layer being removed described Semiconductor substrate 100 front edge region by side washing technique forms window region 110a, after described side washing (EBR) technique refers to and carries out even glue, the fringe region of corner cleaning fluid to Semiconductor substrate 100 is adopted to process, to remove the photoresist in Semiconductor substrate frontside edge region.In other embodiments of the utility model, also remove the photoresist layer formation window region 110a in described Semiconductor substrate 100 front edge region by exposure and developing process.Concrete, can be adopt edge exposure (WEE) or the reticle of only having Semiconductor substrate edge to open to expose, then develop, the photoresist at Semiconductor substrate edge is removed.
As shown in Figure 7, then, with photoresist layer 110 for mask, dry method or wet etching are carried out to the front of Semiconductor substrate 100, dry method or wet method mode is adopted to remove photoresist layer 110 again, thus at formation open region, the front edge region 100a of Semiconductor substrate 100, open region 100a is around the central area 100b of Semiconductor substrate 100.The width of described open region 100a is preferably 1 ~ 5mm.The degree of depth T1 of described open region 100a be greater than or equal to Semiconductor substrate thinning after thickness, the degree of depth T1 of described open region 100a is such as 10 ~ 1000 μm.
In the present embodiment, open region 100a shown in Fig. 7 is an annular groove actually, that is, when Semiconductor substrate 100 is etched, only a part of thickness that etching gets rid of its fringe region, as long as the thickness of this Semiconductor substrate etched away is less than the semiconductive substrate thickness of follow-up thinning rear reservation, so, even if there is deviation when Subsequent semiconductor substrate 100 and liner paster, also be that the part Semiconductor substrate retained below the 100a of this open region is not covered by liner, thus generation breach, crack, collapse the exceptions such as limit, but extended meeting is thinned after this part Semiconductor substrate, in fact the performance of device architecture is not affected.Need to illustrate at this, the formation of described open region 100a is not limited to the mode of above-mentioned etching, also can adopt the mode such as laser or emery wheel.
As shown in Figure 8, then, the region outside the front openings district 100a of Semiconductor substrate 100 forms adhesive layer 120, and namely described open region 100a does not form adhesive layer 120.In the present embodiment, described adhesive layer 120 is adhesive tape, and thickness is 2 ~ 200 μm.In other embodiments of the utility model, described adhesive layer 120 can also be the jointing materials such as glue, and the utility model is not restricted.
As shown in Figure 9, composition graphs 7, then, the Semiconductor substrate 100 front with adhesive layer 120 is bonded together with liner 200.In preferred version, the center 100b in Semiconductor substrate 100 front is positioned at the center of liner 200, namely, the edge of Semiconductor substrate 100 center 100b is consistent to the edge distance of liner 200, so, when the consistent size of Semiconductor substrate 100 and liner 200 time, Semiconductor substrate 100 and liner 200 complete matching; When the size of Semiconductor substrate 100 and liner 200 is inconsistent, as long as the edge of Semiconductor substrate 100 center 100b is consistent to the edge distance of liner 200, after thinning, Semiconductor substrate 100 will be positioned at the center of liner 200.
As shown in Figure 10, then, by the thinning back side of Semiconductor substrate 100 to predetermined thickness T2, and the course of processing of Semiconductor substrate back side device is carried out.The course of processing of described Semiconductor substrate back side device, referring to needs to carry out the techniques such as photoetching, etching, doping, annealing, evaporation according to device architecture, and this content be well known to those skilled in the art, repeats no more herein.
Corase grind can be adopted to add the mode of fine grinding, by Semiconductor substrate thinning back side to the thickness of device requirement.The thickness T2 of the Semiconductor substrate 100 after thinning is less than or equal to the degree of depth T1 of open region 100a, and in the present embodiment, the thickness range of the Semiconductor substrate 100 after thinning is 10 ~ 100 μm.The distance f at Semiconductor substrate 100 edge after thinning and liner 200 edge is wider, and the possibility that Semiconductor substrate contacts with equipment is less, is more not easy to produce fragment, breach etc. abnormal.
Preferably, when carrying out thinning to the back side of described Semiconductor substrate 100, during apart from described open region 100a preset distance, thinning speed reduces, and be such as that thinning speed reduces by half, this preset distance is such as 5 μm.This is because, at the discontinuous intersection of semiconductive substrate thickness, speed lower effectively can reduce silicon chip edge microscopic nicks, crack and disintegrating slag.
After the thinning back side of Semiconductor substrate 100 to predetermined thickness T2, also can carry out wet etching to the Semiconductor substrate after thinning, this wet etching course effectively can be discharged the stress of thinning, and can effectively improve semiconductor substrate surface roughness.
As shown in figure 11, finally, the Semiconductor substrate 100 after thinning be separated with liner 200, after separation, Semiconductor substrate 100 back side forms required device architecture.The mode that annealing, low-temperature heat or ultraviolet heat can be adopted, separation temperature scope is such as 150 ~ 300 degrees Celsius, adhesive layer 120 is separated voluntarily with liner, then adhesive layer 120 is stripped down from Semiconductor substrate 100, the Semiconductor substrate 100 after thinning can be separated with liner 200.
In sum, the utility model is in the formation open region, edge in the front of Semiconductor substrate, the thickness of the Semiconductor substrate after thinning is less than or equal to the degree of depth of described open region, so, when the consistent size of Semiconductor substrate and liner, the two complete matching, there will not be any exception, even if there is size disparity or paster process generation alignment error between Semiconductor substrate and liner, open region around the central area of Semiconductor substrate also can not be influenced, can avoid thinning after there is breach, crack in the edge of Semiconductor substrate, to collapse limit etc. abnormal.
Semiconductor substrate described in the utility model, be applicable to MOSFET such as VDMOS (vertical double diffused metal-oxide semiconductor field effect transistor), IGBT (insulated gate bipolar transistor), three dimensional integrated circuits (3DIC) field, be also applicable to the fields such as MEMS (micro electro mechanical system) (MEMS).
Although the utility model embodiment with preferred embodiment openly as above; but it is not for limiting claim; any those skilled in the art are not departing from spirit and scope of the present utility model; can make possible variation and amendment, the scope that therefore protection range of the present utility model should define with the utility model claim is as the criterion.
Claims (9)
1. a Semiconductor substrate, the front of described Semiconductor substrate is formed with device architecture, it is characterized in that, the formation open region, edge in the front of described Semiconductor substrate.
2. Semiconductor substrate as claimed in claim 1, it is characterized in that, described open region is an annular groove.
3. Semiconductor substrate as claimed in claim 2, it is characterized in that, the width range of described open region is 1 ~ 5mm.
4. Semiconductor substrate as claimed in claim 2, it is characterized in that, the depth bounds of described open region is 10 ~ 1000 μm.
5. as the Semiconductor substrate in claims 1 to 3 as described in any one, it is characterized in that, the device architecture in described Semiconductor substrate front is MOSFET.
6. as the Semiconductor substrate in claims 1 to 3 as described in any one, it is characterized in that, the device architecture in described Semiconductor substrate front is IGBT.
7. as the Semiconductor substrate in claims 1 to 3 as described in any one, it is characterized in that, the device architecture in described Semiconductor substrate front is MEMS.
8. as the Semiconductor substrate in claims 1 to 3 as described in any one, it is characterized in that, the device architecture in described Semiconductor substrate front is 3DIC.
9. as the Semiconductor substrate in claims 1 to 3 as described in any one, it is characterized in that, the device architecture in described Semiconductor substrate front is BJT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520758856.5U CN204946904U (en) | 2015-09-28 | 2015-09-28 | Semiconductor substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520758856.5U CN204946904U (en) | 2015-09-28 | 2015-09-28 | Semiconductor substrate |
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| Publication Number | Publication Date |
|---|---|
| CN204946904U true CN204946904U (en) | 2016-01-06 |
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| CN201520758856.5U Expired - Fee Related CN204946904U (en) | 2015-09-28 | 2015-09-28 | Semiconductor substrate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161522A (en) * | 2015-09-28 | 2015-12-16 | 杭州士兰集成电路有限公司 | Semiconductor substrate and thinning method |
| CN109786234A (en) * | 2017-11-13 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
-
2015
- 2015-09-28 CN CN201520758856.5U patent/CN204946904U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105161522A (en) * | 2015-09-28 | 2015-12-16 | 杭州士兰集成电路有限公司 | Semiconductor substrate and thinning method |
| CN105161522B (en) * | 2015-09-28 | 2019-03-26 | 杭州士兰集成电路有限公司 | Semiconductor substrate and its thining method |
| CN109786234A (en) * | 2017-11-13 | 2019-05-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
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| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160106 Termination date: 20210928 |
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| CF01 | Termination of patent right due to non-payment of annual fee |