CN103928348B - Separation method for double grids - Google Patents
Separation method for double grids Download PDFInfo
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- CN103928348B CN103928348B CN201410174398.0A CN201410174398A CN103928348B CN 103928348 B CN103928348 B CN 103928348B CN 201410174398 A CN201410174398 A CN 201410174398A CN 103928348 B CN103928348 B CN 103928348B
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- hard mask
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- grid
- fin
- mask layer
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- 238000000926 separation method Methods 0.000 title claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 17
- 230000005669 field effect Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 230000008021 deposition Effects 0.000 claims description 6
- 238000004062 sedimentation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 53
- 238000010586 diagram Methods 0.000 description 16
- 239000011265 semifinished product Substances 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
Abstract
The invention discloses a separation method for double grids. The separation method comprises the steps that a hard mask layer is arranged at the top end of each fin of a fin field-effect transistor; the hard mask layers arranged at the top ends of the fins are removed partly or completely in a selective mode, and a grid layer is formed through sedimentation of grid materials; a photoresistance layer is formed on the upper surface of the grid layer, and grids corresponding to the fins with the hard mask layers reserved are exposed; the grids corresponding to the fins with the hard mask layers are partly etched away through the etching process, the etching process is stopped at the hard mask layers arranged on the top ends of the fins with the hard mask layers reserved, and therefore the heights of the corresponding grids are reduced and the corresponding grids are exposed; remaining portions of the photoresistance layer on the grid layer are removed. According to the separation method for the double grids, the hard mask layers and the photoresistance layer are additionally arranged in an early structure, as a result, etching accuracy can be controlled accurately, the structure is protected against damage, and difficulty of self alignment can be lowered.
Description
Technical field
The invention belongs to technical field of semiconductors, specifically, it is related to a kind of two grid separation method.
Background technology
Fin field-effect transistor (finfield-effecttransistor, abbreviation finfet) is a kind of new complementary
Metal-oxide-semiconductor (MOS) (cmos) transistor.It is (transistor field-effect transistor, the field- of the fet to traditional standard
Effecttransistor, fet) improvement.Fin field-effect transistor finfet can as needed adjusting means threshold value electricity
Pressure, reduces static energy consumption (static powerconsumption) further.
At present, fin field-effect transistor finfet includes three end finfet (3terminal finfet, abbreviation 3t-
Finfet), four end finfet (4terminal finfet, abbreviation 4t-finfet).Fig. 1 is 3t-finfet in prior art
Brief configuration schematic diagram；As shown in figure 1, it includes a source electrode s101, a drain electrode d102, and a grid g103, altogether
Three terminations of meter.In prior art, the schematic equivalent circuit of 3t-finfet is as shown in Figure 2.Fig. 3 is 4t- in prior art
The brief configuration schematic diagram of finfet；As shown in figure 3, it includes a source electrode s201, a drain electrode d202, and a grid
G1203, another one grid g2204,4 terminations altogether.The schematic equivalent circuit of 4t-finfet such as Fig. 4 in prior art
Shown.
Wherein, for 4t-finfet, in order to obtain two grids, prior art provides two kinds of solution technical sides
Case: first kind of way is by fin using cmp (chemical mechanical polishing, abbreviation cmp)
The grid on fin300 top grinds away, the structural representation before and after its grinding, as shown in Figure 5 and Figure 6；The second way is to increase
One light shield 400, the grid etch on fin fin300 top is fallen, the structural representation before and after etching is as shown in Figure 7 and Figure 8.
But, when forming two grids using above-mentioned technique, if there are gap between grid and source/drain region
Words, then during device work, raceway groove cannot turn on, and therefore, needs to be provided with certain overlapping between grid and source/drain region
Covering part.But, if this lap is excessive, so that the parasitic capacitance and gate-drain between gate-source is increased, lead to
The high frequency characteristics of device degenerates.So, in order to enable the device to turn on, and do not cause device high frequency characteristics deteriorate it is necessary to
Ask lap between gate-source or between gate-drain as far as possible little, that is, reach high-precision be aligned, i.e. autoregistration.
But, inventor finds during realizing the present invention, due to etching or grinding, easily causes the damage of structure
Wound, is difficult to accurately ensure overlapping coverage sectors between grid and source/drain region further, therefore, leads to autoregistration degree difficult
To control.
Content of the invention
The technical problem to be solved is to provide a kind of two grid separation method and formula field-effect transistor half to become
Product structure, in order to solve in prior art due to etching or grinding the damage easily causing structure, leads to autoregistration degree difficult
To control.
In order to solve above-mentioned technical problem, the invention provides a kind of two grid separation method, comprising:
On each fin top of fin field-effect transistor, one hard mask layer is set；
Selectively partly or entirely get rid of the hard mask layer of fin top setting, and deposition of gate material forms grid
Layer；
Form a photoresist layer in described grid layer upper surface, and the exposed corresponding grid of fin still retaining hard mask layer；
Fall not getting rid of the corresponding grid of fin of hard mask layer by etching technics partial etching, stop at still to retain and firmly cover
The hard mask layer of the fin top setting of film layer makes corresponding gate height reduce and exposed；
Remove the remaining photoresist layer on described grid layer.
In order to solve above-mentioned technical problem, the invention provides a kind of fin field-effect transistor semi-finished product structure, comprising:
Grid layer；
Hard mask layer, positioned at the fin top of fin field-effect transistor；
Photoresist layer, positioned at described grid layer upper surface.
Preferably, in one embodiment of this invention, the material of described protective layer is sin or sion.
Preferably, in one embodiment of this invention, the material of described photoresist layer is oxide material.
Preferably, in one embodiment of this invention, the thickness of described hard mask layer is not more than 10nm.
Compared with currently existing scheme, in separated grid, due to increased hard mask layer and photoresistance in previous structure
Layer, can accurately control the accuracy of etching, it is to avoid the damage to structure, such that it is able to reduce self aligned difficulty.
Brief description
Fig. 1 is the brief configuration schematic diagram of 3t finfet in prior art；
Fig. 2 is the schematic equivalent circuit of 3t finfet in prior art；
Fig. 3 is the brief configuration schematic diagram of 4t finfet in prior art；
Fig. 4 is the schematic equivalent circuit of 4t finfet in prior art；
Fig. 5 and Fig. 6 is the structural representation before and after transistor grinding in prior art；
Fig. 7 and Fig. 8 is the structural representation before and after transistor etching in prior art；
Fig. 9 is the two grid separation method schematic flow sheet of the embodiment of the present invention one；
Figure 10 is the transistor semi-finished product structure schematic diagram after processing through step s901；
Figure 11 is the transistor semi-finished product structure schematic diagram after processing through step s902；
Figure 12 is the transistor semi-finished product structure schematic diagram after processing through step s903；
Figure 13 is the transistor semi-finished product structure schematic diagram after processing through step s904；
Figure 14 is the transistor semi-finished product structure schematic diagram after processing through step s905；
Figure 15 is the transistor semi-finished product structure schematic diagram after processing through step s906.
Specific embodiment
To describe embodiments of the present invention in detail below in conjunction with schema and embodiment, thereby how the present invention to be applied
Technological means are solving technical problem and to reach realizing process and fully understanding and implement according to this of technology effect.
Fig. 9 is the two grid separation method schematic flow sheet of the embodiment of the present invention one；As shown in figure 9, in the present embodiment
Concrete technical scheme may include that
Step s901, each fin top of fin field-effect transistor arrange a hard mask layer；
Figure 10 is the transistor semi-finished product structure schematic diagram after processing through step s901；As shown in Figure 10, fin 1001 can
It is formed at the upper surface of a buried oxide layer 1000 (buried oxide, abbreviation box).Hard mask layer 1002 is located at fin 1001
Top.In other words carry buried oxide layer box the isolation of wafer it goes without doing shallow trench (shallow trench isolation,
Abbreviation sti).The present embodiment is only taking be buried oxide layer box as a example, it is possible to use body Silicon Wafer.
Step s902, selectively partly or entirely get rid of the hard mask layer of fin top setting, and deposition of gate material
Form grid layer；
In the present embodiment, get rid of the hard mask layer of wherein one fin top setting by photoetching and etching, and remained
The hard mask layer of an other fin top setting.
In the present embodiment, the specific process parameter of photoetching and etching can require flexibly to arrange with concrete technology.
Figure 11 is the transistor semi-finished product structure schematic diagram after processing through step s902；As shown in figure 11, two fins
In 1001, the hard mask layer 1002 of a fin 1001 top setting is removed, and remains the hard of an other fin 1001 top setting
Mask layer 1002.
Step s903, deposition of gate material form grid layer；
In the present embodiment, after step s902, deposition of gate material forms grid layer.
In the present embodiment, grid material can be polysilicon, and specific technique and parameter those of ordinary skill in the art can
Flexibly to be arranged according to technological requirement.
Figure 12 is the transistor semi-finished product structure schematic diagram after processing through step s903；As shown in figure 12, tie in Figure 11
Grid layer 1003 is increased on the basis of structure.
Step s904, form a photoresist layer in described grid layer upper surface, and the exposed fin still retaining hard mask layer corresponds to
Grid；
In the present embodiment, the permissible technical role of photoresist layer: protect a part of grid, by etch another part grid Lai
Form the different grid structure of height.
Specifically photoresist layer can be formed by way of deposition, its concrete technology ginseng can flexibly be arranged according to technological requirement
Number.
Figure 13 is the transistor semi-finished product structure schematic diagram after processing through step s904；As shown in figure 13, described grid
Layer 1003 upper surface forms a photoresist layer 1004.
Step s905, fall not getting rid of the corresponding grid of fin of hard mask layer by etching technics partial etching, stop at
Still retain the hard mask layer of the fin top setting of hard mask layer；.
In the present embodiment, corresponding gate height is made to reduce and exposed.
The technological parameter of etching, in the present embodiment, flexibly can be set according to technological requirement.
Figure 14 is the transistor semi-finished product structure schematic diagram after processing through step s905；As shown in figure 14, no hard mask
The corresponding grid part grid material of fin 1001 of layer 1002 is removed, and meanwhile, the fin 1001 still retaining hard mask layer 1002 pushes up
The hard mask layer 1002 of end setting keeps down, as the reference of etching stopping.
Remaining photoresist layer on step s906, the described grid layer of removal.
In the present embodiment, wet method or dry etching can be passed through, get rid of remaining photoresist layer, its specific technological parameter
Can be: etch away photoresistance with o2plasma.
Figure 15 is the transistor semi-finished product structure schematic diagram after processing through step s906；As shown in figure 15, all of light
Resistance layer 1005 is removed, and forms two different grids of height, thus finally making two grids of transistor separately come.
It should be noted that in the above-described embodiments, the material of described hard mask layer can but be not limited to sin or
sion.The material of described photoresist layer can but be not limited to oxide material.The thickness of described hard mask layer can be not more than
10nm.
Described above illustrate and describes some preferred embodiments of the present invention, but as previously mentioned it should be understood that the present invention
Be not limited to form disclosed herein, be not to be taken as the exclusion to other embodiment, and can be used for various other combinations,
Modification and environment, and can be in invention contemplated scope described herein, by technology or the knowledge of above-mentioned teaching or association area
It is modified.And the change that those skilled in the art are carried out and change without departing from the spirit and scope of the present invention, then all should be at this
In the protection domain of bright claims.
Claims (3)
1. a kind of two grid separation method is it is characterised in that include:
On each fin top of fin field-effect transistor, one hard mask layer is set；
Selectively partly or entirely get rid of the hard mask layer of fin top setting, and deposition of gate material forms grid layer；
Form a photoresist layer in described grid layer upper surface, and the exposed corresponding grid of fin still retaining hard mask layer；
Fall not getting rid of the corresponding grid of fin of hard mask layer by etching technics partial etching, stop at and still retain hard mask layer
The hard mask layer of fin top setting so that corresponding gate height is reduced and exposed；
Remove the remaining photoresist layer on described grid layer.
2. method according to claim 1 is it is characterised in that the material of described hard mask layer is sin or sion.
3. method according to claim 1 is it is characterised in that the material of described photoresist layer is oxide material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410174398.0A CN103928348B (en) | 2014-04-28 | 2014-04-28 | Separation method for double grids |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410174398.0A CN103928348B (en) | 2014-04-28 | 2014-04-28 | Separation method for double grids |
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| Publication Number | Publication Date |
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| CN103928348A CN103928348A (en) | 2014-07-16 |
| CN103928348B true CN103928348B (en) | 2017-01-25 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104409357B (en) * | 2014-11-28 | 2017-03-29 | 上海华力微电子有限公司 | The method for forming fin formula field effect transistor |
| CN104716046A (en) * | 2015-03-16 | 2015-06-17 | 上海华力微电子有限公司 | Method for manufacturing fin field effect transistor (FET) |
| CN105632936B (en) * | 2016-03-22 | 2018-10-16 | 上海华力微电子有限公司 | A kind of preparation method of bigrid fin formula field effect transistor |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7148526B1 (en) * | 2003-01-23 | 2006-12-12 | Advanced Micro Devices, Inc. | Germanium MOSFET devices and methods for making same |
| US7422946B2 (en) * | 2004-09-29 | 2008-09-09 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
| US20070090416A1 (en) * | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
| CN102122645B (en) * | 2010-01-08 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | Integrated circuit structure, manufacturing method and using method thereof |
| US8426283B1 (en) * | 2011-11-10 | 2013-04-23 | United Microelectronics Corp. | Method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate |
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