JP5471064B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP5471064B2
JP5471064B2 JP2009149670A JP2009149670A JP5471064B2 JP 5471064 B2 JP5471064 B2 JP 5471064B2 JP 2009149670 A JP2009149670 A JP 2009149670A JP 2009149670 A JP2009149670 A JP 2009149670A JP 5471064 B2 JP5471064 B2 JP 5471064B2
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玲子 蛭田
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Fuji Electric Co Ltd
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この発明は、半導体装置の製造方法に関し、特にデバイス厚が薄い薄型半導体デバイスを製造する際に用いる半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device used when manufacturing a thin semiconductor device having a small device thickness.

従来、既存のデバイスよりもデバイスの厚さを減じた薄型半導体デバイスの開発が進んでいる。薄型半導体デバイスを製造する際には、たとえば、フィールドストップ型IGBT(絶縁ゲート型バイポーラトランジスタ)の場合、まず、ウエハにおもて面の構造を形成し、さらにアルミニウム−シリコン合金の電極を形成する。つぎに、ウエハ裏面を研削し、さらにエッチングをおこなって、ウエハ厚を所望の厚さとする(薄層化工程)。そして、ウエハを洗浄した後、リン(P)およびボロン(B)をイオン注入し、400℃程度の温度でアニールを行う。その後、ウエハおもて面にポリイミドで保護膜を形成し、ウエハの裏面に裏面電極を形成する。最後に、ウエハをダイシングして、個々のチップを形成する。   Conventionally, development of a thin semiconductor device in which the thickness of the device is reduced as compared with an existing device is progressing. When manufacturing a thin semiconductor device, for example, in the case of a field stop type IGBT (insulated gate bipolar transistor), first, the structure of the front surface is formed on the wafer, and then the electrode of aluminum-silicon alloy is formed. . Next, the wafer back surface is ground and further etched to obtain a desired wafer thickness (thinning step). Then, after cleaning the wafer, ions of phosphorus (P) and boron (B) are implanted, and annealing is performed at a temperature of about 400 ° C. Thereafter, a protective film is formed of polyimide on the front surface of the wafer, and a back electrode is formed on the back surface of the wafer. Finally, the wafer is diced to form individual chips.

上述した製造工程において、薄層化工程後のウエハ厚は、たとえばFZウエハを用いた場合、耐圧1200Vクラスのデバイスで120〜140μm程度、耐圧600Vクラスのデバイスでは60〜100μm程度と非常に薄くなる。このようにウエハの厚さが薄くなると、ウエハの強度が低下してダイシングの際などにひびや割れが生じやすくなり、ウエハの不良率が増加してしまう。   In the above-described manufacturing process, for example, when an FZ wafer is used, the wafer thickness after the thinning process is very thin, about 120 to 140 μm for a device with a withstand voltage of 1200 V class and about 60 to 100 μm with a device with a withstand voltage of 600 V class. . When the wafer thickness is reduced in this way, the strength of the wafer is reduced, and cracks and cracks are likely to occur during dicing, thereby increasing the defect rate of the wafer.

そこで、薄層化したウエハをダイシングする際にウエハが割れるのを防ぐため、紫外線(UV)硬化型接着剤によってウエハと支持基板とを接着して、強度を高めた上でダイシングを行う技術が提案されている(たとえば、特許文献1参照)。また、ダイング時にウエハにひびや割れが生じるのを防止するため、薄層化されていないウエハのおもて面にダイシングラインに沿ってトレンチを形成した後、ウエハの裏面から研削をおこなって個々のチップを形成する技術が提案されている(たとえば、特許文献2参照)。   Therefore, in order to prevent the wafer from cracking when dicing the thinned wafer, there is a technique in which the wafer and the support substrate are bonded with an ultraviolet (UV) curable adhesive to increase the strength and dicing is performed. It has been proposed (see, for example, Patent Document 1). In addition, in order to prevent the wafer from cracking and cracking during dicing, a trench is formed along the dicing line on the front surface of the non-thinned wafer, and then grinding is performed from the back surface of the wafer. There has been proposed a technique for forming the chip (for example, see Patent Document 2).

また、薄層化したウエハは、各種の膜応力の影響を受けて反りやすくなる。ウエハに反りが生じると、その後の製造工程や搬送過程でトラブルの原因となる場合がある。そこで、ウエハの外周を数mm(たとえば2〜5mm)残してウエハ中央部のみを薄層化することによりウエハの反りを防止する技術が知られている。   Further, the thinned wafer is easily warped under the influence of various film stresses. If the wafer is warped, it may cause a trouble in the subsequent manufacturing process and transfer process. Therefore, a technique for preventing the warpage of the wafer is known by thinning only the central portion of the wafer while leaving the outer periphery of the wafer several mm (for example, 2 to 5 mm).

また、同様の技術として、ウエハの両面に酸化膜を形成し、ウエハ裏面の膜を外周端部を残して除去し、残った酸化膜をマスクとしてエッチングしてウエハの中央部のみを薄層化する方法が知られている(たとえば、特許文献3参照)。また、エッチングポットに設けられたシールパッキンでウエハの外周端部をマスクし、ウエハ中央部の露出面をエッチング液にさらすことによって、ウエハの中央部のみを薄層化する方法が知られている(たとえば、特許文献4参照)。   Also, as a similar technique, an oxide film is formed on both sides of the wafer, the film on the backside of the wafer is removed leaving the outer peripheral edge, and the remaining oxide film is used as a mask to make a thin layer only at the center of the wafer. There is a known method (see, for example, Patent Document 3). Also known is a method in which only the central portion of the wafer is thinned by masking the outer peripheral edge of the wafer with a seal packing provided in the etching pot and exposing the exposed surface of the central portion of the wafer to an etching solution. (For example, refer to Patent Document 4).

上述のような製造方法で製造されたウエハにおいて、薄層化されない外周部を「リブ部」という。リブ部の厚さは、デバイス形成部(ウエハ中央部)の厚さにもよるが、たとえば200μm以上であればウエハの反りを防止する効果がある。   In the wafer manufactured by the above-described manufacturing method, the outer peripheral portion that is not thinned is referred to as a “rib portion”. Although the thickness of the rib portion depends on the thickness of the device forming portion (wafer center portion), for example, if it is 200 μm or more, there is an effect of preventing wafer warpage.

しかし、外周部にリブ部が形成されたウエハは、ウエハ中央部とリブ部との間に段差があるため、ダイシング工程においてウエハ裏面にダイシングテープを貼付する際、段差の周辺においてウエハとダイシングテープとの間に隙間が生じてしまう。ウエハとダイシングテープとの間に隙間があると、その隙間にシリコン屑が入ったり、ダイシングテープに貼り付いていない部分に形成されたチップがダイシング時に飛び散ってしまうなどの不具合が生じる。一方、段差の周辺部に無理にダイシングテープを貼付しようとすると、段差の周辺部に形成されたデバイスが破損してしまう恐れがある。   However, since a wafer having ribs formed on the outer periphery has a step between the wafer center and the rib, when the dicing tape is applied to the back surface of the wafer in the dicing process, the wafer and the dicing tape are around the step. There will be a gap between the two. If there is a gap between the wafer and the dicing tape, problems such as silicon scraps entering the gap or chips formed in a portion not attached to the dicing tape scatter during dicing. On the other hand, if the dicing tape is forcibly applied to the periphery of the step, the device formed on the periphery of the step may be damaged.

このような不具合を解消するため、リブ部が形成されたウエハをダイシングする際に、ウエハの中央部(リブ部が形成されていない凹部)とほぼ同サイズのステージを用いてダイシングをおこなう技術が提案されている(たとえば、特許文献5参照)。
特開2004−140101号公報 特開2004−006635号公報 特開2004−253527号公報 特許第3620528号公報 特開2003−332271号公報
In order to solve such problems, when dicing a wafer having a rib portion, there is a technology that performs dicing using a stage that is substantially the same size as the central portion of the wafer (a recess portion where no rib portion is formed). It has been proposed (see, for example, Patent Document 5).
JP 2004-140101 A JP 2004-006635 A JP 2004-253527 A Japanese Patent No. 3620528 JP 2003-332271 A

しかしながら、前記した特許文献5の技術では、ウエハに合わせたステージなどの器具が必要となり、既存のダイシング装置を使用することができない。このため、あらたな設備投資が必要となり、半導体デバイスの生産コストが上昇してしまうという問題点があ
る。
However, the technique of Patent Document 5 described above requires a tool such as a stage that matches the wafer, and an existing dicing apparatus cannot be used. For this reason, there is a problem that a new capital investment is required and the production cost of the semiconductor device is increased.

また、ダイシング工程前にウエハ中央部とリブ部とを分離したり、リブ部の表面を研削してウエハ中央部との段差をなくすなどして、リブ部を除去する方法も考えられる。
しかし、ウエハ中央部とリブ部を分離する場合には、分離工程でウエハ(特に薄いウエハ中央部)が撓んだり、割れたり、反ったりする。ウエハが撓んだり、反ったりすると、ウエハ中央部とリブ部を切り離す切削加工が精度よくできなくなる。
In addition, a method of removing the rib portion by separating the wafer central portion and the rib portion before the dicing process or grinding the surface of the rib portion to eliminate a step from the wafer central portion is also conceivable.
However, when the wafer central portion and the rib portion are separated, the wafer (particularly the thin wafer central portion) is bent, cracked, or warped in the separation process. If the wafer bends or warps, cutting that separates the central portion of the wafer from the rib portion cannot be performed with high accuracy.

この発明の目的は、前記の課題を解決して、リブ部をウエハ中央部から切り離すときのウエハの撓み、割れ、反りおよび切削精度不良を防止できる半導体装置の製造方法を提供することである。   SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor device manufacturing method capable of preventing wafer bending, cracking, warping and cutting accuracy failure when a rib portion is separated from a wafer central portion.

前記の目的を達成するために、特許請求の範囲の請求項1記載の発明によれば、半導体ウエハの第1主面側(裏側)の中央部に凹部を設けてその厚みを外周部よりも薄くし該外周部にリブ部を残す工程と、前記半導体ウエハの中央部の凹部に高分子材料からなるレジスト剤を充填して前記半導体ウエハの中央部の厚みを前記外周部のリブ部の厚みとほぼ同じにするとともに、前記半導体ウエハの第2主面側(表側)に保護用テープを貼付する工程と、前記保護用テープが貼付された前記半導体ウエハの中央部を第2主面側から切断し前記リブ部を前記半導体ウエハの中央部から切り離す工程と、を含んだ半導体装置の製造方法とする。 To achieve the above object, according to the first aspect of the present invention in the claims, the outer peripheral portion of the thickness of that a concave portion is provided in a central portion of the first main surface side of the semiconductor wafer (backside) And reducing the thickness of the central portion of the semiconductor wafer by filling the concave portion of the central portion of the semiconductor wafer with a resist material made of a polymer material. A step of applying a protective tape to the second main surface side (front side) of the semiconductor wafer, and a central portion of the semiconductor wafer having the protective tape applied to the second main surface side. And cutting the rib portion from the central portion of the semiconductor wafer.

特許請求の範囲の請求項2記載の発明によれば、請求項1記載の発明において、前記高分子材料が、アルキレングリコール系ポリマー、セルロース系ポリマー、尿素系ポリマー、メラミン系ポリマー、エポキシ系ポリマーまたはアミド系ポリマーのいずれかであるとよい。   According to the invention of claim 2, the polymer material according to claim 1 is characterized in that the polymer material is an alkylene glycol polymer, a cellulose polymer, a urea polymer, a melamine polymer, an epoxy polymer, or It may be any of amide polymers.

この発明によれば、半導体ウエハの裏面の外周部にリブ部を残して中央部を研削して薄くし、リブ部で囲まれた凹部に高分子材料からなるレジスト剤を埋め込むことで、リブ部をウエハ中央部から切り離すときのウエハの撓み、割れ、反りおよび切削精度不良を防止することができる。   According to the present invention, the rib portion is formed by grinding and thinning the central portion while leaving the rib portion on the outer peripheral portion of the back surface of the semiconductor wafer, and embedding a resist material made of a polymer material in the recess surrounded by the rib portion. Can be prevented from bending, cracking, warping and cutting accuracy failure when the wafer is separated from the wafer center.

この発明の一実施例の半導体装置の要部製造工程断面図である。It is principal part manufacturing process sectional drawing of the semiconductor device of one Example of this invention. 図1に続く、この発明の一実施例の半導体装置の要部製造工程断面図である。FIG. 2 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 1; 図2に続く、この発明の一実施例の半導体装置の要部製造工程断面図である。FIG. 3 is a main-portion manufacturing process cross-sectional view of the semiconductor device of the embodiment of the invention, following FIG. 2; 図3に続く、この発明の一実施例の半導体装置の要部製造工程断面図である。FIG. 4 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the embodiment of the invention, following FIG. 3; 図4に続く、この発明の一実施例の半導体装置の要部製造工程断面図である。FIG. 5 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 4; 図5に続く、この発明の一実施例の半導体装置の要部製造工程断面図である。FIG. 6 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 5; 図6に続く、この発明の一実施例の半導体装置の要部製造工程断面図である。FIG. 7 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 6; 図7に続く、この発明の一実施例の半導体装置の要部製造工程断面図である。FIG. 8 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the embodiment of the invention, following FIG. 7;

実施の形態を以下の実施例で説明する。   Embodiments will be described in the following examples.

図1〜図8は、この発明の一実施例の半導体装置の製造方法を示す工程図であり、工程順に示した要部製造工程断面図である。
半導体ウエハ1の表側の面Aに図示しない所望の素子の表面構造(ベース層、ソース層、ゲート電極など)を形成した後に、その表側の面Aに保護テープ2を貼付ける(図1)。
1 to 8 are process diagrams showing a method of manufacturing a semiconductor device according to one embodiment of the present invention, and are cross-sectional views of main part manufacturing processes shown in the order of processes.
After forming a surface structure (a base layer, a source layer, a gate electrode, etc.) of a desired element (not shown) on the surface A on the front side of the semiconductor wafer 1, a protective tape 2 is attached to the surface A on the front side (FIG. 1).

つぎに、半導体ウエハ1を裏返しにし上になった半導体ウエハの裏側の面Bの外周部に、機械的強度を確保するリブ部4を設けるために、半導体ウエハ1の裏側の面Bの中央部をグラインダー3を用いたグライディング加工で研削し薄くし、裏面の外周部にリブ部4を残す。研削後、エッチング処理してグライディング加工時の加工歪みを除去する。   Next, in order to provide the rib portion 4 for ensuring the mechanical strength on the outer peripheral portion of the backside surface B of the semiconductor wafer which is turned upside down, the central portion of the backside surface B of the semiconductor wafer 1 is provided. Is ground and thinned by a grinding process using a grinder 3, and the rib portion 4 is left on the outer peripheral portion of the back surface. After grinding, an etching process is performed to remove processing distortion during the grinding process.

このリブ部4の幅Tは半導体ウエハ1の外周端から中心に向かって例えば2mm〜5mm程度である。研削後の半導体ウエハ1の中央部(ウエハ中央部)の厚さは50〜150μm、例えば80μmとする。また、リブ部4の厚さは、研削前の半導体ウエハの厚さ(例えば650μm)のままとしておく。   The width T of the rib portion 4 is, for example, about 2 mm to 5 mm from the outer peripheral end of the semiconductor wafer 1 toward the center. The thickness of the central portion (wafer central portion) of the semiconductor wafer 1 after grinding is 50 to 150 μm, for example, 80 μm. Further, the thickness of the rib portion 4 remains the same as that of the semiconductor wafer before grinding (for example, 650 μm).

尚、図中のCは半導体ウエハ1の中央部の薄くなった箇所の裏側の面であり、エッチング処理後の面である(図2)。エッチング処理により、リブ部4も若干薄くなるが、中央部とリブ部には段差(例えば、570μm)が形成される。   Incidentally, C in the figure is the surface on the back side of the thinned portion of the central portion of the semiconductor wafer 1, and is the surface after the etching process (FIG. 2). The rib portion 4 is also slightly thinned by the etching process, but a step (for example, 570 μm) is formed between the central portion and the rib portion.

つぎに、保護テープ2を半導体ウエハ1の表側の面Aから剥離する(図3)。
つぎに、半導体ウエハ1の裏側の面Bに図示しない所望の深さで高濃度の半導体層(ドレイン層やコレクタ層など)を形成しその上に図示しない所望の裏面電極(ドレイン電極やコレクタ電極)を形成する(図4)。
Next, the protective tape 2 is peeled from the surface A on the front side of the semiconductor wafer 1 (FIG. 3).
Next, a high-concentration semiconductor layer (drain layer, collector layer, etc.) is formed at a desired depth (not shown) on the backside surface B of the semiconductor wafer 1, and a desired back electrode (drain electrode or collector electrode) (not shown) is formed thereon. ) Is formed (FIG. 4).

リブ部4により、半導体ウエハ1の外周部分が補強されているので、中央部を薄くしたあとに、上記の裏側の面Bに高濃度の半導体層や裏面電極を形成する工程を行っても、半導体ウエハ1が破損しにくくなる。ここで、前記半導体層を形成する工程は、イオン注入,熱処理などの工程であり、裏面電極を形成する工程は、蒸着,スパッタリング,めっきなどの工程である。   Since the outer peripheral portion of the semiconductor wafer 1 is reinforced by the rib portion 4, even after performing the step of forming a high-concentration semiconductor layer or back electrode on the back side surface B after thinning the central portion, The semiconductor wafer 1 is not easily damaged. Here, the process of forming the semiconductor layer is a process such as ion implantation or heat treatment, and the process of forming the back electrode is a process such as vapor deposition, sputtering, or plating.

つぎに、半導体ウエハ1を再度裏返しにして、上になった半導体ウエハ1の表側の面Aに再度保護テープ5を貼付けし、下になった半導体ウエハ1のリブ部4に囲まれた凹部(裏側の面C)に高分子材料であるポリマー材料からなるレジスト剤6を埋め込む。この高分子材料は、例えば、アルキレングリコール系ポリマー、セルロース系ポリマー、尿素系ポリマー、メラミン系ポリマー、エポキシ系ポリマー、アミド系ポリマーなどである。   Next, the semiconductor wafer 1 is turned upside down again, and the protective tape 5 is applied again to the surface A on the front side of the semiconductor wafer 1 that is on the upper side, and the concave portion ( A resist agent 6 made of a polymer material, which is a polymer material, is embedded in the back surface C). Examples of the polymer material include alkylene glycol polymers, cellulose polymers, urea polymers, melamine polymers, epoxy polymers, amide polymers, and the like.

レジスト剤6は、図示しないディスペンサーなどによって、凹部に滴下される。半導体ウエハ1の中央部を研削した際の凹部の容積をあらかじめ算出し、算出結果に基づいてディスペンサーから所定量のレジスト剤6を供給すればよい。このとき、レジスト剤6の供給量を凹部の容積と同じとしてもよいし、後述するプレベーク,ポストベークの工程で、レジスト剤が収縮する量を見込んで供給してもよい。   The resist agent 6 is dropped into the recess by a dispenser (not shown). The volume of the recess when the central portion of the semiconductor wafer 1 is ground may be calculated in advance, and a predetermined amount of resist agent 6 may be supplied from the dispenser based on the calculation result. At this time, the supply amount of the resist agent 6 may be the same as the volume of the concave portion, or the resist agent 6 may be supplied in anticipation of the shrinkage amount of the resist agent in the pre-bake and post-bake steps described later.

レジスト剤6は硬化前は流動性があるので、凹部に滴下することで凹部内に広がる。常温で数分程度でほぼ平坦になる。
あるいは、図示しないステージに半導体ウエハ1の表側の面Aを固定して、半導体ウエハ1を回転させて、レンジスト剤6を凹部内に塗り広げてもよい。
Since the resist agent 6 has fluidity before curing, the resist agent 6 spreads in the recess when dropped into the recess. It becomes almost flat in a few minutes at room temperature.
Alternatively, the front surface A of the semiconductor wafer 1 may be fixed to a stage (not shown), and the semiconductor wafer 1 may be rotated to spread the range agent 6 in the recess.

なお、レジスト剤6を凹部に塗布して充填するのは後述のように、半導体ウエハを破損させずにリブ部4の切り離しを行うため、半導体ウエハ1の裏側の面Bをある程度平坦にすることにある。したがって、レジスト剤6の塗布時に、レジスト剤6の中に空気を巻き込んで若干の気泡ができたとしても問題はない。   In addition, as described later, the resist agent 6 is applied and filled in the recesses in order to separate the ribs 4 without damaging the semiconductor wafer, so that the surface B on the back side of the semiconductor wafer 1 is flattened to some extent. It is in. Therefore, there is no problem even if air is entrained in the resist agent 6 and some bubbles are formed when the resist agent 6 is applied.

凹部にレジスト剤6を充填することにより、半導体ウエハ中央部における半導体ウエハ1の厚さと充填したレジスト剤6の厚さの合計の厚さを、リブ部4における半導体ウエハ1の厚さとほぼ同じとすることができる。   By filling the recess with the resist agent 6, the total thickness of the semiconductor wafer 1 in the central portion of the semiconductor wafer and the thickness of the filled resist agent 6 is substantially the same as the thickness of the semiconductor wafer 1 in the rib portion 4. can do.

ここで、半導体ウエハ中央部における半導体ウエハ1の厚さと充填したレジスト剤6の厚さの合計の厚さを、リブ部4における半導体ウエハ1の厚さは、同じ厚さであることが望ましい。半導体ウエハ1の裏面側のリブ部4から中央部にかけて連続して平坦であった方が半導体ウエハを破損させずにリブ部4の切り離しやすいためである。   Here, it is desirable that the total thickness of the semiconductor wafer 1 in the central portion of the semiconductor wafer and the thickness of the filled resist agent 6 is the same as the thickness of the semiconductor wafer 1 in the rib portion 4. This is because it is easier to separate the rib portion 4 without damaging the semiconductor wafer when the semiconductor wafer 1 is continuously flat from the rib portion 4 on the back surface side to the center portion.

ただし、レジスト剤6の充填は、半導体ウエハを破損させずにリブ部4を切り離すことが目的であるので、リブ部の切断に支障のない程度の段差があってもよい。例えば、リブ部4における半導体ウエハ1の厚さに対して数%程度レジスト剤6が低くても、あるいは高くても、実用上は問題がない。   However, since the filling of the resist agent 6 is intended to separate the rib portion 4 without damaging the semiconductor wafer, there may be a level difference that does not hinder the cutting of the rib portion. For example, there is no practical problem even if the resist agent 6 is about several percent lower or higher than the thickness of the semiconductor wafer 1 in the rib portion 4.

尚、ここで使用する前記のレジスト剤6は、塗布したのちに、例えばプレベークに80℃〜100℃、10分間加熱したのち、ポストベークに80℃〜160℃、30分間加熱して硬化させる。(図5)。   In addition, after apply | coating the said resist agent 6 used here, for example, after heating at 80 degreeC-100 degreeC for 10 minutes to a prebake, it heats and hardens it at 80 degreeC to 160 degreeC for 30 minutes after a postbake. (FIG. 5).

つぎに、半導体ウエハ1の表側の面Aから保護テープ5を貼付けた状態で半導体ウエハ1の外周部のリブ部4をダイシングライン8に沿ってグラインダー7で半導体ウエハ1の中央部から切り離す。   Next, the rib portion 4 on the outer peripheral portion of the semiconductor wafer 1 is separated from the central portion of the semiconductor wafer 1 by the grinder 7 along the dicing line 8 in a state where the protective tape 5 is adhered from the surface A on the front side of the semiconductor wafer 1.

前記凹部内は、硬化したレジスト剤6で充填されているため、リブ部4の高さでほぼ平坦化されている。よって、図6に示すように、半導体ウエハ1の表側の面Aを上側に図示しないステージに載置しても、半導体ウエハ1が撓んだりせず、グラインダー7での切断が可能となる。   Since the inside of the concave portion is filled with the hardened resist agent 6, it is almost flattened at the height of the rib portion 4. Therefore, as shown in FIG. 6, even when the front surface A of the semiconductor wafer 1 is placed on a stage (not shown), the semiconductor wafer 1 is not bent and can be cut by the grinder 7.

リブ部4を切り離した後の半導体ウエハ1の中央部は薄い半導体ウエハ1aになる(図6)。
つぎに、保護テープ5を貼った状態のまま裏側の面Cに接着したレジスト剤6を例えば硫酸/過酸化水素水などによるウエットエッチングにより除去し、その後半導体ウエハ1aを超純水などで洗浄して乾燥させる(図7)。表側の面には保護テープ5が貼られているので、裏側の面をウエットエッチングしても、表側の面の保護層(図示せず)などは保護されている。
The central portion of the semiconductor wafer 1 after cutting the rib portion 4 becomes a thin semiconductor wafer 1a (FIG. 6).
Next, the resist agent 6 adhered to the back surface C with the protective tape 5 applied is removed by wet etching using, for example, sulfuric acid / hydrogen peroxide solution, and then the semiconductor wafer 1a is washed with ultrapure water or the like. And dry (FIG. 7). Since the protective tape 5 is attached to the front side surface, even if the back side surface is wet-etched, the protective layer (not shown) on the front side surface is protected.

つぎに、薄い半導体ウエハ1aの裏側の面Cをダイシングリング10に固定されたダイシングテープ9に貼付け、保護テープ5を剥離したのちに半導体ウエハ1aの表側の面Aから半導体ウエハ1aをダイシングライン11に沿って切断して半導体チップ12にする(図8)。   Next, the back surface C of the thin semiconductor wafer 1a is affixed to a dicing tape 9 fixed to the dicing ring 10, and after the protective tape 5 is peeled off, the semiconductor wafer 1a is separated from the front surface A of the semiconductor wafer 1a by the dicing line 11. Is cut into a semiconductor chip 12 (FIG. 8).

つぎに、ダイシングテープ9から半導体チップ12(半導体素子)を取り出し、この半導体チップ12をパッケージして半導体装置が完成する。
この発明では、半導体ウエハの第2主面に保護テープ5を貼付し、リブ部4の内側の半導体ウエハ1の凹部をポリマー(高分子材料)からなるレジスト剤6を充填し、保護テープを貼付した第2主面側から半導体ウェハを切断することで、リブ部をウエハ中央部から切り離すときの半導体ウエハ1の撓み、割れ、反りおよび切削精度不良を防止することができる。
Next, the semiconductor chip 12 (semiconductor element) is taken out from the dicing tape 9, and the semiconductor chip 12 is packaged to complete the semiconductor device.
In this invention, the protective tape 5 is applied to the second main surface of the semiconductor wafer, the concave portion of the semiconductor wafer 1 inside the rib portion 4 is filled with a resist agent 6 made of a polymer (polymer material) , and the protective tape is applied. By cutting the semiconductor wafer from the second main surface side, it is possible to prevent the semiconductor wafer 1 from being bent, cracked, warped and poor in cutting accuracy when the rib portion is separated from the wafer central portion.

1 半導体ウエハ
1a 半導体ウエハ(薄い)
2 保護テープ
3、7 グラインダー
4 リブ部
5 保護テープ
6 レジスト剤
8、11 ダイシングライン
9 ダイシングテープ
10 ダイシングリング
12 半導体チップ
1 Semiconductor wafer 1a Semiconductor wafer (thin)
2 Protective tape 3, 7 Grinder 4 Rib 5 Protective tape 6 Resist agent 8, 11 Dicing line 9 Dicing tape 10 Dicing ring 12 Semiconductor chip

Claims (2)

半導体ウエハの第1主面側の中央部に凹部を設けてその厚みを外周部よりも薄くし該外周部にリブ部を残す工程と、
前記半導体ウエハの中央部の凹部に高分子材料からなるレジスト剤を充填して前記半導体ウエハの中央部における、半導体ウエハの厚さと前記充填したレジスト剤の厚さの合計の厚さを前記外周部のリブ部の厚さとほぼ同じにするとともに、前記半導体ウエハの第2主面側に保護用テープを貼付する工程と、
前記保護用テープが貼付された前記半導体ウエハの中央部を第2主面側から切断し前記リブ部を前記半導体ウエハの中央部から切り離す工程と、
を含んだことを特徴とする半導体装置の製造方法。
A step of leaving a rib portion on the outer peripheral portion is thinner than the outer peripheral portion of the thickness of that a concave portion is provided in a central portion of the first main surface side of the semiconductor wafer,
Wherein the recess of the central portion of the semiconductor wafer at the center of the filled resist agent comprising a polymeric material the semiconductor wafer, the thickness of said filled the thickness the total thickness of the outer peripheral portion of the resist material of the semiconductor wafer A step of applying a protective tape to the second main surface side of the semiconductor wafer;
Cutting the central part of the semiconductor wafer to which the protective tape is attached from the second main surface side, and cutting the rib part from the central part of the semiconductor wafer;
A method for manufacturing a semiconductor device, comprising:
前記高分子材料が、アルキレングリコール系ポリマー、セルロース系ポリマー、尿素系ポリマー、メラミン系ポリマー、エポキシ系ポリマーまたはアミド系ポリマーのいずれかであることを特徴とする請求項1に記載の半導体装置の製造方法。   The semiconductor device according to claim 1, wherein the polymer material is any one of an alkylene glycol polymer, a cellulose polymer, a urea polymer, a melamine polymer, an epoxy polymer, or an amide polymer. Method.
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