CN104658907A - Manufacturing method of reverse-blocking insulated gate bipolar transistor - Google Patents
Manufacturing method of reverse-blocking insulated gate bipolar transistor Download PDFInfo
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- CN104658907A CN104658907A CN201310590102.9A CN201310590102A CN104658907A CN 104658907 A CN104658907 A CN 104658907A CN 201310590102 A CN201310590102 A CN 201310590102A CN 104658907 A CN104658907 A CN 104658907A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 152
- 238000000034 method Methods 0.000 claims abstract description 59
- 238000002955 isolation Methods 0.000 claims description 116
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
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- 238000011946 reduction process Methods 0.000 claims description 19
- 239000012634 fragment Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract 4
- 238000010586 diagram Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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Abstract
The invention discloses a manufacturing method of a reverse-blocking insulated gate bipolar transistor. In the process of manufacturing the reverse-blocking insulated gate bipolar transistor, a first semiconductor substrate and a second semiconductor substrate are bonded together by adopting a bonding process, so that the mechanical strengths of the bonded semiconductor substrates are improved, the probability of fragments of the bonded semiconductor substrates in the manufacturing process is reduced, and the yield is improved.
Description
Technical field
The present invention relates to technical field of semiconductor device, more particularly, relate to a kind of manufacture method of inverse-impedance type insulated gate bipolar transistor.
Background technology
RB-IGBT(Reverse Blocking-Insulated Gate Bipolar Transistor, inverse-impedance type insulated gate bipolar transistor) be a kind of Novel power semiconductor with reverse blocking capability, it is forward and reverse all can bear voltage.Common IGBT(insulated gate bipolar transistor) switch of forward can only be made, if make IGBT simultaneously as reverser, need to connect a blocking diode in collector electrode or emitter circuit.And namely RB-IGBT is equivalent to common IGBT has connected in collector loop a blocking diode, therefore RB-IGBT as bidirectional switch and common IGBT integrated independently compared with diode chip for backlight unit, it is little that RB-IGBT semiconductor device not only accounts for plate area, cost is low, and pressure drop is low, on-state loss is little.
The method of existing making RB-IGBT is: the Facad structure first making silicon chip, then by after the thinning back side of silicon chip, form structure and multiple isolation channel figure at silicon chip back side, and V-shaped groove etching is carried out to isolation channel figure, until each chip is separated.Adopt existing manufacture method, after silicon chip back side is thinning, reduce the mechanical strength of silicon chip, in making structure and V-shaped groove etching process, very easily fragment occurs, cause rate of finished products low.
Summary of the invention
In view of this, the invention provides a kind of manufacture method of inverse-impedance type insulated gate bipolar transistor, making the probability reducing fragment in RB-IGBT process, improve rate of finished products.
For achieving the above object, the invention provides following technical scheme:
A manufacture method for inverse-impedance type insulated gate bipolar transistor, comprising:
S1, the first semiconductor chip providing the first conduction type to adulterate, the back side of described first semiconductor chip is formed with the second conduction type and mixes layer and multiple first isolation channel;
S2, provide the second semiconductor chip of the second conduction type doping, and adopt bonding technology by the back side bonding of the front of described second semiconductor chip and described first semiconductor chip;
S3, adopt surperficial reduction process by thinning for the front of described first semiconductor chip, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region;
S4, form Facad structure in the front of described first semiconductor chip, and form scribing after structure at the back side of described second semiconductor chip and obtain multiple inverse-impedance type insulated gate bipolar transistor.
Preferably, described first isolation channel is V-arrangement isolation channel or U-shaped isolation channel.
Preferably, described bonding technology is SDB bonding technology, field causes bonding technology or low-temperature bonding technique.
Preferably, described step S3 is specially:
Adopt surperficial reduction process by thinning for the front of described first semiconductor chip, until expose described second conduction type doped layer or until expose described first isolation channel, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
Preferably, described step S3 is specially:
Adopt surperficial reduction process by thinning for the front of described first semiconductor chip;
Multiple second isolation channel is formed in the front of described first semiconductor chip, and described second isolation channel and the first isolation channel one_to_one corresponding, second conduction type doping is carried out to described second isolation channel, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
Preferably, described second isolation channel is V-arrangement isolation channel or U-shaped isolation channel.
Preferably, multiple second isolation channel is formed in the front of described first semiconductor chip, and described second isolation channel and the first isolation channel one_to_one corresponding, second conduction type doping is carried out to described second isolation channel, until the second conduction type doped region of described second isolation channel is communicated with described second conduction type doped layer, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region; Or,
Multiple second isolation channel is formed in the front of described first semiconductor chip, and described second isolation channel and the first isolation channel one_to_one corresponding, the bottom land of described second isolation channel is communicated with the bottom land of described first isolation channel, second conduction type doping is carried out to described second isolation channel, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
Preferably, described step S3 is specially:
Adopt surperficial reduction process by thinning for the front of described first semiconductor chip;
Second conduction type doping is carried out to the region of the bottom land of described first isolation channel corresponding to the front of described first semiconductor chip, until be communicated with described second conduction type doped layer, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
Preferably, described step S4 specifically comprises:
Facad structure is formed in the front of described first semiconductor chip, and adopt surperficial reduction process by the thinning back side of described second semiconductor chip, and scribing obtains multiple inverse-impedance type insulated gate bipolar transistor after the back side of described second semiconductor chip forms structure.
Preferably, described first semiconductor chip is the silicon chip of the first conduction type doping, and described second semiconductor chip is the silicon chip of the second conduction type doping.
Preferably, described first conduction type is N-type, and described second conduction type is P type; Or described first conduction type is P type, described second conduction type is N-type.
Compared with prior art, technical scheme provided by the present invention has the following advantages:
The manufacture method of inverse-impedance type insulated gate bipolar transistor provided by the present invention, in the process making inverse-impedance type insulated gate bipolar transistor, together with first semiconductor chip is bonded to the second semiconductor chip by employing bonding technology, improve the mechanical strength of the semiconductor chip after bonding, reduce the probability of the fragment in manufacturing process of the semiconductor chip after bonding, and then improve rate of finished products.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The manufacture method flow chart of a kind of inverse-impedance type insulated gate bipolar transistor that Fig. 1 provides for the embodiment of the present application;
The manufacture method flow chart of a kind of concrete inverse-impedance type insulated gate bipolar transistor that Fig. 2 a provides for the embodiment of the present application;
The structure flow chart of the method flow diagram that Fig. 2 b provides for corresponding diagram 2a;
The manufacture method flow chart of the inverse-impedance type insulated gate bipolar transistor that the another kind that Fig. 3 a provides for the embodiment of the present application is concrete;
The structure flow chart of the method flow diagram that Fig. 3 b provides for corresponding diagram 3a;
The manufacture method flow chart of another concrete inverse-impedance type insulated gate bipolar transistor that Fig. 4 a provides for the embodiment of the present application;
The structure flow chart of the method flow diagram that Fig. 4 b provides for corresponding diagram 4a.
Embodiment
As described in background, adopt existing manufacture method, after silicon chip back side is thinning, reduce the mechanical strength of silicon chip, in making structure and V-shaped groove etching process, very easily fragment occurs, cause rate of finished products low.
Based on this, the invention provides a kind of manufacture method of inverse-impedance type insulated gate bipolar transistor, to overcome the problems referred to above that prior art exists, comprising:
S1, the first semiconductor chip providing the first conduction type to adulterate, the back side of described first semiconductor chip is formed with the second conduction type and mixes layer and multiple first isolation channel;
S2, provide the second semiconductor chip of the second conduction type doping, and adopt bonding technology by the back side bonding of the front of described second semiconductor chip and described first semiconductor chip;
S3, adopt surperficial reduction process by thinning for the front of described first semiconductor chip, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region;
S4, form Facad structure in the front of described first semiconductor chip, and form scribing after structure at the back side of described second semiconductor chip and obtain multiple inverse-impedance type insulated gate bipolar transistor.
The manufacture method of inverse-impedance type insulated gate bipolar transistor provided by the invention, in the process making inverse-impedance type insulated gate bipolar transistor, together with first semiconductor chip is bonded to the second semiconductor chip by employing bonding technology, improve the mechanical strength of the semiconductor chip after bonding, reduce the probability of the fragment in manufacturing process of the semiconductor chip after bonding, and then improve rate of finished products.
Be more than core concept of the present invention, for enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Present embodiments provide a kind of manufacture method of inverse-impedance type insulated gate bipolar transistor, as shown in Figure 1, be the flow chart of a kind of RB-IGBG manufacture method that the embodiment of the present application provides, comprise step:
S1, the first semiconductor chip providing the first conduction type to adulterate, the back side of described first semiconductor chip is formed with the second conduction type and mixes layer and multiple first isolation channel.
First the first semiconductor chip of one first conduction type doping is got, in backside coating photoresist and the design etched area of the first semiconductor chip, etched area and multiple first isolation channel region, then etch the first isolation channel by wet-etching technology or dry etch process, remove photoresist when etching into the thickness of needs, thus form multiple first isolation channel.First isolation channel can be wet-etching technology formed V-shaped groove, or for dry etch process formation U-lag.
Then carry out the second conduction type doping formation second conduction type doped layer by ion implantation technology or thermal diffusion process at the back side of the first semiconductor chip, namely the final back side of must arriving is formed with the first semiconductor chip that the second conduction type mixes layer and multiple first isolation channel.In the embodiment of the present application, the first semiconductor chip is the silicon chip of the first conduction type doping, and the first conduction type is N-type or P type.
It should be noted that, there is provided the doping content of the first conduction type of the first semiconductor chip in the embodiment of the present application, the second conduction type doping at the degree of depth of multiple first isolation channels at the first semiconductor chip back side and the first semiconductor chip back side densely all to need according to actual needs and subsequent manufacturing processes designs, the application does not specifically limit it.
S2, provide the second semiconductor chip of the second conduction type doping, and adopt bonding technology by the back side bonding of the front of described second semiconductor chip and described first semiconductor chip.
Get the second semiconductor chip of the second conduction type doping, adopt bonding technology by the back side bonding of the front of the second semiconductor chip and described first semiconductor chip, and then increase the thickness of the semiconductor chip after bonding, second semiconductor chip is that the first semiconductor chip provides a supporting role, and indirectly improves the mechanical strength of the first semiconductor chip.
The preferred bonding technology of the present embodiment is SDB(Silicon Wafer Direct Bonding, Si V groove) bonding technology, field cause bonding technology or low-temperature bonding technique.
In the embodiment of the present application, the second semiconductor chip is the silicon chip of the second conduction type doping, and the second conduction type is contrary with the first conduction type, and namely the first conduction type is N-type, and the second conduction type is P type; Or the first conduction type is P type, the second conduction type is N-type.
S3, adopt surperficial reduction process by thinning for the front of described first semiconductor chip, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
S4, form Facad structure in the front of described first semiconductor chip, and form scribing after structure at the back side of described second semiconductor chip and obtain multiple inverse-impedance type insulated gate bipolar transistor.
Facad structure is formed in the front of described first semiconductor chip, and adopt surperficial reduction process by the thinning back side of described second semiconductor chip, and scribing obtains multiple inverse-impedance type insulated gate bipolar transistor after the back side of described second semiconductor chip forms structure.Thickness for thinning back side does not do concrete restriction, needs to carry out according to actual needs calculating and emulating.
The manufacture method of the inverse-impedance type insulated gate bipolar transistor that the embodiment of the present application provides, in the process making inverse-impedance type insulated gate bipolar transistor, together with first semiconductor chip is bonded to the second semiconductor chip by employing bonding technology, improve the mechanical strength of the semiconductor chip after bonding, reduce the probability of the fragment in manufacturing process of the semiconductor chip after bonding, and then improve rate of finished products.
Below the manufacture method of a kind of inverse-impedance type insulated gate bipolar transistor that above-mentioned the embodiment of the present application provides is specifically described, to in the description of the manufacture method of concrete inverse-impedance type insulated gate bipolar transistor below it should be noted that, with the first conduction type for N-type, second conduction type is P type is that example is specifically described, certainly, in following description, the first conduction type also can be P type, and the second conduction type is N-type.
The embodiment of the present application provides a kind of manufacture method of concrete inverse-impedance type insulated gate bipolar transistor, shown in composition graphs 2a and Fig. 2 b, the manufacture method flow chart of a kind of concrete inverse-impedance type insulated gate bipolar transistor that Fig. 2 a provides for the embodiment of the present application, the structure flow chart of the manufacture method that Fig. 2 b provides for corresponding diagram 2a, the structure one_to_one corresponding in the step of Fig. 2 a and Fig. 2 b.
The manufacture method of the inverse-impedance type insulated gate bipolar transistor that the embodiment of the present application provides comprises step:
S1, the first semiconductor chip 1 providing the first conduction type to adulterate, the back side of described first semiconductor chip 1 is formed with the second conduction type and mixes layer 11 and multiple first isolation channel 12.
Shown in figure 2b, the first isolation channel is V-shaped groove.First isolation channel can be also U-lag, and relative to the V-shaped groove that the embodiment of the present application provides, U-lag relatively reduces the width of isolation channel, and then improves the utilance of the first semiconductor chip, reduces costs.
S2, provide the second semiconductor chip of the second conduction type doping, and adopt bonding technology by the back side bonding of the front of described second semiconductor chip and described first semiconductor chip.
S3, adopt surperficial reduction process by thinning for the front of described first semiconductor chip 1, until expose described second conduction type doped layer 11 or until expose described first isolation channel 12, between the front of described first isolation channel 12 to described first semiconductor chip 1, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
By thinning for the front of the first silicon chip, until just expose P type doped layer, make to form P type doped region between the front of V-shaped groove to the first silicon chip, P type doped region surrounding n-type doped region;
Or, by thinning for the front of the first silicon chip, until expose the bottom land (with reference to the structure chart that figure 3b is corresponding, just drawing the structure chart of the bottom land exposing V-shaped groove) of V-shaped groove.
S4, the front of described first semiconductor chip 1 formed Facad structure, and adopt surperficial reduction process by the thinning back side of described second semiconductor chip 2, and scribing obtains multiple inverse-impedance type insulated gate bipolar transistor after the back side of described second semiconductor chip 2 forms structure.
After the thinning back side of the second silicon chip, make structure at the back side of the second silicon chip, then along dicing lane scribing, obtain multiple inverse-impedance type insulated gate bipolar transistor.
The embodiment of the present application additionally provides a kind of manufacture method of concrete inverse-impedance type insulated gate bipolar transistor, shown in composition graphs 3a and Fig. 3 b, the manufacture method flow chart of the inverse-impedance type insulated gate bipolar transistor that the another kind that Fig. 3 a provides for the embodiment of the present application is concrete, the structure flow chart of the manufacture method that Fig. 3 b provides for corresponding diagram 3a, the structure one_to_one corresponding in the step of Fig. 3 a and Fig. 3 b.
The manufacture method of the inverse-impedance type insulated gate bipolar transistor that the embodiment of the present application provides comprises step:
S1, the first semiconductor chip 1 providing the first conduction type to adulterate, the back side of described first semiconductor chip 1 is formed with the second conduction type and mixes layer 11 and multiple first isolation channel 12.
Shown in figure 3b, the first isolation channel is U-lag.Same, the first isolation channel can be also V-shaped groove, and relative to V-shaped groove, the U-lag that the embodiment of the present application provides relatively reduces the width of isolation channel, and then improves the utilance of the first semiconductor chip, reduces costs.
S2, provide the second semiconductor chip of the second conduction type doping, and adopt bonding technology by the back side bonding of the front of described second semiconductor chip and described first semiconductor chip.
S3, adopt surperficial reduction process by thinning for the front of described first semiconductor chip 1; Multiple second isolation channel 13 is formed in the front of described first semiconductor chip 1, and described second isolation channel 13 and the first isolation channel 12 one_to_one corresponding, second conduction type doping is carried out to described second isolation channel 13, between the front of described first isolation channel 12 to described first semiconductor chip 1, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
Shown in figure 3b, the second isolation channel that the embodiment of the present application provides is U-lag, and it should be noted that the second isolation channel can be also V-shaped groove, the present embodiment does not do concrete restriction.
Concrete, two kinds are had for the mode of formation second conduction type doped region in the present embodiment, one is: form multiple second isolation channel in the front of described first semiconductor chip, and described second isolation channel and the first isolation channel one_to_one corresponding, second conduction type doping is carried out to described second isolation channel, until the second conduction type doped region of described second isolation channel is communicated with described second conduction type doped layer, the second conduction type doped region is formed between the front of described first isolation channel to described first semiconductor chip, described second conduction type doped region surrounds the first conduction type doped region.
Or, another kind is: form multiple second isolation channel in the front of described first semiconductor chip, and described second isolation channel and the first isolation channel one_to_one corresponding, the bottom land of described second isolation channel is communicated with the bottom land of described first isolation channel, second conduction type doping is carried out to described second isolation channel, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
The mode of above-mentioned two kinds of formation second conduction type doped regions in the present embodiment, the first isolation channel can be made to be communicated with the bottom land of the second isolation channel, also the first isolation channel can be made not to be communicated with the bottom land of the second isolation channel, no matter any mode, as long as the second conduction type doped region in the first isolation channel region is communicated with the second conduction type doped region in the second isolation channel region.
In manufacturing process, by the bottom land accurate contraposition of the first isolation channel and the second isolation channel, the utilance of the first semiconductor chip can be improved.
S4, the front of described first semiconductor chip 1 formed Facad structure, and adopt surperficial reduction process by the thinning back side of described second semiconductor chip 2, and scribing obtains multiple inverse-impedance type insulated gate bipolar transistor after the back side of described second semiconductor chip 2 forms structure.
After the thinning back side of the second silicon chip, make structure at the back side of the second silicon chip, then along dicing lane scribing, obtain multiple inverse-impedance type insulated gate bipolar transistor.
The embodiment of the present application additionally provides a kind of manufacture method of concrete inverse-impedance type insulated gate bipolar transistor, shown in composition graphs 4a and Fig. 4 b, the manufacture method flow chart of another concrete inverse-impedance type insulated gate bipolar transistor that Fig. 4 a provides for the embodiment of the present application, the structure flow chart of the manufacture method that Fig. 4 b provides for corresponding diagram 4a, the structure one_to_one corresponding in the step of Fig. 4 a and Fig. 4 b.
The manufacture method of the inverse-impedance type insulated gate bipolar transistor that the embodiment of the present application provides comprises step:
S1, the first semiconductor chip 1 providing the first conduction type to adulterate, the back side of described first semiconductor chip 1 is formed with the second conduction type and mixes layer 11 and multiple first isolation channel 12.
Shown in figure 4b, the first isolation channel is V-shaped groove.First isolation channel can be also U-lag, and relative to the V-shaped groove that the embodiment of the present application provides, U-lag relatively reduces the width of isolation channel, and then improves the utilance of the first semiconductor chip, reduces costs.
S2, provide the second semiconductor chip of the second conduction type doping, and adopt bonding technology by the back side bonding of the front of described second semiconductor chip and described first semiconductor chip.
S3, adopt surperficial reduction process by thinning for the front of described first semiconductor chip 1; Second conduction type doping is carried out to the region of the bottom land of described first isolation channel 12 corresponding to the front of described first semiconductor chip 1, until be communicated with described second conduction type doped layer, between the front of described first isolation channel 12 to described first semiconductor chip 1, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
S4, the front of described first semiconductor chip 1 formed Facad structure, and adopt surperficial reduction process by the thinning back side of described second semiconductor chip 2, and scribing obtains multiple inverse-impedance type insulated gate bipolar transistor after the back side of described second semiconductor chip 2 forms structure.
In all embodiments that the application provides, in the process making inverse-impedance type insulated gate bipolar transistor, together with first semiconductor chip is bonded to the second semiconductor chip by employing bonding technology, improve the mechanical strength of the semiconductor chip after bonding, reduce the probability of the fragment in manufacturing process of the semiconductor chip after bonding, and then improve rate of finished products.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (11)
1. a manufacture method for inverse-impedance type insulated gate bipolar transistor, is characterized in that, comprising:
S1, the first semiconductor chip providing the first conduction type to adulterate, the back side of described first semiconductor chip is formed with the second conduction type and mixes layer and multiple first isolation channel;
S2, provide the second semiconductor chip of the second conduction type doping, and adopt bonding technology by the back side bonding of the front of described second semiconductor chip and described first semiconductor chip;
S3, adopt surperficial reduction process by thinning for the front of described first semiconductor chip, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region;
S4, form Facad structure in the front of described first semiconductor chip, and form scribing after structure at the back side of described second semiconductor chip and obtain multiple inverse-impedance type insulated gate bipolar transistor.
2. the manufacture method of inverse-impedance type insulated gate bipolar transistor according to claim 1, is characterized in that, described first isolation channel is V-arrangement isolation channel or U-shaped isolation channel.
3. the manufacture method of inverse-impedance type insulated gate bipolar transistor according to claim 1, is characterized in that, described bonding technology is SDB bonding technology, field causes bonding technology or low-temperature bonding technique.
4. the manufacture method of inverse-impedance type insulated gate bipolar transistor according to claim 1, is characterized in that, described step S3 is specially:
Adopt surperficial reduction process by thinning for the front of described first semiconductor chip, until expose described second conduction type doped layer or until expose described first isolation channel, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
5. the manufacture method of inverse-impedance type insulated gate bipolar transistor according to claim 1, is characterized in that, described step S3 is specially:
Adopt surperficial reduction process by thinning for the front of described first semiconductor chip;
Multiple second isolation channel is formed in the front of described first semiconductor chip, and described second isolation channel and the first isolation channel one_to_one corresponding, second conduction type doping is carried out to described second isolation channel, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
6. the manufacture method of inverse-impedance type insulated gate bipolar transistor according to claim 5, is characterized in that, described second isolation channel is V-arrangement isolation channel or U-shaped isolation channel.
7. the manufacture method of inverse-impedance type insulated gate bipolar transistor according to claim 5, it is characterized in that, multiple second isolation channel is formed in the front of described first semiconductor chip, and described second isolation channel and the first isolation channel one_to_one corresponding, second conduction type doping is carried out to described second isolation channel, until the second conduction type doped region of described second isolation channel is communicated with described second conduction type doped layer, the second conduction type doped region is formed between the front of described first isolation channel to described first semiconductor chip, described second conduction type doped region surrounds the first conduction type doped region, or,
Multiple second isolation channel is formed in the front of described first semiconductor chip, and described second isolation channel and the first isolation channel one_to_one corresponding, the bottom land of described second isolation channel is communicated with the bottom land of described first isolation channel, second conduction type doping is carried out to described second isolation channel, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
8. the manufacture method of inverse-impedance type insulated gate bipolar transistor according to claim 1, is characterized in that, described step S3 is specially:
Adopt surperficial reduction process by thinning for the front of described first semiconductor chip;
Second conduction type doping is carried out to the region of the bottom land of described first isolation channel corresponding to the front of described first semiconductor chip, until be communicated with described second conduction type doped layer, between the front of described first isolation channel to described first semiconductor chip, form the second conduction type doped region, described second conduction type doped region surrounds the first conduction type doped region.
9. the manufacture method of inverse-impedance type insulated gate bipolar transistor according to claim 1, is characterized in that, described step S4 specifically comprises:
Facad structure is formed in the front of described first semiconductor chip, and adopt surperficial reduction process by the thinning back side of described second semiconductor chip, and scribing obtains multiple inverse-impedance type insulated gate bipolar transistor after the back side of described second semiconductor chip forms structure.
10. the manufacture method of the inverse-impedance type insulated gate bipolar transistor according to claim 1 ~ 9 any one, it is characterized in that, described first semiconductor chip is the silicon chip of the first conduction type doping, and described second semiconductor chip is the silicon chip of the second conduction type doping.
The manufacture method of 11. inverse-impedance type insulated gate bipolar transistors according to claim 1 ~ 9 any one, it is characterized in that, described first conduction type is N-type, and described second conduction type is P type; Or described first conduction type is P type, described second conduction type is N-type.
Priority Applications (1)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106711036A (en) * | 2015-11-12 | 2017-05-24 | 上海联星电子有限公司 | Reverse blocking IGBT (Insulated Gate Bipolar Transistor) chip and manufacturing method thereof |
| CN108598011A (en) * | 2018-05-10 | 2018-09-28 | 全球能源互联网研究院有限公司 | A kind of manufacturing method and reverse blocking IGBT of reverse blocking IGBT |
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| JP2012124190A (en) * | 2010-12-06 | 2012-06-28 | Ricoh Co Ltd | Piezoelectric element, inkjet head using the same, and inkjet printer using the inkjet head |
| JP2012160738A (en) * | 2012-03-12 | 2012-08-23 | Fuji Electric Co Ltd | Method of manufacturing reverse blocking type semiconductor element |
| CN103258847A (en) * | 2013-05-09 | 2013-08-21 | 电子科技大学 | Reverse block (RB)-insulated gate bipolar transistor (IGBT) device provided with double-faced field stop with buried layers |
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| CN102244091A (en) * | 2010-05-10 | 2011-11-16 | 英飞凌科技奥地利有限公司 | Semiconductor component with a trench edge termination |
| JP2012124190A (en) * | 2010-12-06 | 2012-06-28 | Ricoh Co Ltd | Piezoelectric element, inkjet head using the same, and inkjet printer using the inkjet head |
| JP2012160738A (en) * | 2012-03-12 | 2012-08-23 | Fuji Electric Co Ltd | Method of manufacturing reverse blocking type semiconductor element |
| CN103258847A (en) * | 2013-05-09 | 2013-08-21 | 电子科技大学 | Reverse block (RB)-insulated gate bipolar transistor (IGBT) device provided with double-faced field stop with buried layers |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106711036A (en) * | 2015-11-12 | 2017-05-24 | 上海联星电子有限公司 | Reverse blocking IGBT (Insulated Gate Bipolar Transistor) chip and manufacturing method thereof |
| CN108598011A (en) * | 2018-05-10 | 2018-09-28 | 全球能源互联网研究院有限公司 | A kind of manufacturing method and reverse blocking IGBT of reverse blocking IGBT |
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| CN104658907B (en) | 2019-03-22 |
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