CN204809208U - Electric crystal packaging part with high -dielectric material layer - Google Patents

Electric crystal packaging part with high -dielectric material layer Download PDF

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Publication number
CN204809208U
CN204809208U CN201520461837.6U CN201520461837U CN204809208U CN 204809208 U CN204809208 U CN 204809208U CN 201520461837 U CN201520461837 U CN 201520461837U CN 204809208 U CN204809208 U CN 204809208U
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China
Prior art keywords
dielectric material
material layer
high dielectric
packaging part
electric crystal
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CN201520461837.6U
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Inventor
石磊
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Tongfu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors

Abstract

The utility model provides an electric crystal packaging part with high -dielectric material layer, the electric crystal packaging part is supreme including integrated circuit layer, silicon layer, aluminium lamination, encapsulation sheetmetal from down, integrated circuit layer with connect through the solder layer between the silicon layer, the aluminium lamination with the silicon layer borders on, the encapsulation sheetmetal with connect through the solder layer between the aluminium lamination, encapsulation sheetmetal one end drains with the chip, the pad welding of source electrode, the other end and the welding of the outer pin pad of encapsulation, and its characterized in that: the encapsulation sheetmetal is the copper sheet, the projection region that lower surface and the grid lead of encapsulation sheetmetal correspond is covered and is had the high -dielectric material layer. The utility model provides an encapsulation sheetmetal bottom electric crystal packaging part with high -dielectric material layer can satisfy heavy current, high -power chip package's requirement, is suitable for the chip design of any shape, and simple process is with low costs, stable performance moreover, long service life.

Description

A kind of electric crystal packaging part with high dielectric material layer
Technical field
The utility model relates to field of semiconductor package, particularly relates to a kind of electric crystal packaging part with high dielectric material layer.
Background technology
In semiconductor packaging process, with wire, the electrode on semiconductor chip and external pin are welded, namely complete the circuit pathways between chip and the outer pin of encapsulation.This based semiconductor of electric crystal, has three poles: drain electrode (drain), source electrode (source), grid (gate).They are all connected by plain conductor with the outer pin of encapsulation.It is thread bonded that plain conductor connected mode has three kinds: 1, i.e. wirebond, and used mostly is Au, Cu, Al line; 2 is metal forging bands, as Al band; 3 is sheet metal welding, i.e. clipbond, as adopted Cu sheet welding etc.Grid (gate) adopts silk thread welding, and drain electrode (drain), source electrode (source) can adopt above-mentioned three kinds of connected modes.Generally adopt silk thread to weld in existing semiconductor packaging process, this method because of stable performance, efficiency is high and be widely used, but shortcoming to be suitable for the powerful encapsulation of big current; Applying minimum is adopt sheet metal clip to weld, because often kind of package metals sheet can only be applicable to a kind of chip in the prior art, namely the design of each chip is different, the package metals plate shape that is suitable for also can be different, the mould of preparation package metals sheet is also different, and like this, each chip design just needs to design one set of die, virtually increase the cost of chip package, thus Clipbond is little in actual applications.For this reason, the utility model devises a kind of package metals sheet of universal type, all chips can be applied to, but because the lead pitch above universal type package metals sheet of the present utility model and grid is from close to too, just likely there is arcing between package metals sheet and lead-in wire, thus puncture the dielectric substance between package metals sheet and lead-in wire, cause short circuit thus defective chip, so core content of the present utility model is exactly to find the method solving this technical problem.
Chinese patent 200710128216.6 discloses a kind of semiconductor package part and routing method thereof of tool copper cash, by planting the projection on bearing part weldering node, improve copper cash in bearing part weldering node on weld property, solve the problem that seam point comes off, but this technical scheme can not be applicable to the encapsulation of high-power chip.Chinese patent 201320112889.3 discloses a kind of semiconductor packages sheet metal siamese part, comprise fin orginal, top brace, middle part brace and bottom tabs, the prior art can improve the precision that walks, good heat dissipation effect, but cost of manufacture is high, the problem puncturing capsulation material also could not be solved in packaging part.
Although above-mentioned prior art all relates to semiconductor package part and routing technique, in unresolved packaging part, puncture this technical problem of plastic packaging dielectric material.
Summary of the invention
In order to solve package metals sheet and lead pitch from causing because arcing punctures dielectric substance between filling close to too, thus cause this technical problem of Damage by Short Circuit chip, the utility model provides a kind of electric crystal packaging part with high dielectric material layer.
The technical solution of the utility model is: a kind of electric crystal packaging part with high dielectric material layer, described electric crystal packaging part comprises integrated circuit layer, silicon layer, aluminium lamination, package metals sheet from bottom to up, is connected between described integrated circuit layer with described silicon layer by solder layer; Described aluminium lamination and described silicon layer adjoin; Described package metals sheet is connected by solder layer with between described aluminium lamination; Described package metals sheet one end and chip drain, the pad solder of source electrode, the other end and the outer pin pad solder of encapsulation, it is characterized in that: described package metals sheet is copper sheet, the view field that the lower surface of described package metals sheet is corresponding with grid lead is covered with high dielectric material layer.
The drain electrode of described package metals sheet covering semiconductor, source electrode, grid.
Described grid is reverse routing with the mode of the outer pin bonding of encapsulation, and the pad namely encapsulating outer pin starts routing as the first solder joint, and bank stops to grid, and grid is as the second solder joint.
Further, as the utility model one preferred embodiment, described high dielectric material layer cover gate and grid lead upper area.
Further, as a kind of optional execution mode of the utility model, described high dielectric material layer is Al 2o 3or TiO 2, the method forming described high dielectric material layer is the one in magnetron sputtering, physical vapour deposition (PVD), ion beam assisted depositing, pulse laser deposition; The thickness of described high dielectric material layer is 0.01-0.05mm.
As a kind of optional execution mode of the utility model, described high dielectric material layer is film, and described film is the one in polyvinyl chloride, polyester, Kynoar, polyimides.
As a kind of optional execution mode of the utility model, described high dielectric material layer is the epoxy resin being mixed with inorganic powder, and described inorganic powder is one or more in talcum powder, calcium carbonate, calcite; The thickness of described high dielectric material layer is 0.01-0.12mm.
As a kind of optional execution mode of the utility model, described high dielectric material layer is the composite material of polyamide and barium titanate composition generation.
As a kind of optional execution mode of the utility model, described high dielectric material layer is epoxy resin and CaCu 3ti 4o 12mix, described high dielectric material layer adopts the mode of silk screen printing, and print thickness is 0.01-0.04mm.
As a kind of optional execution mode of the utility model, described high dielectric material layer is barium titanate coating, and the method generating described barium titanate coating is plasma spray method.
Compared with prior art, the beneficial effects of the utility model are: the electric crystal packaging part bottom the package metals sheet that the utility model provides with high dielectric material layer, the requirement of big current, high-power chip encapsulation can be met, the chip design of any shape, technique is simple, cost is low, and stable performance, long service life.
Accompanying drawing explanation
Fig. 1 is the electric crystal package structure profile having high dielectric material layer;
Description of symbols in figure: package metals sheet (Clip) 2-1, silk thread keyed jointing pin 2-3, grid (gate) 2-4, silk thread 2-5, high dielectric material layer 2-6, integrated circuit layer (DiePad) 2-7, silicon layer (Si) 2-8, aluminium lamination (Al) 2-9, solder layer (solder) 2-10.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
Embodiment 1
As shown in Figure 1, a kind of electric crystal packaging part with high dielectric material layer, is comprised integrated circuit layer 2-7, silicon layer 2-8, aluminium lamination 2-9, package metals sheet 2-1 from bottom to up, is connected between integrated circuit layer 2-7 with silicon layer 2-8 by solder layer 2-10; Aluminium lamination 2-9 and silicon layer 2-8 adjoins; Package metals sheet 2-1 is connected by solder layer with between aluminium lamination 2-9.Package metals sheet 2-1 one end and chip drain, the pad solder of source electrode, the other end and the outer pin pad solder of encapsulation.Package metals sheet 2-1 is copper sheet, and the view field that the lower surface of package metals sheet 2-1 is corresponding with grid lead is covered with high dielectric material layer 2-6.(drain electrode, source electrode do not show on figure, and drain electrode, source electrode are part chip removing grid, and each chip design is different, and drain electrode, source region are also different)
The drain electrode of package metals sheet 2-1 covering semiconductor, source electrode, grid 2-4.Wherein, grid (gate) 2-4 is reverse routing with the mode of the outer pin 2-3 bonding of encapsulation, and the pad namely encapsulating outer pin starts routing as the first solder joint, and bank stops to grid 2-4, and grid 2-4 is as the second solder joint.
High dielectric material layer covers the part except welding region bottom package metals sheet 2-1, but in order to make technique simple and save cost, can but the package metals sheet bottom surface of cover gate and grid lead upper area.
In the present embodiment, high dielectric material layer is Al 2o 3or TiO 2, the method for formation high dielectric material layer is the one in magnetron sputtering, physical vapour deposition (PVD), ion beam assisted depositing, pulse laser deposition; The thickness of described high dielectric material layer is 0.01-0.05mm.
Embodiment 2
With reference to figure 1, a kind of electric crystal packaging part with high dielectric material layer, is comprised integrated circuit layer 2-7, silicon layer 2-8, aluminium lamination 2-9, package metals sheet 2-1 from bottom to up, is connected between integrated circuit layer 2-7 with silicon layer 2-8 by solder layer 2-10; Aluminium lamination 2-9 and silicon layer 2-8 adjoins; Package metals sheet 2-1 is connected by solder layer with between aluminium lamination 2-9.Package metals sheet 2-1 one end and chip drain, the pad solder of source electrode, the other end and the outer pin pad solder of encapsulation.Package metals sheet 2-1 is copper sheet, and the view field that the lower surface of package metals sheet 2-1 is corresponding with grid lead is covered with high dielectric material layer 2-6.
Be with the difference of embodiment 1, high dielectric material layer is film, and described film is the one in polyvinyl chloride, polyester, Kynoar, polyimides.
Embodiment 3
With reference to figure 1, a kind of electric crystal packaging part with high dielectric material layer, is comprised integrated circuit layer 2-7, silicon layer 2-8, aluminium lamination 2-9, package metals sheet 2-1 from bottom to up, is connected between integrated circuit layer 2-7 with silicon layer 2-8 by solder layer 2-10; Aluminium lamination 2-9 and silicon layer 2-8 adjoins; Package metals sheet 2-1 is connected by solder layer with between aluminium lamination 2-9.Package metals sheet 2-1 one end and chip drain, the pad solder of source electrode, the other end and the outer pin pad solder of encapsulation.Package metals sheet 2-1 is copper sheet, and the view field that the lower surface of package metals sheet 2-1 is corresponding with grid lead is covered with high dielectric material layer 2-6.
Be with the difference of embodiment 1, high dielectric material layer 2-6 is the epoxy resin doped with inorganic powder, and described inorganic powder is one or more in talcum powder, calcium carbonate, calcite; The thickness of described high dielectric material layer is 0.01-0.12mm.
Embodiment 4
There is with reference to 1 one kinds, figure the electric crystal packaging part of high dielectric material layer, comprise integrated circuit layer 2-7, silicon layer 2-8, aluminium lamination 2-9, package metals sheet 2-1 from bottom to up, be connected by solder layer 2-10 between integrated circuit layer 2-7 with silicon layer 2-8; Aluminium lamination 2-9 and silicon layer 2-8 adjoins; Package metals sheet 2-1 is connected by solder layer with between aluminium lamination 2-9.Package metals sheet 2-1 one end and chip drain, the pad solder of source electrode, the other end and the outer pin pad solder of encapsulation.Package metals sheet 2-1 is copper sheet, and the view field that the lower surface of package metals sheet 2-1 is corresponding with grid lead is covered with high dielectric material layer 2-6.
Be with the difference of embodiment 1, high dielectric material layer 2-6 is the composite material of polyamide and barium titanate composition generation.
Embodiment 5
With reference to figure 1, a kind of electric crystal packaging part with high dielectric material layer, is comprised integrated circuit layer 2-7, silicon layer 2-8, aluminium lamination 2-9, package metals sheet 2-1 from bottom to up, is connected between integrated circuit layer 2-7 with silicon layer 2-8 by solder layer 2-10; Aluminium lamination 2-9 and silicon layer 2-8 adjoins; Package metals sheet 2-1 is connected by solder layer with between aluminium lamination 2-9.Package metals sheet 2-1 one end and chip drain, the pad solder of source electrode, the other end and the outer pin pad solder of encapsulation.Package metals sheet 2-1 is copper sheet, and the view field that the lower surface of package metals sheet 2-1 is corresponding with grid lead is covered with high dielectric material layer 2-6.
Be with the difference of embodiment 1, high dielectric material layer 2-6 is epoxy resin and CaCu 3ti 4o 12mix, the method forming high dielectric material layer is silk screen printing, and print thickness is 0.01-0.04mm.
Embodiment 6
With reference to figure 1, a kind of electric crystal packaging part with high dielectric material layer, is comprised integrated circuit layer 2-7, silicon layer 2-8, aluminium lamination 2-9, package metals sheet 2-1 from bottom to up, is connected between integrated circuit layer 2-7 with silicon layer 2-8 by solder layer 2-10; Aluminium lamination 2-9 and silicon layer 2-8 adjoins; Package metals sheet 2-1 is connected by solder layer with between aluminium lamination 2-9.Package metals sheet 2-1 one end and chip drain, the pad solder of source electrode, the other end and the outer pin pad solder of encapsulation.Package metals sheet 2-1 is copper sheet, and the view field that the lower surface of package metals sheet 2-1 is corresponding with grid lead is covered with high dielectric material layer 2-6.
Be with the difference of embodiment 1, high dielectric material layer 2-6 is barium titanate coating, and the method generating described barium titanate coating is plasma spray method.
Compared with prior art, there is bottom the package metals sheet that the utility model provides the electric crystal packaging part of high dielectric material layer, the requirement of big current, high-power chip encapsulation can be met, the chip design of any shape, technique is simple, and cost is low, and stable performance, long service life.
Above-mentioned explanation illustrate and describes preferred embodiment of the present utility model, as previously mentioned, be to be understood that the utility model is not limited to the form disclosed by this paper, should not regard the eliminating to other embodiments as, and can be used for other combinations various, amendment and environment, and can in invention contemplated scope described herein, changed by the technology of above-mentioned instruction or association area or knowledge.And the change that those skilled in the art carry out and change do not depart from spirit and scope of the present utility model, then all should in the protection range of the utility model claims.

Claims (10)

1. have an electric crystal packaging part for high dielectric material layer, described electric crystal packaging part comprises integrated circuit layer, silicon layer, aluminium lamination, package metals sheet from bottom to up, is connected between described integrated circuit layer with described silicon layer by solder layer; Described aluminium lamination and described silicon layer adjoin; Described package metals sheet is connected by solder layer with between described aluminium lamination; Described package metals sheet one end and chip drain, the pad solder of source electrode, the other end and the outer pin pad solder of encapsulation, it is characterized in that: described package metals sheet is copper sheet, the view field that the lower surface of described package metals sheet is corresponding with grid lead is covered with high dielectric material layer.
2. a kind of electric crystal packaging part with high dielectric material layer according to claim 1, is characterized in that: the drain electrode of described package metals sheet covering semiconductor, source electrode, grid.
3. a kind of electric crystal packaging part with high dielectric material layer according to claim 2, is characterized in that: described high dielectric material layer cover gate and grid lead upper area.
4. a kind of electric crystal packaging part with high dielectric material layer according to claim 2, is characterized in that: described high dielectric material layer is Al 2o 3or TiO 2, the method forming described high dielectric material layer is the one in magnetron sputtering, physical vapour deposition (PVD), ion beam assisted depositing, pulse laser deposition; The thickness of described high dielectric material layer is 0.01-0.05mm.
5. a kind of electric crystal packaging part with high dielectric material layer according to claim 2, it is characterized in that: described high dielectric material layer is film, described film is the one in polyvinyl chloride, polyester, Kynoar, polyimides.
6. a kind of electric crystal packaging part with high dielectric material layer according to claim 2, it is characterized in that: described high dielectric material layer is the epoxy resin being mixed with inorganic powder, described inorganic powder is one or more in talcum powder, calcium carbonate, calcite; The thickness of described high dielectric material layer is 0.01-0.12mm.
7. a kind of electric crystal packaging part with high dielectric material layer according to claim 2, is characterized in that: described high dielectric material layer is the composite material of polyamide and barium titanate composition generation.
8. a kind of electric crystal packaging part with high dielectric material layer according to claim 2, is characterized in that: described high dielectric material layer is epoxy resin and CaCu 3ti 4o 12mix, described high dielectric material layer adopts the mode of silk screen printing, and print thickness is 0.01-0.04mm.
9. a kind of electric crystal packaging part with high dielectric material layer according to claim 2, is characterized in that: described high dielectric material layer is barium titanate coating, and the method generating described barium titanate coating is plasma spray method.
10. a kind of electric crystal packaging part with high dielectric material layer according to claim 2, it is characterized in that: described grid is reverse routing with the mode of the outer pin bonding of encapsulation, namely the pad encapsulating outer pin starts routing as the first solder joint, bank stops to grid, and grid is as the second solder joint.
CN201520461837.6U 2015-06-30 2015-06-30 Electric crystal packaging part with high -dielectric material layer Active CN204809208U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109545697A (en) * 2018-12-26 2019-03-29 桂林电子科技大学 Method for packaging semiconductor and semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109545697A (en) * 2018-12-26 2019-03-29 桂林电子科技大学 Method for packaging semiconductor and semiconductor package

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CP01 Change in the name or title of a patent holder

Address after: Jiangsu province Nantong City Chongchuan road 226004 No. 288

Patentee after: Tongfu Microelectronics Co., Ltd.

Address before: Jiangsu province Nantong City Chongchuan road 226004 No. 288

Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong