CN109545697A - Method for packaging semiconductor and semiconductor package - Google Patents
Method for packaging semiconductor and semiconductor package Download PDFInfo
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- CN109545697A CN109545697A CN201811605514.4A CN201811605514A CN109545697A CN 109545697 A CN109545697 A CN 109545697A CN 201811605514 A CN201811605514 A CN 201811605514A CN 109545697 A CN109545697 A CN 109545697A
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- Prior art keywords
- adhesion layer
- lead frame
- semiconductor chip
- conductive
- conductive adhesion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/84986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
Abstract
The present invention provides a kind of method for packaging semiconductor and semiconductor packages, comprising: the drain electrode of semiconductor chip is set in the main body of lead frame；The first conductive adhesion layer is set on the first pin of lead frame, the second conductive adhesion layer is set on the source electrode of semiconductor chip；One end of conductive metal sheet is connected by the first conductive adhesion layer with the first pin, the other end of conductive metal sheet is connected by the second conductive adhesion layer with the source electrode of semiconductor chip；The grid of semiconductor chip is connected with the second pin of lead frame by bonding wire；Encapsulation of semiconductor chip, conductive metal sheet, bonding wire and part lead frame.Due to being realized using conductive metal sheet without using aluminum steel or aluminium strip bonding technology, reduce semiconductor packaging process threshold and sealed in unit cost, and conductive metal sheet can customize various specifications according to semiconductor chip packaging performance requirement, be conducive to the electric property and heat dissipation performance that improve semiconductor package.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more specifically, are related to a kind of method for packaging semiconductor and a kind of partly lead
Body encapsulating structure.
Background technique
In recent years, power semiconductor application field constantly extends, and operating current is constantly promoted, especially power electronics with
The high power applications scene such as automotive electronics is even more so, holds this requires the micro- interconnection of power semiconductor package has stronger electric current
Loading capability.Current way is encapsulated by being bonded more interconnecting lines, especially high-power chip, is mostly more aluminum steels of bonding
Or aluminium strip.However, the bonding technology of aluminum steel and aluminium strip is high to equipment performance requirement, the current country there is no mature aluminum steel or aluminium strip
Bonding apparatus supply, can only high price import American-European countries equipment, greatly drawn high power device package cost.
Summary of the invention
The present invention is directed at least solve one of the technical problems existing in the prior art.
One aspect of the present invention provides a kind of method for packaging semiconductor.
One aspect of the present invention provides a kind of semiconductor package.
In view of above-mentioned, a kind of method for packaging semiconductor provided by the invention, method for packaging semiconductor includes: by semiconductor core
The drain electrode of piece is set in the main body of lead frame；The first conductive adhesion layer is set on the first pin of lead frame, half
Second conductive adhesion layer is set on the source electrode of conductor chip；One end of conductive metal sheet is passed through into the first conductive adhesion layer and first
Pin is connected, and the other end of conductive metal sheet is connected by the second conductive adhesion layer with the source electrode of semiconductor chip；It will
The grid of semiconductor chip is connected with the second pin of lead frame by bonding wire；Encapsulation of semiconductor chip, conductive gold
Belong to piece, bonding wire and part lead frame.
In method for packaging semiconductor provided by the invention, the drain electrode of semiconductor chip is installed to the master of lead frame first
On body, so that the drain electrode of semiconductor chip can realize mechanically interconnected and electrically conducting with lead frame, secondly in lead frame
First conductive adhesion layer is set on the first pin, while the second conductive adhesion layer is set on the source electrode of semiconductor chip, then
One end of conductive metal sheet is connected by the first conductive adhesion layer with the first pin, then the other end of conductive metal sheet is led to
It crosses the second conductive adhesion layer to be connected with the source electrode of semiconductor chip, realizes the first of lead frame by setting conductive metal sheet
The effect that pin is connected with the source electrode of semiconductor chip, so that the source electrode of lead frame and semiconductor chip realizes machinery
Interconnection and electrically conducting；Part lead frame, semiconductor chip, conductive metal sheet and bonding wire are then encapsulated again, complete half
The preparation process of conductor package structure is reduced due to being realized using conductive metal sheet without using aluminum steel or aluminium strip bonding technology
Semiconductor packaging process threshold and sealed in unit cost, and conductive metal sheet can want according to semiconductor chip packaging performance
Customization various specifications are sought, the electric property and heat dissipation performance that improve semiconductor package are conducive to.
Preferably, need to consider the performance number of semiconductor chip when selecting conductive metal sheet, and conductive metal sheet
Resistance value and the performance number of semiconductor chip are positively correlated, in order to choose suitable conductive gold according to the performance number of semiconductor chip
Belong to piece, so that semiconductor package has stronger current carrying capacity.
In addition, a kind of method for packaging semiconductor that above-mentioned technical proposal provides according to the present invention also has following supplementary technology
Feature:
In any of the above-described technical solution, it is preferable that the drain electrode of semiconductor chip is set in the main body of lead frame
The step of, comprising: third conductive adhesion layer is set in the main body of lead frame；The drain electrode of semiconductor chip is fitted in into third
On conductive adhesion layer.
In the technical scheme, providing a kind of will be set to the drain electrode of semiconductor chip in the main body of lead frame
Scheme, first in the main body of lead frame be arranged third conductive adhesion layer so that semiconductor chip third conductive adhesion layer with
The main body of lead frame is connected, so that the drain electrode of semiconductor chip can realize mechanically interconnected and electrically conducting with lead frame.
In any of the above-described technical solution, it is preferable that be set to the main body of lead frame in the drain electrode by semiconductor chip
Before upper step, further includes: according to the size custom lead-frame of semiconductor chip.
In the technical scheme, it according to die size custom lead-frame, can guarantee the size symbol of lead frame
Semiconductor chip is closed, thus the surface area firstly the need of guarantee semiconductor chip is less than the surface area of the main body of lead frame,
Semiconductor chip is allowed to conform to the main body of lead frame completely without leaking outside, this ensure that safety when using
Energy.
In any of the above-described technical solution, it is preferable that the step of according to the size custom lead-frame of semiconductor chip, packet
It includes: in ieadf iotaame frame, the surface area of the first pin of lead frame being set greater than the second pin of lead frame
Surface area.
In the technical scheme, a kind of concrete scheme of custom lead-frame is provided, in custom lead-frame, is also needed
To consider the surface area that the surface area of the first pin of lead frame is set greater than to the second pin of lead frame, even if
It obtains the first pin being connected with conductive metal sheet and is greater than the second pin being connected with bonding wire, this is because conductive metal
Sector-meeting is big relative to bonding wire volume, and such first pin needs to guarantee to connect efficiently with conductive metal sheet by
The surface area of one pin is accordingly done greatly, to improve connection area.
In any of the above-described technical solution, it is preferable that the step of according to the size custom lead-frame of semiconductor chip, packet
It includes: in ieadf iotaame frame, the first pin and second pin of lead frame being passed through into acclivitous changeover portion and lead frame
The main body of frame is connected, so that the first conductive adhesion layer and the second conductive adhesion layer are in the same plane.
In the technical scheme, a kind of concrete scheme of custom lead-frame is provided, in custom lead-frame, is also needed
Will consider conductive metal sheet both ends installation site difference in height so that conductive metal sheet both ends installation site be preferably located at it is same
In plane, thus it is required that the surface of the first conductive adhesion layer and the surface of the second conductive adhesion layer are located at sustained height,
Due to being provided with semiconductor chip below the first conductive adhesion layer, and the lower section of the second conductive adhesion layer be then directly with
First pin is connected, and thus causes difference in height due to the presence of semiconductor chip, at this time in order to overcome the difference in height, needs
First pin and second pin are raised upwards relative to the main body of lead frame, therefore will pass through acclivitous changeover portion
It is attached, the low one end of height is connected with the main body of lead frame in changeover portion both ends, and height is high in changeover portion both ends
One end is connected with the first pin and second pin, so that the table on the surface of the first conductive adhesion layer and the second conductive adhesion layer
Face is located at sustained height, and the both ends of such conductive metal sheet can connect respectively with the first conductive adhesion layer and the second conductive adhesive level
Touching guarantees that the both ends connection of conductive metal sheet is firm.
It is contemplated that ground, in order to guarantee that the both ends of conductive metal sheet respectively can be conductive viscous with the first conductive adhesion layer and second
Level contact is connect, changeover portion can not also be used to go to make up difference in height, but setting among conductive metal sheet is had into ladder section,
So that the both ends of conductive metal sheet have difference in height, at this time in fixed conductive metal sheet, it is necessary to positioned at different height
Both ends distinguish, when according to changeover portion if the setting position that is not necessarily to conductive metal sheet distinguish.
In any of the above-described technical solution, it is preferable that be connected with semiconductor chip in conductive metal sheet with bonding wire
After connecing, conductive metal sheet and bonding wire the surface of semiconductor chip projection in the plane without overlapping region.
In the technical scheme, due to needing to avoid the connection between conductive metal sheet and bonding wire, the two phase is avoided
A series of the problems such as influences occurred after connection, such as short circuit, thus conductive metal sheet and bonding wire and semiconductor chip
After being connected, need to guarantee conductive metal sheet and bonding wire the surface of semiconductor chip projection in the plane without being overlapped
Region, so that a possibility that conductive metal sheet can not be contacted with bonding wire, while also there is no contacts.
In any of the above-described technical solution, it is preferable that the first conductive adhesion layer is following any or combination: conducting resinl, pricker
Wlding material or eutectic wlding material；And/or second conductive adhesion layer be it is following any or combination: conducting resinl, brazing material or eutectic
Wlding material；And/or third conductive adhesion layer is following any or combination: conducting resinl, brazing material or eutectic wlding material.
In the technical scheme, the first conductive adhesion layer and/or the second conductive adhesion layer and/or third conductive adhesion layer point
It is not set as any in conducting resinl, brazing material or eutectic wlding material or combination, as long as can be realized between connected component
Mechanical connection and electrically conducting purpose.And the first conductive adhesion layer, the second conductive adhesion layer and third conductive adhesion layer
It can choose identical or different material.
It is contemplated that ground, the material according to selected by conductive adhesion layer can be by conductive sheet adhesive technique, unleaded in connection
Soldering processes or eutectic Welding realize the connection between two components.
In addition, the first conductive adhesion layer, the second conductive adhesion layer and third conductive adhesion layer are respectively continuous sheet knot
Structure or convex block structure for discrete distribution.Conductive adhesion layer can be continuous laminated structure, simultaneously because needing to consider envelope
Stress is filled, so that conductive adhesion layer is also possible to the convex block structure (for example, convex block structure of array) of discrete distribution, or
Other shapes, for the purpose of reducing the encapsulation stress between semiconductor chip and conductive metal sheet.
A kind of semiconductor package is provided according to the second aspect of invention, semiconductor package includes: lead frame
Frame；The drain electrode of semiconductor chip, semiconductor chip is set in the main body of lead frame, and the periphery of semiconductor chip is without departing from drawing
The main body of wire frame；First conductive adhesion layer and the second conductive adhesion layer are separately positioned on the first pin and half of lead frame
On the source electrode of conductor chip；One end of conductive metal sheet, conductive metal sheet is connected by the first conductive adhesion layer with the first pin
It connects, the other end of conductive metal sheet is connected by the second conductive adhesion layer with the source electrode of semiconductor chip.
Semiconductor package provided by the invention includes lead frame, semiconductor chip, the first conductive adhesion layer, and second
The drain electrode of conductive adhesion layer and conductive metal sheet, semiconductor chip is set in the main body of lead frame, so that semiconductor chip
Drain electrode can with lead frame realize mechanically interconnected and electrically conducting, the first conductive adhesion layer and the second conductive adhesion layer are set respectively
It sets on the first pin of lead frame and the source electrode of semiconductor chip, one end of conductive metal sheet passes through the first conductive adhesion layer
It is connected with the first pin, then the other end of conductive metal sheet is passed through to the source electrode phase of the second conductive adhesion layer and semiconductor chip
Connection realizes the effect that the first pin of lead frame is connected with the source electrode of semiconductor chip by setting conductive metal sheet,
So that the source electrode of lead frame and semiconductor chip realizes mechanically interconnected and electrically conducting；Due to using conductive metal sheet without
Aluminum steel or aluminium strip bonding technology need to be used to realize, reduce semiconductor packaging process threshold and sealed in unit cost, and conductive
Sheet metal can customize various specifications according to semiconductor chip packaging performance requirement, be conducive to the electricity for improving semiconductor package
Learn performance and heat dissipation performance.
Wherein, the periphery of semiconductor chip allows the drain electrode of semiconductor chip complete without departing from the main body of lead frame
It is set in the main body of lead frame entirely, guarantee semiconductor chip ensures that the main body of lead frame can be right without exposed area
Semiconductor chip plays certain protection supporting role.
Preferably, need to consider the performance number of semiconductor chip when selecting conductive metal sheet, and conductive metal sheet
Resistance value and the performance number of semiconductor chip are positively correlated, in order to choose suitable conductive gold according to the performance number of semiconductor chip
Belong to piece, so that semiconductor package has stronger current carrying capacity.
In addition, a kind of semiconductor package that above-mentioned technical proposal provides according to the present invention also has following supplementary technology
Feature:
In any of the above-described technical solution, it is preferable that semiconductor package further include: bonding wire, bonding wire
One end is connected with the grid of semiconductor chip, and the other end of bonding wire is connected with the second pin of lead frame；Encapsulation
Part lead frame, semiconductor chip, conductive metal sheet and bonding wire are packaged by shell, encapsulating housing.
In the technical scheme, semiconductor package further includes bonding wire and encapsulating housing, one end of bonding wire
It is connected with the grid of semiconductor chip, the other end of bonding wire is connected with the second pin of lead frame, so that lead
The second pin of frame and the grid of semiconductor chip are realized, are then encapsulated part lead frame by encapsulating housing again, are partly led
Body chip realizes conductive metal sheet and bonding wire is mechanically interconnected and electrically conducting.
In any of the above-described technical solution, it is preferable that semiconductor package further include: third conductive adhesion layer, third
Conductive adhesion layer is arranged between the main body of lead frame and semiconductor chip.
In the technical scheme, semiconductor package further includes third conductive adhesion layer, and third conductive adhesion layer provides
A kind of scheme that the drain electrode of semiconductor chip will be set in the main body of lead frame, is arranged in the main body of lead frame
Third conductive adhesion layer, so that semiconductor chip third conductive adhesion layer is connected with the main body of lead frame, so that semiconductor
The drain electrode of chip can realize mechanically interconnected and electrically conducting with lead frame.
In any of the above-described technical solution, it is preferable that the surface area of the first pin of lead frame is greater than lead frame
The surface area of second pin.
In the technical scheme, a kind of concrete scheme of custom lead-frame is provided, in custom lead-frame, is also needed
To consider the surface area that the surface area of the first pin of lead frame is set greater than to the second pin of lead frame, even if
It obtains the first pin being connected with conductive metal sheet and is greater than the second pin being connected with bonding wire, this is because conductive metal
Sector-meeting is big relative to bonding wire volume, and such first pin needs to guarantee to connect efficiently with conductive metal sheet by
The surface area of one pin is accordingly done greatly, to improve connection area.
In any of the above-described technical solution, it is preferable that semiconductor package further include: changeover portion, changeover portion are inclination
Setting, the first pin of lead frame and second pin are connected by changeover portion with the main body of lead frame, so that first leads
Electric adhesive layer and the second conductive adhesion layer are in the same plane.
In the technical scheme, a kind of concrete scheme of custom lead-frame is provided, in custom lead-frame, is also needed
Will consider conductive metal sheet both ends installation site difference in height so that conductive metal sheet both ends installation site be preferably located at it is same
In plane, thus it is required that the surface of the first conductive adhesion layer and the surface of the second conductive adhesion layer are located at sustained height,
Due to being provided with semiconductor chip below the first conductive adhesion layer, and the lower section of the second conductive adhesion layer be then directly with
First pin is connected, and thus causes difference in height due to the presence of semiconductor chip, at this time in order to overcome the difference in height, needs
First pin and second pin are raised upwards relative to the main body of lead frame, therefore will pass through acclivitous changeover portion
It is attached, the low one end of height is connected with the main body of lead frame in changeover portion both ends, and height is high in changeover portion both ends
One end is connected with the first pin and second pin, so that the table on the surface of the first conductive adhesion layer and the second conductive adhesion layer
Face is located at sustained height, and the both ends of such conductive metal sheet can connect respectively with the first conductive adhesion layer and the second conductive adhesive level
Touching guarantees that the both ends connection of conductive metal sheet is firm.
It is contemplated that ground, in order to guarantee that the both ends of conductive metal sheet respectively can be conductive viscous with the first conductive adhesion layer and second
Level contact is connect, changeover portion can not also be used to go to make up difference in height, but setting among conductive metal sheet is had into ladder section,
So that the both ends of conductive metal sheet have difference in height, at this time in fixed conductive metal sheet, it is necessary to positioned at different height
Both ends distinguish, when according to changeover portion if the setting position that is not necessarily to conductive metal sheet distinguish.
In any of the above-described technical solution, it is preferable that be connected with semiconductor chip in conductive metal sheet with bonding wire
After connecing, conductive metal sheet and bonding wire the surface of semiconductor chip projection in the plane without overlapping region.
In the technical scheme, due to needing to avoid the connection between conductive metal sheet and bonding wire, the two phase is avoided
A series of the problems such as influences occurred after connection, such as short circuit, thus conductive metal sheet and bonding wire and semiconductor chip
After being connected, need to guarantee conductive metal sheet and bonding wire the surface of semiconductor chip projection in the plane without being overlapped
Region, so that a possibility that conductive metal sheet can not be contacted with bonding wire, while also there is no contacts.
In any of the above-described technical solution, it is preferable that the surface area at the both ends of conductive metal sheet is respectively greater than the first conduction
The surface area of adhesive layer and the second conductive adhesion layer glues so that the first conduction can be completely covered in the both ends of conductive metal sheet respectively
Connect layer and the second conductive adhesion layer.
In the technical scheme, the surface area at the both ends of conductive metal sheet is respectively greater than the first conductive adhesion layer and second
The surface area of conductive adhesion layer, in this way the both ends of conductive metal sheet respectively with the first conductive adhesion layer and the second conductive adhesion layer
When being connected, it can make the both ends of conductive metal sheet that the first conductive adhesion layer and the second conductive adhesive can be completely covered respectively
Layer guarantees that connection effect is stablized, prevents the first conductive adhesion layer for having exposing and the second conductive adhesion layer from influencing whether other
Element.
In any of the above-described technical solution, it is preferable that the resistance value of conductive metal sheet and the performance number positive of semiconductor chip
It closes.
In the technical scheme, need to consider the performance number of semiconductor chip when selecting conductive metal sheet, and conductive
The resistance value of sheet metal and the performance number of semiconductor chip are positively correlated, suitable in order to choose according to the performance number of semiconductor chip
Conductive metal sheet so that semiconductor package has stronger current carrying capacity.
In any of the above-described technical solution, it is preferable that the first conductive adhesion layer is following any or combination: conducting resinl, pricker
Wlding material or eutectic wlding material；And/or second conductive adhesion layer be it is following any or combination: conducting resinl, brazing material or eutectic
Wlding material；And/or third conductive adhesion layer is following any or combination: conducting resinl, brazing material or eutectic wlding material.
In the technical scheme, the first conductive adhesion layer and/or the second conductive adhesion layer and/or third conductive adhesion layer point
It is not set as any in conducting resinl, brazing material or eutectic wlding material or combination, as long as can be realized between connected component
Mechanical connection and electrically conducting purpose.And the first conductive adhesion layer, the second conductive adhesion layer and third conductive adhesion layer
It can choose identical or different material.
It is contemplated that ground, the material according to selected by conductive adhesion layer can be by conductive sheet adhesive technique, unleaded in connection
Soldering processes or eutectic Welding realize the connection between two components.
In any of the above-described technical solution, it is preferable that the first conductive adhesion layer, the second conductive adhesion layer and third conduction are viscous
Connecing layer is respectively continuous laminated structure or the convex block structure for discrete distribution.
In the technical scheme, the first conductive adhesion layer, the second conductive adhesion layer and third conductive adhesion layer are respectively and connect
Continuous laminated structure or the convex block structure for discrete distribution.Conductive adhesion layer can be continuous laminated structure, simultaneously because
It needs to consider encapsulation stress, so that conductive adhesion layer is also possible to convex block structure (for example, convex block of array of discrete distribution
Shape structure) or other shapes, for the purpose of reducing the encapsulation stress between semiconductor chip and conductive metal sheet.
Additional aspect and advantage according to the present invention will provide in following description section, partially will be from following description
In become obvious, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 shows the flow chart of the method for packaging semiconductor of one embodiment of the present of invention offer.
Fig. 2 shows the another flow charts for the method for packaging semiconductor that one embodiment of the present of invention provides；
Fig. 3 shows the another flow chart of the method for packaging semiconductor of one embodiment of the present of invention offer；
Fig. 4 shows a signal of the encapsulation process of the semiconductor package of one embodiment of the present of invention offer
Figure；
Fig. 5 shows another signal of the encapsulation process of the semiconductor package of one embodiment of the present of invention offer
Figure；
Fig. 6 shows another signal of the encapsulation process of the semiconductor package of one embodiment of the present of invention offer
Figure；
Fig. 7 shows another signal of the encapsulation process of the semiconductor package of one embodiment of the present of invention offer
Figure；
Fig. 8 shows another signal of the encapsulation process of the semiconductor package of one embodiment of the present of invention offer
Figure；
Fig. 9 shows another signal of the encapsulation process of the semiconductor package of one embodiment of the present of invention offer
Figure；
Figure 10 shows a schematic diagram of the semiconductor package of one embodiment of the present of invention offer；
Figure 11 shows another schematic diagram of the semiconductor package of one embodiment of the present of invention offer；
Figure 12 shows another schematic diagram of the semiconductor package of one embodiment of the present of invention offer；
Figure 13 shows another schematic diagram of the semiconductor package of one embodiment of the present of invention offer；
Figure 14 shows another schematic diagram of the semiconductor package of one embodiment of the present of invention offer；
Figure 15 shows another schematic diagram of the semiconductor package of one embodiment of the present of invention offer.
Appended drawing reference:
Wherein, corresponding relationship of the Fig. 4 into Figure 15 between appended drawing reference and component names are as follows:
10 lead frames, 102 main bodys, 104 first pins, 106 second pins, 108 changeover portions, 12 semiconductor chips, 122
Grid, 14 first conductive adhesion layers, 16 second conductive adhesion layers, 18 conductive metal sheets, 20 bonding wires, 22 encapsulating housings, 24
Third conductive adhesion layer.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention is further described in detail.It should be noted that in the absence of conflict, the implementation of the application
Feature in example and embodiment can be combined with each other.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, still, the present invention may be used also
Implement in a manner of using other than the one described here, therefore, protection scope of the present invention is not by following public tool
The limitation of body embodiment.
The method for packaging semiconductor provided according to one embodiment of present invention and half are described referring to Fig. 1 to Figure 15
Conductor package structure.
Fig. 1 shows the schematic block diagram of the method for packaging semiconductor of embodiment according to the present invention.
As shown in Figure 1, method for packaging semiconductor according to an embodiment of the invention, comprising:
The drain electrode of semiconductor chip is set in the main body of lead frame by S102；
S104 is arranged the first conductive adhesion layer on the first pin of lead frame, sets on the source electrode of semiconductor chip
Set the second conductive adhesion layer；
One end of conductive metal sheet is connected by the first conductive adhesion layer with the first pin, by conductive metal by S106
The other end of piece is connected by the second conductive adhesion layer with the source electrode of semiconductor chip；
The grid of semiconductor chip is connected with the second pin of lead frame by bonding wire by S108；
S110, encapsulation of semiconductor chip, conductive metal sheet, bonding wire and part lead frame.
In method for packaging semiconductor provided by the invention, the drain electrode of semiconductor chip is installed to the master of lead frame first
On body, so that the drain electrode of semiconductor chip can realize mechanically interconnected and electrically conducting with lead frame, secondly in lead frame
First conductive adhesion layer is set on the first pin, while the second conductive adhesion layer is set on the source electrode of semiconductor chip, then
One end of conductive metal sheet is connected by the first conductive adhesion layer with the first pin, then the other end of conductive metal sheet is led to
It crosses the second conductive adhesion layer to be connected with the source electrode of semiconductor chip, realizes the first of lead frame by setting conductive metal sheet
The effect that pin is connected with the source electrode of semiconductor chip, so that the source electrode of lead frame and semiconductor chip realizes machinery
Interconnection and electrically conducting；Then encapsulate part lead frame, semiconductor chip, conductive metal sheet and bonding wire again, rib cutting at
Type completes power device package, the preparation process of semiconductor package, due to using conductive metal sheet without using aluminum steel or
Aluminium strip bonding technology is realized, reduces semiconductor packaging process threshold and sealed in unit cost, and conductive metal sheet can root
Various specifications are customized according to semiconductor chip packaging performance requirement, are conducive to the electric property and the heat dissipation that improve semiconductor package
Performance.
Preferably, need to consider the performance number of semiconductor chip when selecting conductive metal sheet, and conductive metal sheet
Resistance value and the performance number of semiconductor chip are positively correlated, in order to choose suitable conductive gold according to the performance number of semiconductor chip
Belong to piece, so that semiconductor package has stronger current carrying capacity.
Fig. 2 shows the schematic block diagrams of the method for packaging semiconductor of embodiment according to the present invention.
As shown in Fig. 2, method for packaging semiconductor according to an embodiment of the invention, comprising:
Third conductive adhesion layer is arranged in S202 in the main body of lead frame；
S204 fits in the drain electrode of semiconductor chip on third conductive adhesion layer；
S206 is arranged the first conductive adhesion layer on the first pin of lead frame, sets on the source electrode of semiconductor chip
Set the second conductive adhesion layer；
One end of conductive metal sheet is connected by the first conductive adhesion layer with the first pin, by conductive metal by S208
The other end of piece is connected by the second conductive adhesion layer with the source electrode of semiconductor chip；
The grid of semiconductor chip is connected with the second pin of lead frame by bonding wire by S210；
S212, encapsulation of semiconductor chip, conductive metal sheet, bonding wire and part lead frame.
In this embodiment, a kind of side that the drain electrode of semiconductor chip will be set in the main body of lead frame is provided
Case, first in the main body of lead frame be arranged third conductive adhesion layer so that semiconductor chip third conductive adhesion layer with draw
The main body of wire frame is connected, so that the drain electrode of semiconductor chip can realize mechanically interconnected and electrically conducting with lead frame.
Fig. 3 shows the schematic block diagram of the method for packaging semiconductor of embodiment according to the present invention.
As shown in figure 3, method for packaging semiconductor according to an embodiment of the invention, comprising:
S302, according to the size custom lead-frame of semiconductor chip；
The drain electrode of semiconductor chip is set in the main body of lead frame by S304；
S306 is arranged the first conductive adhesion layer on the first pin of lead frame, sets on the source electrode of semiconductor chip
Set the second conductive adhesion layer；
One end of conductive metal sheet is connected by the first conductive adhesion layer with the first pin, by conductive metal by S308
The other end of piece is connected by the second conductive adhesion layer with the source electrode of semiconductor chip；
The grid of semiconductor chip is connected with the second pin of lead frame by bonding wire by S310；
S312, encapsulation of semiconductor chip, conductive metal sheet, bonding wire and part lead frame.
In this embodiment, it can guarantee that the size of lead frame meets according to die size custom lead-frame
Semiconductor chip, thus the surface area firstly the need of guarantee semiconductor chip is less than the surface area of the main body of lead frame, makes
Semiconductor chip can conform to the main body of lead frame without leaking outside completely, this ensure that security performance when using.
In one embodiment provided by the invention, it is preferable that according to the size custom lead-frame of semiconductor chip
Step, comprising: in ieadf iotaame frame, the surface area of the first pin of lead frame is set greater than the second of lead frame
The surface area of pin.
In this embodiment, a kind of concrete scheme of custom lead-frame is provided, in custom lead-frame, it is also necessary to
In view of the surface area of the first pin of lead frame to be set greater than to the surface area of the second pin of lead frame, i.e., so that
The first pin being connected with conductive metal sheet is greater than the second pin being connected with bonding wire, this is because conductive metal sheet
Can be big relative to bonding wire volume, such first pin needs to guarantee to connect efficiently with conductive metal sheet by first
The surface area of pin is accordingly done greatly, to improve connection area.
In one embodiment provided by the invention, it is preferable that according to the size custom lead-frame of semiconductor chip
Step, comprising: in ieadf iotaame frame, by the first pin and second pin of lead frame by acclivitous changeover portion with
The main body of lead frame is connected, so that the first conductive adhesion layer and the second conductive adhesion layer are in the same plane.
In this embodiment, a kind of concrete scheme of custom lead-frame is provided, in custom lead-frame, it is also necessary to
In view of the difference in height of conductive metal sheet both ends installation site, so that conductive metal sheet both ends installation site is preferably located at same put down
On face, thus it is required that the surface of the first conductive adhesion layer and the surface of the second conductive adhesion layer are located at sustained height, by
It is then directly in being provided with semiconductor chip below the first conductive adhesion layer, and in the lower section of the second conductive adhesion layer
One pin is connected, and thus causes difference in height due to the presence of semiconductor chip, at this time in order to overcome the difference in height, needs
First pin and second pin are raised upwards relative to the main body of lead frame, thus will pass through acclivitous changeover portion into
Row connects, and the low one end of height is connected with the main body of lead frame in changeover portion both ends, height is high in changeover portion both ends one
End is connected with the first pin and second pin, so that the surface on the surface of the first conductive adhesion layer and the second conductive adhesion layer
Positioned at sustained height, the both ends of such conductive metal sheet can connect respectively with the first conductive adhesion layer and the second conductive adhesive level
Touching guarantees that the both ends connection of conductive metal sheet is firm.
It is contemplated that ground, in order to guarantee that the both ends of conductive metal sheet respectively can be conductive viscous with the first conductive adhesion layer and second
Level contact is connect, changeover portion can not also be used to go to make up difference in height, but setting among conductive metal sheet is had into ladder section,
So that the both ends of conductive metal sheet have difference in height, at this time in fixed conductive metal sheet, it is necessary to positioned at different height
Both ends distinguish, when according to changeover portion if the setting position that is not necessarily to conductive metal sheet distinguish.
In one embodiment provided by the invention, it is preferable that conductive metal sheet and bonding wire and semiconductor core
After piece is connected, conductive metal sheet and bonding wire the surface of semiconductor chip projection in the plane without overlapping region.
In this embodiment, due to needing to avoid the connection between conductive metal sheet and bonding wire, the two is avoided to be connected
A series of the problems such as influences occurred after connecing, such as short circuit, thus conductive metal sheet and bonding wire with semiconductor chip phase
After connection, need to guarantee conductive metal sheet and bonding wire the surface of semiconductor chip projection in the plane without being overlapped area
Domain, so that a possibility that conductive metal sheet can not be contacted with bonding wire, while also there is no contacts.
In one embodiment provided by the invention, it is preferable that the first conductive adhesion layer is following any or combination: conductive
Glue, brazing material or eutectic wlding material；And/or second conductive adhesion layer be it is following any or combination: conducting resinl, brazing material or
Eutectic wlding material；And/or third conductive adhesion layer is following any or combination: conducting resinl, brazing material or eutectic wlding material.
In this embodiment, the first conductive adhesion layer and/or the second conductive adhesion layer and/or third conductive adhesion layer difference
It is set as any in conducting resinl, brazing material or eutectic wlding material or combination, as long as can be realized the machine between connected component
Tool connection and electrically conducting purpose.And the first conductive adhesion layer, the second conductive adhesion layer and third conductive adhesion layer can
To select identical or different material.
It is contemplated that ground, the material according to selected by conductive adhesion layer can be by conductive sheet adhesive technique, unleaded in connection
Soldering processes or eutectic Welding realize the connection between two components.
In addition, the first conductive adhesion layer, the second conductive adhesion layer and third conductive adhesion layer are respectively continuous sheet knot
Structure or convex block structure for discrete distribution.Conductive adhesion layer can be continuous laminated structure, simultaneously because needing to consider envelope
Stress is filled, so that conductive adhesion layer is also possible to the convex block structure (for example, convex block structure of array) of discrete distribution, or
Other shapes, for the purpose of reducing the encapsulation stress between semiconductor chip and conductive metal sheet.
As Fig. 4 to Figure 10 show the preparation process signal of the method for packaging semiconductor of one embodiment provided by the invention
Figure, Fig. 4 and Fig. 5 are the size custom lead-frame according to semiconductor chip, and Fig. 6 is that third is arranged in the main body of lead frame
Conductive adhesion layer, Fig. 7 are to fit in the drain electrode of semiconductor chip on third conductive adhesion layer, and Fig. 8 is the of lead frame
First conductive adhesion layer is set on one pin, the second conductive adhesion layer is set on the source electrode of semiconductor chip, and Fig. 9 is will be conductive
One end of sheet metal is connected by the first conductive adhesion layer with the first pin, and the other end of conductive metal sheet is led by second
Electric adhesive layer is connected with the source electrode of semiconductor chip, and Figure 10 is by the second pin of the grid of semiconductor chip and lead frame
It is connected by bonding wire.
A kind of semiconductor package is provided according to the second aspect of invention, semiconductor package includes: lead frame
Frame 10；The drain electrode of semiconductor chip 12, semiconductor chip 12 is set in the main body of lead frame 10, the periphery of semiconductor chip
Without departing from the main body of lead frame；First conductive adhesion layer 14 and the second conductive adhesion layer 16, are separately positioned on lead frame 10
The first pin 104 and semiconductor chip 12 source electrode on；It is led by first one end of conductive metal sheet 18, conductive metal sheet 18
Electric adhesive layer 14 is connected with the first pin 104, and the other end of conductive metal sheet 18 is passed through the second conductive adhesion layer 16 and half
The source electrode of conductor chip 12 is connected.
As shown in Figure 11 to Figure 15, semiconductor package provided by the invention includes lead frame 10, semiconductor chip
12, the first conductive adhesion layer 14, the second conductive adhesion layer 16 and conductive metal sheet 18, the drain electrode of semiconductor chip 12, which is set to, draws
In the main body 102 of wire frame 10 so that the drain electrode of semiconductor chip 12 can be realized with lead frame 10 it is mechanically interconnected with electrically lead
Logical, the first conductive adhesion layer 14 and the second conductive adhesion layer 16 are separately positioned on the first pin 104 of lead frame 10 and partly lead
On the source electrode of body chip 12, one end of conductive metal sheet 18 is connected by the first conductive adhesion layer 14 with the first pin 104, then
The other end of conductive metal sheet 18 is connected by the second conductive adhesion layer 16 with the source electrode of semiconductor chip 12, setting is passed through
Conductive metal sheet 18 realizes the effect that the first pin 104 of lead frame 10 is connected with the source electrode of semiconductor chip 12, in turn
So that the source electrode of lead frame 10 and semiconductor chip 12 realizes mechanically interconnected and electrically conducting；Due to using conductive metal sheet 18
It is realized without using aluminum steel or aluminium strip bonding technology, reduces semiconductor packaging process threshold and sealed in unit cost, and lead
Electric metal piece 18 can require customization various specifications according to 12 encapsulation performance of semiconductor chip, be conducive to improve semiconductor packages knot
The electric property and heat dissipation performance of structure.
Wherein, the periphery of semiconductor chip 12 without departing from lead frame 10 main body so that the drain electrode of semiconductor chip 12
Can be completely set up in the main body of lead frame 10, guarantee semiconductor chip 12 ensures lead frame without exposed area
10 main body can play certain protection supporting role to semiconductor chip 12.
Preferably, need to consider the performance number of semiconductor chip 12, and conductive metal when selecting conductive metal sheet 18
The resistance value of piece 18 and the performance number of semiconductor chip 12 are positively correlated, and are closed in order to choose according to the performance number of semiconductor chip 12
Suitable conductive metal sheet 18, so that semiconductor package has stronger current carrying capacity.
In one embodiment provided by the invention, it is preferable that semiconductor package further include: bonding wire 20, key
The one end for closing lead 20 is connected with the grid 122 of semiconductor chip 12, the other end and the lead frame 10 of bonding wire 20
Second pin 106 is connected；Encapsulating housing 22, encapsulating housing 22 is by part lead frame 10, semiconductor chip 12, conductive metal
Piece 18 and bonding wire 20 are packaged.
In this embodiment, semiconductor package further includes bonding wire 20 and encapsulating housing 22, bonding wire 20
One end is connected with the grid 122 of semiconductor chip 12, the other end of bonding wire 20 and the second pin 106 of lead frame 10
It is connected, so that the grid 122 of the second pin 106 of lead frame 10 and semiconductor chip 12 is realized, then passes through encapsulation again
Shell 22 encapsulate part lead frame 10, semiconductor chip 12, realize conductive metal sheet 18 and bonding wire 20 it is mechanically interconnected with
Electrically conducting.
In one embodiment provided by the invention, it is preferable that semiconductor package further include: third conductive adhesion layer
24, third conductive adhesion layer 24 is arranged between the main body 102 of lead frame 10 and semiconductor chip 12.
In this embodiment, semiconductor package further includes third conductive adhesion layer 24, and third conductive adhesion layer 24 mentions
A kind of scheme that the drain electrode of semiconductor chip 12 will be set in the main body 102 of lead frame 10 is supplied, in lead frame 10
Main body 102 on third conductive adhesion layer 24 is set so that 12 third conductive adhesion layer 24 of semiconductor chip and lead frame 10
Main body 102 be connected so that the drain electrode of semiconductor chip 12 can realize mechanically interconnected and electrically conducting with lead frame 10.
In one embodiment provided by the invention, it is preferable that the surface area of the first pin 104 of lead frame 10 is greater than
The surface area of the second pin 106 of lead frame 10.
In this embodiment, a kind of concrete scheme of custom lead-frame 10 is provided, in custom lead-frame 10, also
Need the second pin 106 in view of the surface area of the first pin 104 of lead frame 10 to be set greater than to lead frame 10
Surface area, i.e., so that the first pin 104 being connected with conductive metal sheet 18 be greater than be connected with bonding wire 20 second
Pin 106, this is because conductive metal sheet 18 can be big relative to 20 volume of bonding wire, such first pin 104 is in order to guarantee
It can be connect with conductive metal sheet 18 and the surface area by the first pin 104 is efficiently needed accordingly to do greatly, to improve connection area.
In one embodiment provided by the invention, it is preferable that semiconductor package further include: changeover portion 108, transition
Section 108 is is obliquely installed, and changeover portion 108 is by the first pin 104 and second pin 106 of lead frame 10 and lead frame 10
Main body 102 is connected, so that the first conductive adhesion layer 14 and the second conductive adhesion layer 16 are in the same plane.
In this embodiment, a kind of concrete scheme of custom lead-frame 10 is provided, in custom lead-frame 10, also
The difference in height in view of 18 both ends installation site of conductive metal sheet is needed, so that the 18 best position of both ends installation site of conductive metal sheet
In on same plane, thus it is required that the surface of the first conductive adhesion layer 14 and the surface of the second conductive adhesion layer 16 are located at
Sustained height, due to being provided with semiconductor chip 12 in the lower section of the first conductive adhesion layer 14, and in the second conductive adhesion layer 16
Lower section be then directly to be connected with the first pin 104, difference in height is thus caused due to the presence of semiconductor chip 12, this
When in order to overcome the difference in height, need by the first pin 104 and second pin 106 relative to lead frame 10 main body 102 to
On raise, therefore will pass through acclivitous changeover portion 108 and be attached, in 108 both ends of changeover portion the low one end of height with draw
The main body 102 of wire frame 10 is connected, the high one end of height and the first pin 104 and second pin 106 in 108 both ends of changeover portion
It is connected, so that the surface of the first conductive adhesion layer 14 and the surface of the second conductive adhesion layer 16 are located at sustained height, in this way
The both ends of conductive metal sheet 18 can guarantee conductive gold with 16 face contact of the first conductive adhesion layer 14 and the second conductive adhesion layer respectively
The both ends connection for belonging to piece 18 is firm.
It is contemplated that ground, in order to guarantee that the both ends of conductive metal sheet 18 can be led respectively with the first conductive adhesion layer 14 and second
Electric 16 face contact of adhesive layer can not also use changeover portion 108 to go to make up difference in height, but will be arranged among conductive metal sheet 18
With ladder section, so that the both ends of conductive metal sheet 18 have difference in height, at this time in fixed conductive metal sheet 18, it is necessary to right
Both ends positioned at different height distinguish, when according to changeover portion 108 if be not necessarily to setting position to conductive metal sheet 18
It distinguishes.
In one embodiment provided by the invention, it is preferable that conductive metal sheet 18 and bonding wire 20 with partly lead
After body chip 12 is connected, conductive metal sheet 18 and bonding wire 20 the surface of semiconductor chip 12 projection in the plane
Without overlapping region.
In this embodiment, due to needing to avoid the connection between conductive metal sheet 18 and bonding wire 20, the two is avoided
A series of the problems such as influences occurred after being connected, such as short circuit, thus conductive metal sheet 18 and bonding wire 20 with partly lead
After body chip 12 is connected, need to guarantee conductive metal sheet 18 and bonding wire 20 in plane where the surface of semiconductor chip 12
On projection without overlapping region so that conductive metal sheet 18 can not be contacted with bonding wire 20, at the same also there is no contact can
It can property.
In one embodiment provided by the invention, it is preferable that the surface area at the both ends of conductive metal sheet 18 is respectively greater than
The surface area of first conductive adhesion layer 14 and the second conductive adhesion layer 16, so that the both ends of conductive metal sheet 18 respectively can be complete
Cover the first conductive adhesion layer 14 and the second conductive adhesion layer 16.
In this embodiment, the surface area at the both ends of conductive metal sheet 18 is respectively greater than the first conductive adhesion layer 14 and
The surface area of two conductive adhesion layers 16 is led with the first conductive adhesion layer 14 and second at the both ends of conductive metal sheet 18 respectively in this way
When electric adhesive layer 16 is connected, can make the both ends of conductive metal sheet 18 can be completely covered respectively the first conductive adhesion layer 14 and
Second conductive adhesion layer 16 guarantees that connection effect is stablized, and prevents the first conductive adhesion layer 14 and second for having exposing conductive viscous
It connects layer 16 and influences whether other elements.
In one embodiment provided by the invention, it is preferable that the resistance value of conductive metal sheet 18 and semiconductor chip 12
Performance number is positively correlated.
In this embodiment, it needs to consider the performance number of semiconductor chip 12 when selecting conductive metal sheet 18, and leads
The resistance value of electric metal piece 18 and the performance number of semiconductor chip 12 are positively correlated, in order to can be according to the performance number of semiconductor chip 12
Suitable conductive metal sheet 18 is chosen, so that semiconductor package has stronger current carrying capacity.
In one embodiment provided by the invention, it is preferable that the first conductive adhesion layer 14 is following any or combination: being led
Electric glue, brazing material or eutectic wlding material；And/or second conductive adhesion layer 16 be it is following any or combination: conducting resinl, soldering material
Material or eutectic wlding material；And/or third conductive adhesion layer 24 is following any or combination: conducting resinl, brazing material or eutectic weldering
Material.
In this embodiment, the first conductive adhesion layer 14 and/or the second conductive adhesion layer 16 and/or third conductive adhesion layer
24 be respectively set to it is any in conducting resinl, brazing material or eutectic wlding material or combination, as long as can be realized connected component it
Between mechanical connection and electrically conducting purpose.And the first conductive adhesion layer 14, the second conductive adhesion layer 16 and third are led
Electric adhesive layer 24 can choose identical or different material.
It is contemplated that ground, the material according to selected by conductive adhesion layer can be by conductive sheet adhesive technique, unleaded in connection
Soldering processes or eutectic Welding realize the connection between two components.
In one embodiment provided by the invention, it is preferable that the first conductive adhesion layer 14, the second conductive adhesion layer 16 and
Third conductive adhesion layer 24 is respectively continuous laminated structure or the convex block structure for discrete distribution.
In this embodiment, the first conductive adhesion layer 14, the second conductive adhesion layer 16 and third conductive adhesion layer 24 are distinguished
For continuous laminated structure or be discrete distribution convex block structure.Conductive adhesion layer can be continuous laminated structure, simultaneously
Due to needing to consider encapsulation stress, so that conductive adhesion layer is also possible to convex block structure (for example, array of discrete distribution
Convex block structure) or other shapes, for the purpose of reducing the encapsulation stress between semiconductor chip 12 and conductive metal sheet 18.
In the description of this specification, the orientation or positional relationship of the instructions such as term " on ", "lower" is based on shown in attached drawing
Orientation or positional relationship, be merely for convenience of description of the present invention and simplification of the description, rather than the device of indication or suggestion meaning
Or element must have a particular orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention；
Term " connection ", " installation ", " fixation " etc. shall be understood in a broad sense, for example, " connection " may be a fixed connection, being also possible to can
Dismantling connection, or be integrally connected；It can be directly connected, it can also be indirectly connected through an intermediary.For this field
For those of ordinary skill, the specific meanings of the above terms in the present invention can be understood according to specific conditions.
In the description of this specification, the description of term " one embodiment ", " some embodiments ", " specific embodiment " etc.
Mean that particular features, structures, materials, or characteristics described in conjunction with this embodiment or example are contained at least one reality of the invention
It applies in example or example.In the present specification, schematic expression of the above terms are not necessarily referring to identical embodiment or reality
Example.Moreover, description particular features, structures, materials, or characteristics can in any one or more of the embodiments or examples with
Suitable mode combines.
These are only the preferred embodiment of the present invention, is not intended to restrict the invention, for those skilled in the art
For member, the invention may be variously modified and varied.All within the spirits and principles of the present invention, it is made it is any modification,
Equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (17)
1. a kind of method for packaging semiconductor, which is characterized in that the method for packaging semiconductor includes:
The drain electrode of semiconductor chip is set in the main body of lead frame；
The first conductive adhesion layer is set on the first pin of the lead frame, is arranged on the source electrode of the semiconductor chip
Second conductive adhesion layer；
One end of conductive metal sheet is connected by first conductive adhesion layer with first pin, by the conductive gold
The other end for belonging to piece is connected by second conductive adhesion layer with the source electrode of the semiconductor chip；
The grid of the semiconductor chip is connected with the second pin of the lead frame by bonding wire；
Encapsulate the semiconductor chip, the conductive metal sheet, the bonding wire and the part lead frame.
2. method for packaging semiconductor according to claim 1, which is characterized in that the drain electrode by semiconductor chip is arranged
Step in the main body of lead frame, comprising:
Third conductive adhesion layer is set in the main body of the lead frame；
The drain electrode of the semiconductor chip is fitted on the third conductive adhesion layer.
3. method for packaging semiconductor according to claim 1, which is characterized in that set the drain electrode of semiconductor chip described
It is placed in the main body of lead frame before step, further includes:
The lead frame is customized according to the size of the semiconductor chip.
4. method for packaging semiconductor according to claim 3, which is characterized in that the ruler according to the semiconductor chip
The step of very little customization lead frame, comprising:
When making the lead frame, the surface area of the first pin of the lead frame is set greater than the lead frame
Second pin surface area.
5. method for packaging semiconductor according to claim 3, which is characterized in that the ruler according to the semiconductor chip
The step of very little customization lead frame, comprising:
When making the lead frame, the first pin and second pin of the lead frame are passed through into acclivitous changeover portion
It is connected with the main body of the lead frame, so that first conductive adhesion layer and second conductive adhesion layer are located at together
In one plane.
6. method for packaging semiconductor according to any one of claim 1 to 5, which is characterized in that
After the conductive metal sheet is connected with the semiconductor chip with the bonding wire, the conductive metal sheet with
The bonding wire the surface of the semiconductor chip projection in the plane without overlapping region.
7. method for packaging semiconductor according to claim 2, which is characterized in that
First conductive adhesion layer is following any or combination: conducting resinl, brazing material or eutectic wlding material；And/or
Second conductive adhesion layer is following any or combination: conducting resinl, brazing material or eutectic wlding material；And/or
The third conductive adhesion layer is following any or combination: conducting resinl, brazing material or eutectic wlding material.
8. a kind of semiconductor package, which is characterized in that the semiconductor package includes:
Lead frame；
The drain electrode of semiconductor chip, the semiconductor chip is set in the main body of the lead frame, the semiconductor chip
Periphery without departing from the lead frame main body；
First conductive adhesion layer and the second conductive adhesion layer are separately positioned on the first pin of the lead frame and described partly lead
On the source electrode of body chip；
One end of conductive metal sheet, the conductive metal sheet is connected by first conductive adhesion layer with first pin
It connects, the other end of the conductive metal sheet is connected by second conductive adhesion layer with the source electrode of the semiconductor chip
It connects.
9. semiconductor package according to claim 8, which is characterized in that the semiconductor package further include:
Bonding wire, one end of the bonding wire are connected with the grid of the semiconductor chip, the bonding wire it is another
One end is connected with the second pin of the lead frame；
Encapsulating housing, the encapsulating housing is by the part lead frame, the semiconductor chip, the conductive metal sheet and institute
Bonding wire is stated to be packaged.
10. semiconductor package according to claim 8, which is characterized in that the semiconductor package further include:
Third conductive adhesion layer, the third conductive adhesion layer be arranged in the lead frame main body and the semiconductor chip
Between.
11. semiconductor package according to claim 8, which is characterized in that
The surface area of first pin of the lead frame is greater than the surface area of the second pin of the lead frame.
12. semiconductor package according to claim 8, which is characterized in that the semiconductor package further include:
Changeover portion, the changeover portion are to be obliquely installed, and the changeover portion is by the first pin and second pin of the lead frame
It is connected with the main body of the lead frame, so that first conductive adhesion layer and second conductive adhesion layer are located at together
In one plane.
13. semiconductor package according to claim 9, which is characterized in that
After the conductive metal sheet is connected with the semiconductor chip with the bonding wire, the conductive metal sheet with
The bonding wire the surface of the semiconductor chip projection in the plane without overlapping region.
14. semiconductor package according to claim 9, which is characterized in that
The surface area at the both ends of the conductive metal sheet is respectively greater than first conductive adhesion layer and second conductive adhesive
The surface area of layer, so that first conductive adhesion layer and described the can be completely covered in the both ends of the conductive metal sheet respectively
Two conductive adhesion layers.
15. semiconductor package according to claim 9, which is characterized in that
The resistance value of the conductive metal sheet and the performance number of the semiconductor chip are positively correlated.
16. semiconductor package according to claim 10, which is characterized in that
First conductive adhesion layer is following any or combination: conducting resinl, brazing material or eutectic wlding material；And/or
Second conductive adhesion layer is following any or combination: conducting resinl, brazing material or eutectic wlding material；And/or
The third conductive adhesion layer is following any or combination: conducting resinl, brazing material or eutectic wlding material.
17. semiconductor package according to claim 10, which is characterized in that
First conductive adhesion layer, second conductive adhesion layer and the third conductive adhesion layer are respectively continuous sheet
Structure or convex block structure for discrete distribution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811605514.4A CN109545697A (en) | 2018-12-26 | 2018-12-26 | Method for packaging semiconductor and semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811605514.4A CN109545697A (en) | 2018-12-26 | 2018-12-26 | Method for packaging semiconductor and semiconductor package |
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| CN109545697A true CN109545697A (en) | 2019-03-29 |
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| CN201811605514.4A Pending CN109545697A (en) | 2018-12-26 | 2018-12-26 | Method for packaging semiconductor and semiconductor package |
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| CN (1) | CN109545697A (en) |
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