CN208111419U - A kind of encapsulating structure of chip - Google Patents
A kind of encapsulating structure of chip Download PDFInfo
- Publication number
- CN208111419U CN208111419U CN201820423595.5U CN201820423595U CN208111419U CN 208111419 U CN208111419 U CN 208111419U CN 201820423595 U CN201820423595 U CN 201820423595U CN 208111419 U CN208111419 U CN 208111419U
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- Prior art keywords
- chip
- packaged
- contact jaw
- back side
- weld pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Technical solutions of the utility model disclose a kind of encapsulating structure of chip; technical solutions of the utility model are packaged protection to chip to be packaged by package substrate; the package substrate has receiving hole; the chip to be packaged is fixed in the receiving hole; the intensity of chip to be packaged can be improved; the weld pad of chip to be packaged can be connect by its back side interconnection architecture with external circuit, or be connect by first contact jaw, the second contact jaw and interconnection circuit on package substrate surface with external circuit.
Description
Technical field
The utility model relates to chip encapsulation technology fields, more specifically, being related to a kind of encapsulating structure of chip.
Background technique
With science and technology be constantly progressive, more and more electronic equipments be widely used in daily life with
And in work, huge convenience is brought for daily life and work, becomes the indispensable weight of current people
Want tool.Electronic equipment realizes that the main component of various functions is chip, in order to guarantee the reliability of chip, service life and
External factor is avoided to damage, chip needs are packaged protection.
In the prior art, it usually directlys adopt packaging plastic to be packaged chip, forms encapsulating structure.In this way, inconvenient
It is connected in the encapsulating structure of chip with external circuit.
Utility model content
To solve the above-mentioned problems, technical solutions of the utility model provide a kind of encapsulating structure of chip, are convenient for chip
Encapsulating structure connected with external circuit.
To achieve the goals above, the utility model provides the following technical solutions：
A kind of encapsulating structure of chip, the encapsulating structure include：
Package substrate, the package substrate include opposite first surface and second surface；Through the first surface
And the receiving hole of the second surface；
Chip to be packaged, the chip to be packaged are fixed in the receiving hole, and the chip to be packaged has opposite
Front and the back side, the weld pad that front has functional unit and connect with the functional unit；
Wherein, the first surface is provided with the first contact jaw, and the second surface is provided with the second contact jaw, and described
Two contact jaws are provided in the package substrate for connecting external circuit for connecting first contact jaw and described second
The interconnection circuit of contact jaw, at least partly described weld pad are connect with first contact jaw；Alternatively, the back of the chip to be packaged
Face is provided with back side interconnection architecture, and at least partly described weld pad is connect by the back side interconnection architecture with the external circuit.
Optionally, in above-mentioned encapsulating structure, for the chip to be packaged, front has multiple weld pads,
Front is close to the first surface, and the back side is close to the second surface.
Optionally, in above-mentioned encapsulating structure, the back side of the chip to be packaged has hatch frame, the hatch frame
For exposing the weld pad；
The back side interconnection architecture is connect by the hatch frame with the weld pad that the hatch frame exposes, described
Back side interconnection architecture with external circuit for connecting.
Optionally, in above-mentioned encapsulating structure, the hatch frame is used for weld pad described in exposed portion, welds described in the part
Pad by the back side interconnection architecture with external circuit for being connected；
Weld pad described in another part with described first connects by conducting wire or positioned at the conductive interconnections layer of the first surface
Contravention connection.
Optionally, in above-mentioned encapsulating structure, the hatch frame is for exposing all weld pads, all weld pads
For being connected by the back side interconnection architecture with external circuit.
Optionally, in above-mentioned encapsulating structure, the hatch frame includes multiple through-holes, the corresponding dew of each described through-hole
A weld pad out.
Optionally, in above-mentioned encapsulating structure, the through-hole is straight hole or trapezoidal hole.
Optionally, in above-mentioned encapsulating structure, fluted, the depth of the groove is arranged in the back side of the chip to be packaged
Less than the thickness of the chip to be packaged, the through-hole is located in the groove.
Optionally, in above-mentioned encapsulating structure, all weld pads pass through conducting wire or leading positioned at the first surface
Electric interconnection layer is connect with first contact jaw.
Optionally, in above-mentioned encapsulating structure, the front of the chip to be packaged is flushed with the first surface.
Optionally, in above-mentioned encapsulating structure, the second surface of the package substrate is covered with the first encapsulation glue-line, described
First encapsulation glue-line also fills up the gap between the chip to be packaged and the receiving hole, for consolidating the chip to be packaged
It is scheduled in the receiving hole；
When the second surface is provided with the second contact jaw, the first encapsulation glue-line covers second contact jaw,
The first encapsulation glue-line exposes second contact jaw by milled processed；
When the back side of the chip to be packaged is provided with back side interconnection architecture, the back side interconnection architecture include for and
The third contact jaw of external circuit connection, the first encapsulation glue-line cover the third contact jaw, the first encapsulation glue-line
Expose the third contact jaw by milled processed.
Optionally, in above-mentioned encapsulating structure, the first surface of the package substrate is covered with the second encapsulation glue-line；
When at least partly described weld pad is connect with first contact jaw, the weld pad is connect by conducting wire with described first
Contravention connection, the second encapsulation glue-line cover the conducting wire, or, the weld pad passes through the conduction positioned at the first surface
Interconnection layer is connect with first contact jaw, and the second encapsulation glue-line covers the conductive interconnections layer.
As can be seen from the above description, in the chip-packaging structure and packaging method that technical solutions of the utility model provide, lead to
It crosses package substrate and protection is packaged to chip to be packaged, the package substrate has receiving hole, and the chip to be packaged is fixed
In the receiving hole, the intensity of chip to be packaged can be improved, the weld pad of chip to be packaged can mutually be coupled by its back side
Structure is connect with external circuit, or passes through first contact jaw, the second contact jaw and interconnection circuit on package substrate surface and outer
Portion's circuit connection.
Detailed description of the invention
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is only
It is the embodiments of the present invention, for those of ordinary skill in the art, without creative efforts, also
Other attached drawings can be obtained according to the attached drawing of offer.
Fig. 1 is a kind of schematic diagram of the encapsulating structure of chip provided by the embodiment of the utility model；
A kind of Fig. 2 a structural schematic diagrams of chip to be packaged provided by the embodiment of the utility model；
Fig. 2 b is the structural schematic diagram of another kind chip to be packaged provided by the embodiment of the utility model；
Fig. 3 is the package structure diagram of another chip provided by the embodiment of the utility model；
Fig. 4 is the schematic diagram of the encapsulating structure of another chip provided by the embodiment of the utility model；
Fig. 5 is the schematic diagram of the encapsulating structure of another chip provided by the embodiment of the utility model；
Fig. 6 is the schematic diagram of the encapsulating structure of another chip provided by the embodiment of the utility model；
Fig. 7-Figure 15 is a kind of flow diagram of packaging method provided by the embodiment of the utility model；
Figure 16-Figure 18 is the flow diagram of another packaging method provided by the embodiment of the utility model；
Figure 19-Figure 26 is the flow diagram of another packaging method provided by the embodiment of the utility model；
Figure 27-Figure 32 is the flow diagram of another packaging method provided by the embodiment of the utility model；
Figure 33-Figure 38 is the flow diagram of another packaging method provided by the embodiment of the utility model；
Figure 39-Figure 41 is a kind of flow diagram of chip manufacture method provided by the embodiment of the utility model；
Figure 42-Figure 49 is a kind of flow diagram of chip manufacture method provided by the embodiment of the utility model.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model
Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole
Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
Every other embodiment obtained, fall within the protection scope of the utility model.
To keep the above objects, features, and advantages of the utility model more obvious and easy to understand, with reference to the accompanying drawing and have
Body embodiment is described in further detail the utility model.
With reference to Fig. 1, Fig. 1 is a kind of schematic diagram of the encapsulating structure of chip provided by the embodiment of the utility model, the encapsulation
Structure includes：Package substrate 11, the package substrate 11 include opposite first surface and second surface；Through described first
The receiving hole 111 of surface and the second surface；Chip 12 to be packaged, the chip 12 to be packaged are fixed on the receiving hole
In 111, the chip 12 to be packaged have opposite front and the back side, front have functional unit 121 and with it is described
The weld pad 122 that functional unit 121 connects.
In the embodiment shown in fig. 1, the first surface is provided with the first contact jaw 112, the second surface setting
There is the second contact jaw 113, second contact jaw 113 is provided in the package substrate 11 and is used for for connecting external circuit
Connect the interconnection circuit 114 of first contact jaw 112 and second contact jaw 113.Weld pad 122 shown in a part with it is described
The connection of first contact jaw 112, with by the interconnection circuit 114 being connect with first contact jaw 112 and the second contact jaw 113 and
External circuit connection.The back side of the chip to be packaged 12 is provided with back side interconnection architecture, and weld pad 122 described in another part passes through
The back side interconnection architecture is connect with the external circuit.Fig. 2 a
For the chip 12 to be packaged, front has multiple weld pads 122, and front is close to first table
Face, the back side is close to the second surface.Multiple weld pads 122 can be divided into two column and be separately positioned on the functional unit
121 two sides, or the surrounding of the functional unit 121 is uniformly set.Multiple weld pads can be designed according to demand
122 are not especially limited this in the positive layout of the chip 12 to be packaged, impracticable new embodiment.
Optionally, the front that the chip 12 to be packaged is arranged is flushed with the first surface.Thus it is possible, on the one hand, being convenient for
Chip 12 to be packaged is fixed in the receiving hole 111 in encapsulation process, on the other hand, can according to circuit demand for interconnection,
Convenient for forming conductive interconnections layer 13, pass through the connection of conductive interconnections layer 13 at least partly weld pad 122 and the first contact jaw 112.
With reference to Fig. 2 a, a kind of Fig. 2 a structural schematic diagrams of chip to be packaged provided by the embodiment of the utility model should be to
Encapsulating chip 12 has back side interconnection architecture.The back side of the chip to be packaged 12 has hatch frame 21, the hatch frame
21 for exposing the weld pad 122, can design the hatch frame 21 for described in exposed portion according to circuit demand for interconnection
Weld pad 122 or all weld pad 122.The back side interconnection architecture passes through the hatch frame 21 and the hatch frame 21
The weld pad 122 exposed connects, and the back side interconnection architecture with external circuit for connecting.It covers in the front of chip 12 to be packaged
It is stamped protective layer 124,124 covering function unit 121 of protective layer.In which, if having at least partly weld pad 122 need and
The connection of first contact jaw 112 needs the position of the corresponding at least partly weld pad 122 of protective layer 124 when carrying out chip package
Setting has opening, exposes the positive at least partly weld pad 122, the opening is not shown in Fig. 2 b.
In chip 12 to be packaged shown in Fig. 2 a, the hatch frame 21 includes multiple through-holes 211, each described through-hole
211 it is corresponding expose the weld pads 122, optionally, the through-hole 211 is straight hole or trapezoidal hole, in mode shown in Fig. 2 a,
Shown through-hole 211 is trapezoidal hole.The through-hole directly can be formed by etching technics at the back side of the chip 12 to be packaged
211, in order to reduce etching difficulty, guarantee the etching quality of through-hole 211, the back side setting of the chip 12 to be packaged is fluted
212, the depth of the groove 212 is less than the thickness of the chip 12 to be packaged, and the through-hole 211 is located in the groove 212.
The back side interconnection architecture includes wiring layer 23 and third contact jaw 123 again, and the third contact jaw 123 can be with
For tin ball.Specifically, the back side of the chip to be packaged 12 is covered with insulating layer 22, insulating layer 22 covers the side of hatch frame 21
Wall, and the bottom of corresponding opening structure 21 has window area, to expose the corresponding weld pad 122.Wiring layer 23 is located at again
22 surface of insulating layer is connected in the bottom of hatch frame 21 and corresponding weld pad 122, then wiring layer 23 extends to hatch frame 21
It is external.23 surface of wiring layer is covered with solder mask 24 again, and 24 surface of solder mask has opening, and third contact jaw 123 is opened by this
Mouth and again wiring layer 23 connect.
When the weld pad 122 shown in a part is connected by the back side interconnection architecture with external circuit, the hatch frame
21 for exposing weld pad 122 described in the part, and weld pad 122 described in the part is used to pass through the back side interconnection architecture and external electrical
Road connection；Weld pad 122 described in another part passes through the conductive interconnections layer 13 and first contact jaw positioned at the first surface
112 connections.In other embodiments, as shown in figure 3, Fig. 3 is the encapsulation of another chip provided by the embodiment of the utility model
Structural schematic diagram, weld pad 122 described in another part can also be connect by conducting wire 16 with first contact jaw 112.
Optionally, shown in Fig. 2 a in chip 12 to be packaged, the hatch frame 21 can also be set for exposing all institutes
Weld pad 122 is stated, all weld pads 122 are used to connect by the back side interconnection architecture with external circuit, at this point, the encapsulation
Structure is as shown in figure 4, Fig. 4 is the schematic diagram of the encapsulating structure of another chip provided by the embodiment of the utility model, the envelope
In assembling structure, all weld pads 122 are connected by back side interconnection architecture with the external circuit.At this point, without in the encapsulation
First contact jaw, the second contact jaw and interconnection circuit are set on substrate.
In the utility model embodiment, all weld pads 122 and the connection of the first contact jaw 112 can also be set, in turn
It is connect by interconnection circuit 114 and the second contact jaw 113 with external circuit.At this point, the structure of the chip to be packaged 12 is as schemed
Shown in 2b, Fig. 2 b is the structural schematic diagram of another kind chip to be packaged provided by the embodiment of the utility model, the core to be packaged
In piece 12, no setting is required back side interconnection architecture.It is identical as mode shown in Fig. 2 a, the front covering matcoveredn of chip 12 to be packaged
124, protective layer 124 covers the functional unit 121.In which, all weld pads 122 need and the connection of the first contact jaw 112,
When carrying out chip package, needs the position of the corresponding each weld pad 122 of protective layer 124 that there is opening, expose positive weld pad
The opening is not shown in 122, Fig. 2 b.
When all weld pads 122 and the first contact jaw 112 connect, as shown in Figure 5 and Figure 6, Fig. 5 is the utility model
The schematic diagram of the encapsulating structure for another chip that embodiment provides, Fig. 6 are another core provided by the embodiment of the utility model
The schematic diagram of the encapsulating structure of piece, all weld pads 122 pass through conducting wire 16 or the conductive interconnections positioned at the first surface
Layer 13 is connect with first contact jaw 112.
In encapsulating structure described in the utility model embodiment, the second surface of the package substrate 11 is covered with the first encapsulation
Glue-line 14, the first encapsulation glue-line 14 also fill up the gap between the chip to be packaged 12 and the receiving hole 111, are used for
The chip 12 to be packaged is fixed in the receiving hole 111.When the second surface is provided with the second contact jaw 113,
The first encapsulation glue-line 14 covers second contact jaw 113, and the first encapsulation glue-line 14 exposes institute by milled processed
State the second contact jaw 113.When the back side of the chip 12 to be packaged is provided with back side interconnection architecture, the back side interconnection architecture
Including the third contact jaw 123 for connecting with external circuit, the first encapsulation glue-line 14 covers the third contact jaw
123, the first encapsulation glue-line 14 exposes the third contact jaw 123 by milled processed.
In encapsulating structure described in the utility model embodiment, the first surface of the package substrate 11 is covered with the second encapsulation
Glue-line 15.
When at least partly described weld pad 122 is connect with first contact jaw 112, the weld pad 122 passes through conducting wire 16
It being connect with first contact jaw 112, the second encapsulation glue-line 15 covers the conducting wire 16, or, the weld pad 122 passes through
Conductive interconnections layer 13 positioned at the first surface is connect with first contact jaw 112, and the second encapsulation glue-line 15 covers
The conductive interconnections layer 13.
To avoid short circuit, each first contact jaw 112 is set and is correspondingly connected with a weld pad 122, each first contact jaw
112 are connected by a corresponding interconnection circuit 114 and corresponding second contact jaw 113.
As can be seen from the above description, there is two ways in encapsulating structure described in the utility model embodiment：
First way is that the setting first surface is provided with the first contact jaw 112, and the second surface is provided with the
Two contact jaws 113, second 113 ends of contact are provided in the package substrate 11 for connecting for connecting external circuit
The interconnection circuit 114 of first contact jaw 112 and second contact jaw 113, at least partly weld pad 122 and described the
The connection of one contact jaw 112.Which includes：Part of solder pads 122 and the connection of the first contact jaw 112, are connected with realizing with external circuit
It connects, another part weld pad 122 is connected by back side interconnection architecture with external circuit；Alternatively, all weld pads 122 and the first contact jaw
112 connections, are connected with realizing with external circuit.
The second way is that the back side of the chip 12 to be packaged is arranged to be provided with back side interconnection architecture, at least partly described
Weld pad 122 is connect by the back side interconnection architecture with the external circuit.Which includes：Part of solder pads 122 passes through the back side
Interconnection architecture is connect with external circuit, and another part weld pad 122 and the connection of the first contact jaw 112 are connected with realizing with external circuit
It connects；Alternatively, all weld pads 122 are connected by back side interconnection architecture with external circuit.
That is, there are three types of the mode connected in encapsulating structure described in the embodiment of the present application with external circuit has：Mode
First is that a part of weld pad 122 and the connection of the first contact jaw 112, another part weld pad 122 pass through back side interconnection architecture and external electrical
Road connection；Mode is second is that all weld pads 122 and the connection of the first contact jaw 112；Mode is third is that all weld pads 122 are interconnected by the back side
Structure is connected with external circuit.
It is to be packaged with the continuous diminution and the continuous improvement of 12 integrated level of chip to be packaged of 12 size of chip to be packaged
The size of 12 front weld pad 122 of chip is smaller and smaller, and density is increasing, forms the back side by TSV technique completely and is mutually coupled
Structure connects the third contact jaw 123 at 12 back side of all weld pads 122 and chip to be packaged, due to the gap of third contact jaw 123
It is smaller, be not easy to circuit interconnection, and completely connect all weld pads 122 and the first contact jaw 112, due to 122 gap of weld pad compared with
It is small, and it is not easy to circuit interconnection.Therefore interconnected for the ease of circuit, a part of weld pad 122 is set in the utility model embodiment
It is connected with the first contact jaw 112, another part weld pad 122 is connected by back side interconnection architecture with external circuit.
In the utility model embodiment, the machinery that the mechanical strength of setting package substrate 11 is greater than chip 12 to be packaged is strong
Degree, in this way, compared with the existing technology, reduction processing further can be carried out to chip 12 to be packaged, it is bigger by mechanical strength
11 pairs of encapsulation chips 12 of package substrate be packaged protection, can guarantee encapsulating structure have preferable mechanical strength, simultaneously
Reduce the thickness of encapsulating structure.
Optionally, first surface is additionally provided at least the first solder terminal, and first solder terminal is plug-in for binding
Element, the plug-in element include one in resistance, capacitor and inductance or multiple.Second surface is additionally provided with and first
One-to-one second solder terminal of solder terminal, the first weld pad terminal and second solder terminal pass through package substrate
Wired circuit connection inside 11, the second solder terminal with external circuit for connecting.In the utility model Figure of description not
First solder terminal, the second solder terminal, plug-in element and wired circuit are shown.In this way, encapsulated circuit can be multiplexed
Plate binds plug-in element, improves integrated level.Plug-in element can be encapsulated in the second encapsulation glue-line 15.
As can be seen from the above description, in encapsulating structure described in the utility model embodiment, envelope is treated by package substrate 11
Cartridge chip 12 is packaged protection, and the package substrate 11 has receiving hole 111, and the chip 12 to be packaged is fixed on the appearance
It receives in hole 111, the intensity of chip 12 to be packaged can be improved, the weld pad 122 of chip 12 to be packaged can be interconnected by its back side
Structure is connect with external circuit, or by first contact jaw 112 on 11 surface of package substrate, the second contact jaw 113 and mutually
Connection circuit 114 is connect with external circuit.Relative to directly in 12 front of chip to be packaged or back side setting strengthening course to increase
The appearance of package substrate 11 is directly arranged in chip 12 to be packaged by the mode of 12 mechanical strength of chip to be packaged, the embodiment of the present application
It receives in hole 111, chip 12 to be packaged can be further greatly lowered in package substrate 11 and the setting of 12 same layer of chip to be packaged
Thickness.
Based on the above embodiment, another embodiment of the utility model additionally provides a kind of packaging method, above-mentioned for making
Encapsulating structure described in embodiment, as shown in Fig. 7-Figure 15, Fig. 7-Figure 15 is provided the packaging method for the utility model embodiment
A kind of packaging method flow diagram, which includes：
Step S11：As shown in fig. 7, providing a package substrate 11.
The package substrate 11 includes opposite first surface and second surface；The package substrate 11 is divided into multiple
Chip bonding region has cutting channel 10 between two neighboring chip bonding region.The chip bonding region includes：Run through
The receiving hole 111 of the first surface and the second surface.
Step S12：As shown in Fig. 8-Figure 14, a chip 12 to be packaged is set in each receiving hole 111.
The chip to be packaged 12 have opposite front and the back side, front have functional unit 121 and with institute
State the weld pad 122 of the connection of functional unit 121.
In the step, the chip 12 to be packaged that is arranged in each receiving hole 111 includes：
Firstly, as shown in figure 8, the first surface in the package substrate 11 is bonded adhesive film 31.
Then, the package substrate 11 is horizontally arranged, first surface is arranged downward.
As shown in fig. 9 again, the chip to be packaged 12 is placed in the receiving hole 111, the chip 12 to be packaged is logical
The adhesive film 31 is crossed to be fixed in the receiving hole 111.Specifically, being placed in the receiving hole 111 described to be packaged
Chip 12 includes：The front of the chip to be packaged 12 is set close to the first surface, the back side close to the second surface,
As shown in figure 9, chip 12 to be packaged is horizontally arranged, and its face down is arranged.Wherein, the front of the chip to be packaged 12
With multiple weld pads 122.The front of the chip to be packaged 12 is flushed with the first surface of the package substrate 11.
In the packaging method, for any chip bonding region, the first surface is provided with the first contact jaw
112, the second surface is provided with the second contact jaw 113, and second contact jaw 113 is for connecting external circuit, the envelope
The interconnection circuit 114 for connecting first contact jaw 112 and second contact jaw 113 is provided in dress substrate 11, until
Weld pad 122 described in small part is connect with first contact jaw 112.And to be provided with the back side mutual at the back side of the chip to be packaged 12
It is coupled structure, at least partly described weld pad 122 is connect by the back side interconnection architecture with the external circuit.The namely encapsulation
In method, a part of weld pad 122 and the connection of the first contact jaw 112, to connect with external circuit, another part weld pad 122 passes through
Back side interconnection architecture is connected with external circuit.
As shown in Fig. 2, the back side of the setting chip 12 to be packaged has hatch frame 21, the hatch frame 21 is used for
Expose the weld pad 122；The back side interconnection architecture is exposed by the hatch frame 21 with the hatch frame 21 described
Weld pad 122 connects, and the back side interconnection architecture with external circuit for connecting.It can be according to the circuit Networking Design hatch frame
Exposed portion weld pad 122 or whole weld pad 122 in packaging method shown in Fig. 7-Figure 15, need to design the hatch frame 21
For weld pad 122 described in exposed portion, weld pad 122 described in the part is used to connect by the back side interconnection architecture and external circuit
It connects, places the chip to be packaged in the receiving hole at this point, described and include：Weld pad described in another part is passed through into conducting wire 16
Or the conductive interconnections layer 13 of the first surface positioned at the package substrate connects.
As described in above-described embodiment, the hatch frame 21 includes multiple through-holes 211, each described through-hole 211 is corresponding
Expose a weld pad 122.The through-hole 211 is straight hole or trapezoidal hole.The back side of the chip to be packaged 12 is provided with
Groove 212, the depth of the groove 212 are less than the thickness of the chip 12 to be packaged, and the through-hole 211 is located in the groove
212。
The step further includes：As shown in Figure 10 and Figure 11, the first encapsulation is formed in the second surface of the package substrate 11
Glue-line 14, the first encapsulation glue-line 14 also fill up the gap between the chip to be packaged 12 and the receiving hole 111, are used for
The chip 12 to be packaged is fixed in the receiving hole 111.
When the second surface is provided with the second contact jaw 113, the first encapsulation glue-line 14 covers described second and connects
Contravention 113, the first encapsulation glue-line 14 expose second contact jaw 114 by milled processed.That is, forming first
After encapsulating glue-line 14, the second contact jaw 113 is completely covered in encapsulation glue-line 14, then by milled processed, removes certain thickness envelope
Assembling structure layer 14 and the second contact jaw 113.
When the back side of the chip 12 to be packaged is provided with back side interconnection architecture, the back side interconnection architecture includes being used for
The third contact jaw 123 connected with external circuit, the first encapsulation glue-line 14 expose the third by milled processed and contact
End 123.Equally, after forming the first encapsulation glue-line 14, third contact jaw 123 is completely covered in encapsulation glue-line 14, then by grinding
Reason, removes certain thickness encapsulating structure layer 14 and third contact jaw 123.
Later, as shown in figure 12, after the first encapsulation glue-line 14 solidifies, first surface is horizontally arranged upward, removal is viscous
Film 31 is tied, then as shown in figure 13, conductive interconnections layer 13 is formed in first surface, by preset a part of weld pad 122 and first
Contact jaw 112 connects.Conductive interconnections layer 13 can be the metal layer with setting patterning.
The step further includes：As shown in figure 14, further include：Before dividing the package substrate 11, in the encapsulation base
The first surface of plate 11 forms the second encapsulation glue-line 15.When at least partly described weld pad 122 is connect with first contact jaw 112
When, the weld pad 122 is connect by conducting wire 16 with first contact jaw 112, and the second encapsulation glue-line 15 covers described lead
Line 16, or, the conductive interconnections layer 13 and first contact jaw 112 that the weld pad is located at the first surface by 122 connect
It connects, the second encapsulation glue-line 15 covers the conductive interconnections layer 13.
Step S13：As shown in figure 15, the package substrate 11 is divided based on the cutting channel 10, forms multiple encapsulation
Structure.
The package substrate 11 is cut into the encapsulating structure 11 of multiple small sizes, and the package substrate 11 of each small size includes
One chip bonding region.Each encapsulating structure includes a chip 12 to be packaged and a chip bonding region.Finally
Form encapsulating structure as shown in Figure 1.
With reference to Figure 16-Figure 18, Figure 16-Figure 18 is that the process of another packaging method provided by the embodiment of the utility model is shown
It is intended to, packaging method packaging method difference corresponding with encapsulating structure shown in Fig. 1 is, replaces conductive interconnection using conducting wire 16
The preset a part of weld pad 122 of 13 connection of layer and the first contact jaw 112, ultimately form encapsulating structure as shown in Figure 3, method
Process can correspond to the description of the corresponding packaging method of the encapsulating structure with reference to shown in Fig. 1, and details are not described herein.
With reference to Figure 19-Figure 26, Figure 19-Figure 26 is that the process of another packaging method provided by the embodiment of the utility model is shown
It is intended to, packaging method packaging method difference corresponding with encapsulating structure shown in Fig. 1 is that all weld pads 122 pass through the back side
Interconnection architecture is connected with external circuit.At this point, the hatch frame 21 is for exposing all weld pads 122, all welderings
Pad 122 is used to connect by the back side interconnection architecture with external circuit.So when package substrate 11 no setting is required first contact
The 112, second contact jaw 113 and third contact jaw 114 are held, ultimately forms encapsulating structure as shown in Figure 4, method flow can be with
The description of the corresponding corresponding packaging method of encapsulating structure with reference to shown in Fig. 1, details are not described herein.In other modes, it can also set
The chip to be packaged 12 is placed in the receiving hole 111 described in setting includes：All weld pads 122 are passed through into conducting wire 16
The conductive interconnections layer 13 (as shown in Figure 5) and described the of (as shown in Figure 6) or the first surface positioned at the package substrate 11
The connection of one contact jaw 112.At this point, the structure of chip to be packaged is as shown in Figure 2 b
With reference to Figure 27-Figure 32, Figure 27-Figure 32 is that the process of another packaging method provided by the embodiment of the utility model is shown
It is intended to, packaging method packaging method difference corresponding with encapsulating structure shown in Fig. 1 is, 12 structure of chip to be packaged is different,
Not set back side interconnection architecture, all weld pads 122 are connected by conductive interconnection layer 13 and corresponding first contact jaw 112, most
For end form at encapsulating structure as shown in Figure 5, method flow can correspond to the corresponding packaging method of the encapsulating structure with reference to shown in Fig. 1
Description, details are not described herein.
With reference to Figure 33-Figure 38, Figure 33-Figure 38 is that the process of another packaging method provided by the embodiment of the utility model is shown
It is intended to, packaging method packaging method difference corresponding with encapsulating structure shown in Fig. 5 is that all weld pads 122 pass through conducting wire
16 and corresponding first contact jaw 112 connection, ultimately form encapsulating structure as shown in FIG. 6, method flow can correspond to ginseng
The description of the corresponding packaging method of encapsulating structure shown in Fig. 5 is examined, details are not described herein.
As can be seen from the above description, in packaging method described in the utility model embodiment, for any chip bonding
Region, the first surface are provided with the first contact jaw 112, and the second surface is provided with the second contact jaw 113, and described second
Contact jaw 113 is provided in the package substrate 11 for connecting external circuit for connecting first contact jaw 112 and institute
The interconnection circuit 114 of the second contact jaw 113 is stated, at least partly described weld pad 122 is connect with first contact jaw 112；Alternatively,
The back side of the chip to be packaged 12 is provided with back side interconnection architecture, and at least partly described weld pad 122 is interconnected by the back side
Structure is connect with the external circuit.
Optionally, first surface is additionally provided at least the first solder terminal, and second surface is additionally provided with and the first welding ends
One-to-one second solder terminal of son, the first weld pad terminal and second solder terminal pass through inside package substrate 11
Wired circuit connection, the second solder terminal with external circuit for connecting.The encapsulation process can also include：Described
Plug-in element, the plug-in element and first solder terminal welding are bound in one surface, and the plug-in element includes resistance, electricity
Hold and inductance in one or it is multiple.When being provided with the second encapsulation glue-line, it is outer that the covering of the second encapsulation glue-line can be set
Hang element.
With reference to Figure 39-Figure 41, Figure 39-Figure 41 is a kind of process of chip manufacture method provided by the embodiment of the utility model
Schematic diagram, this method include：
Firstly, Figure 40 is Figure 39 in the sectional drawing in the direction P-P ' as shown in Figure 39 and Figure 40, a wafer 43, the crystalline substance are provided
Circle 43 includes multiple chip units 42, has cutting channel 41 between adjacent chips unit 42.Each chip unit 42 is used for shape
At the chip of a simple grain.The front covering matcoveredn 400 of wafer, protective layer 400 cover the positive function of each chip unit
It can unit 421 and weld pad 422.
Then, as shown in figure 41, wafer 41 is divided based on cutting channel 41, forms the chip of multiple simple grains.Each chip
Front include functional unit 421 and weld pad 422.
Chip to be packaged shown in Fig. 2 b can be prepared by production method shown in Figure 39-Figure 41.
With reference to Figure 42-Figure 49, Figure 42-Figure 49 is a kind of process of chip manufacture method provided by the embodiment of the utility model
Schematic diagram, this method include：
Firstly, Figure 43 is Figure 42 in the sectional drawing in the direction Q-Q ' as shown in Figure 42 and Figure 43, a wafer 53, the crystalline substance are provided
Circle 53 includes multiple chip units 52, has cutting channel 51 between adjacent chips unit 52.Each chip unit 52 is used for shape
At the chip of a simple grain.The front covering matcoveredn 500 of wafer, protective layer 500 cover the positive function of each chip unit
It can unit 521 and weld pad 522.
Then, as shown in figure 44, wafer 53 is fixed on 62 surface of loading plate by adhesive film 61.The front of wafer 53
Downward, it is horizontally arranged.
Again as shown in figure 45, hatch frame 70 is formed at the back side of wafer 53, for exposing a part or whole welderings
Pad 522.
Again as shown in figure 46, insulating layer 71 being formed at the back side of wafer 53, insulation 71 covers the side wall of hatch frame 70, and
Expose the weld pad 522 of 70 bottom of hatch frame.
Again as shown in figure 47, wiring layer 72 again, then wiring layer covering and hatch frame 70 are formed on the surface of insulating layer 71
The weld pad 522 of bottom connects, and extends to the outside of hatch frame 70.
Again as shown in figure 48, solder mask 73 being formed on 72 surface of wiring layer again, the solder mask 73 has opening,
The opening forms contact jaw 74, and contact jaw 74 is connect with the wiring layer again 73.
Finally, dividing wafer as shown in figure Figure 49 based on cutting channel 51, forming multiple simple grain chips.
Chip to be packaged shown in Fig. 2 a can be prepared by production method shown in Figure 42-Figure 49.
As can be seen from the above description, production method provided by the embodiment of the utility model can be used for making above-described embodiment
The encapsulating structure, production method simple process, low manufacture cost are packaged guarantor to chip to be packaged by package substrate
Shield, the package substrate have receiving hole, and the chip to be packaged is fixed in the receiving hole, and chip to be packaged can be improved
Intensity, the weld pad of chip to be packaged can be connect by its back side interconnection architecture with external circuit, or pass through package substrate
First contact jaw, the second contact jaw and the interconnection circuit on surface are connect with external circuit.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For device disclosed in embodiment
For, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, related place is said referring to method part
It is bright.
The foregoing description of the disclosed embodiments can be realized professional and technical personnel in the field or using originally practical new
Type.Various modifications to these embodiments will be readily apparent to those skilled in the art, and determine herein
The General Principle of justice can be realized in other embodiments without departing from the spirit or scope of the present utility model.Cause
This, the present invention will not be limited to the embodiments shown herein, and is to fit to and principles disclosed herein
The widest scope consistent with features of novelty.
Claims (12)
1. a kind of encapsulating structure of chip, which is characterized in that the encapsulating structure includes：
Package substrate, the package substrate include opposite first surface and second surface；Through the first surface and
The receiving hole of the second surface；
Chip to be packaged, the chip to be packaged are fixed in the receiving hole, and the chip to be packaged has opposite front
And the back side, the weld pad that front has functional unit and connect with the functional unit；
Wherein, the first surface is provided with the first contact jaw, and the second surface is provided with the second contact jaw, and described second connects
Contravention is provided in the package substrate for connecting external circuit for connecting first contact jaw and second contact
The interconnection circuit at end, at least partly described weld pad are connect with first contact jaw；Alternatively, the back side of the chip to be packaged is set
It is equipped with back side interconnection architecture, at least partly described weld pad is connect by the back side interconnection architecture with the external circuit.
2. encapsulating structure according to claim 1, which is characterized in that for the chip to be packaged, front has more
A weld pad, front is close to the first surface, and the back side is close to the second surface.
3. encapsulating structure according to claim 2, which is characterized in that the back side of the chip to be packaged has opening knot
Structure, the hatch frame is for exposing the weld pad；
The back side interconnection architecture is connect by the hatch frame with the weld pad that the hatch frame exposes, the back side
Interconnection architecture with external circuit for connecting.
4. encapsulating structure according to claim 3, which is characterized in that the hatch frame described in exposed portion for welding
It pads, weld pad described in the part is used to connect by the back side interconnection architecture with external circuit；
Weld pad described in another part passes through conducting wire or the conductive interconnections layer positioned at the first surface and first contact jaw
Connection.
5. encapsulating structure according to claim 3, which is characterized in that the hatch frame is for exposing all welderings
Pad, all weld pads are used to connect by the back side interconnection architecture with external circuit.
6. encapsulating structure according to claim 3, which is characterized in that the hatch frame includes multiple through-holes, each
The through-hole is corresponding to expose a weld pad.
7. encapsulating structure according to claim 6, which is characterized in that the through-hole is straight hole or trapezoidal hole.
8. encapsulating structure according to claim 6, which is characterized in that the back side setting of the chip to be packaged is fluted,
The depth of the groove is less than the thickness of the chip to be packaged, and the through-hole is located in the groove.
9. encapsulating structure according to claim 2, which is characterized in that all weld pads are by conducting wire or are located at described
The conductive interconnections layer of first surface is connect with first contact jaw.
10. encapsulating structure according to claim 1, which is characterized in that the front and described first of the chip to be packaged
Surface flushes.
11. encapsulating structure according to claim 1, which is characterized in that the second surface of the package substrate is covered with
One encapsulation glue-line, the first encapsulation glue-line also fill up the gap between the chip to be packaged and the receiving hole, and being used for will
The chip to be packaged is fixed in the receiving hole；
When the second surface is provided with the second contact jaw, the first encapsulation glue-line covers second contact jaw, described
First encapsulation glue-line exposes second contact jaw by milled processed；
When the back side of the chip to be packaged is provided with back side interconnection architecture, the back side interconnection architecture includes being used for and external
The third contact jaw of circuit connection, the first encapsulation glue-line cover the third contact jaw, and the first encapsulation glue-line passes through
Milled processed exposes the third contact jaw.
12. encapsulating structure according to claim 1, which is characterized in that the first surface of the package substrate is covered with
Two encapsulation glue-lines；
When at least partly described weld pad is connect with first contact jaw, the weld pad passes through conducting wire and first contact jaw
Connection, the second encapsulation glue-line cover the conducting wire, or, the weld pad passes through the conductive interconnections positioned at the first surface
Layer is connect with first contact jaw, and the second encapsulation glue-line covers the conductive interconnections layer.
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| CN201820423595.5U CN208111419U (en) | 2018-03-27 | 2018-03-27 | A kind of encapsulating structure of chip |
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| CN201820423595.5U CN208111419U (en) | 2018-03-27 | 2018-03-27 | A kind of encapsulating structure of chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257921A (en) * | 2018-03-27 | 2018-07-06 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and packaging method of a kind of chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257921A (en) * | 2018-03-27 | 2018-07-06 | 苏州晶方半导体科技股份有限公司 | The encapsulating structure and packaging method of a kind of chip |
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