CN204792779U - Diode packaging structure - Google Patents

Diode packaging structure Download PDF

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Publication number
CN204792779U
CN204792779U CN201520424595.3U CN201520424595U CN204792779U CN 204792779 U CN204792779 U CN 204792779U CN 201520424595 U CN201520424595 U CN 201520424595U CN 204792779 U CN204792779 U CN 204792779U
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China
Prior art keywords
conductor layer
chip
conductive layer
silver
layer
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Active
Application number
CN201520424595.3U
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Chinese (zh)
Inventor
张子岳
刘家宾
佘春林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LIZ Electronics (Kunshan) Co., Ltd.
Original Assignee
Beautiful Intelligence Electronics (kunshan) Has Co
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Priority to CN201520424595.3U priority Critical patent/CN204792779U/en
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Publication of CN204792779U publication Critical patent/CN204792779U/en
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Abstract

The utility model discloses a diode packaging structure, including two termination electrodes, be provided with ceramic substrate between two termination electrodes, ceramic substrate's upper surface printing has silver -colored conductive layer, it has connect the chip to lead on the silver conductive layer, the positive electrode of chip is led and has been connect vacuum sputter conductive layer, chip periphery between silver conductive layer and the vacuum sputter conductive layer is provided with an epoxy layer, the top of vacuum sputter conductive layer is provided with the 2nd epoxy layer. Can electrically conduct heat radiating area through adopting vacuum sputter conductive layer to realize connecing with leading of chip positive electrode, having increased, promote power dissipation ability, reduce manufacturing cost in addition, improve production efficiency.

Description

A kind of diode package structure
Technical field
The utility model relate to a kind of diode package structure, belongs to diode package processing technique field.
Background technology
The diode packaging technology of plastic packaging is adopted be used as carrier with copper stent or PCB to carry out encapsulating with the technology of die bond, bonding wire (or mode of die bond welding) or mold pressing and complete Product processing through plating and Sheet Metal Forming Technology again and encapsulate in the market.
In the encapsulation technology that this market adopts, the less impedance of its bonding wire sectional area and thermal resistance value are easy to more greatly cause power dissipation and can not bear higher power; Heat dissipation characteristics is not good, and bonding wire UPH is comparatively slow, and about 20kpcs/ hour relative packaging cost is higher.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of diode package structure, by adopting vacuum splashing and plating conductor layer to realize and the connecting of chip positive electrode, increasing can conductive radiator area, improves power dissipation ability, and reduce production cost, improve production efficiency.
In order to solve the problems of the technologies described above, the technical scheme that the utility model adopts is:
A kind of diode package structure, comprise two termination electrodes, ceramic substrate is provided with between described two termination electrodes, the upper surface of described ceramic substrate is printed with silver conductor layer, described silver conductor layer has connected chip, the positive electrode of described chip has connected vacuum splashing and plating conductor layer, and the chip periphery between described silver conductor layer and vacuum splashing and plating conductor layer is provided with first ring epoxy layer, and the top of described vacuum splashing and plating conductor layer is provided with the second epoxy resin layer.
Aforesaid a kind of diode package structure, is characterized in that: the upper surface of described second epoxy resin layer is also provided with anti-welding protective layer.
Aforesaid a kind of diode package structure, is characterized in that: the contact-making surface of described vacuum splashing and plating conductor layer is the circle of diameter 0.22mm.
Aforesaid a kind of diode package structure, is characterized in that: the material of described vacuum splashing and plating conductor layer is silver or copper.
Aforesaid a kind of diode package structure, is characterized in that: described termination electrode adopts metal paste whole applying structure.
Aforesaid a kind of diode package structure, is characterized in that: described termination electrode adopts vacuum splashing and plating metal structure.
The beneficial effects of the utility model are:
1, by adopting vacuum splashing and plating conductor layer to realize and the connecting of chip positive electrode, increasing can conductive radiator area, improves power dissipation ability, and reduces production cost, improve production efficiency;
2, client's welding quality is improved by being beneficial to the coating of whole of metal paste or the mode enlarged portion electrode area of vacuum splashing and plating metal by termination electrode;
3, the encapsulating structure of patch form, can be beneficial to the improved efficiency of client SMT piece.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of diode package structure of the utility model.
Embodiment
Below in conjunction with Figure of description, the utility model is further described.
As shown in Figure 1, a kind of diode package structure, comprise two termination electrodes 8, ceramic substrate 1 is provided with between described two termination electrodes 8, the upper surface of described ceramic substrate 1 is printed with silver conductor layer 2, and described silver conductor layer 2 has connected chip 3, and the positive electrode of described chip 3 has connected vacuum splashing and plating conductor layer 5, chip 3 periphery between described silver conductor layer 2 and vacuum splashing and plating conductor layer 5 is provided with first ring epoxy layer 4, and the top of described vacuum splashing and plating conductor layer 5 is provided with the second epoxy resin layer 6.
With ceramic substrate 1 for ground, printing silver conductor layer 2 carries out conductor high temperature sintering, add conducting resinl at silver conductor layer 2 with die bond equipment chip 3 to be planted after on conductive silver glue and carry out conducting resinl solidification, thus carries chips 3, replace copper stent (or PCB) the carries chips mode of market diode technologies.
First ring epoxy layer 4 covers chip 3 and is cured, with the positive electrode vacuum splashing and plating conductor layer 5 that vacuum sputtering equipment adopts vacuum splashing and plating technique to expose at chip 3, realize and the connecting of chip 3 positive electrode by adopting vacuum splashing and plating conductor layer 5, increasing can conductive radiator area, improve power dissipation ability, and reduce production cost, improve production efficiency.
Then the second epoxy resin layer 6 is adopted full wafer printing to be covered chip 3 and vacuum splashing and plating conductor layer 5 and be cured, as the operator guards of diode.
Sheet products is split into strip with sliver or cutting mode and automatic Loading in tool, to be automatically coated with silver or vacuum sputtering equipment does the coating of whole of conductor in two side ends electrode, strip material is divided into graininess with jackknifing or cutting mode, carry out termination electrode electronickelling and electrotinning, thus enlarged portion electrode area is beneficial to raising client welding quality.
In the present embodiment, the material of vacuum splashing and plating conductor layer 5 is silver or copper, and contact-making surface is the circle of diameter 0.22mm, can conductive radiator area be 3.14*0.11mm*0.11mm=0.038mm 2, and tactile the amassing of its positive electrode of product of existing market plastic package diode encapsulation technology conduction junction is: 3.14*0.021mm*0.021mm=0.0138mm 2, for dissipation capability improving 2-3 times of power, and without quality problem such as DELAMINATE, effectively reduce the reduction of client's production cost and designing quality risk.
The upper surface of described second epoxy resin layer 4 is also provided with anti-welding protective layer 7, is convenient to user's welding.
In sum, a kind of diode package structure that the utility model provides, realizes and the connecting of chip positive electrode by adopting vacuum splashing and plating conductor layer, increasing can conductive radiator area, improve power dissipation ability, and reduce production cost, improve production efficiency.
More than show and describe general principle of the present utility model, principal character and advantage.The technical staff of the industry should understand; the utility model is not restricted to the described embodiments; what describe in above-described embodiment and specification just illustrates principle of the present utility model; under the prerequisite not departing from the utility model spirit and scope; the utility model also has various changes and modifications, and these changes and improvements all fall within the scope of claimed the utility model.The claimed scope of the utility model is by appending claims and equivalent circle thereof.

Claims (6)

1. a diode package structure, comprise two termination electrodes (8), ceramic substrate (1) is provided with between described two termination electrodes (8), it is characterized in that: the upper surface of described ceramic substrate (1) is printed with silver conductor layer (2), described silver conductor layer (2) has connected chip (3), the positive electrode of described chip (3) has connected vacuum splashing and plating conductor layer (5), chip (3) periphery between described silver conductor layer (2) and vacuum splashing and plating conductor layer (5) is provided with first ring epoxy layer (4), the top of described vacuum splashing and plating conductor layer (5) is provided with the second epoxy resin layer (6).
2. a kind of diode package structure according to claim 1, is characterized in that: the upper surface of described second epoxy resin layer (4) is also provided with anti-welding protective layer (7).
3. a kind of diode package structure according to claim 1, is characterized in that: the contact-making surface of described vacuum splashing and plating conductor layer (5) is the circle of diameter 0.22mm.
4. a kind of diode package structure according to claim 1, is characterized in that: the material of described vacuum splashing and plating conductor layer (5) is silver or copper.
5. a kind of diode package structure according to claim 1, is characterized in that: described termination electrode (8) adopts metal paste whole applying structure.
6. a kind of diode package structure according to claim 1, is characterized in that: described termination electrode (8) adopts vacuum splashing and plating metal structure.
CN201520424595.3U 2015-06-19 2015-06-19 Diode packaging structure Active CN204792779U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201520424595.3U CN204792779U (en) 2015-06-19 2015-06-19 Diode packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201520424595.3U CN204792779U (en) 2015-06-19 2015-06-19 Diode packaging structure

Publications (1)

Publication Number Publication Date
CN204792779U true CN204792779U (en) 2015-11-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201520424595.3U Active CN204792779U (en) 2015-06-19 2015-06-19 Diode packaging structure

Country Status (1)

Country Link
CN (1) CN204792779U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108172522A (en) * 2017-12-15 2018-06-15 丽智电子(昆山)有限公司 A kind of method of laser manufacture semiconductor packing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108172522A (en) * 2017-12-15 2018-06-15 丽智电子(昆山)有限公司 A kind of method of laser manufacture semiconductor packing device
CN108172522B (en) * 2017-12-15 2019-10-11 丽智电子(昆山)有限公司 A kind of method of laser manufacture semiconductor packing device

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C14 Grant of patent or utility model
GR01 Patent grant
CP03 Change of name, title or address

Address after: Suzhou City, Jiangsu province 215300 north of the city of Kunshan high tech Industrial Park Hanpu Road No. 989

Patentee after: LIZ Electronics (Kunshan) Co., Ltd.

Address before: Suzhou City, Jiangsu province 215316 north of the city of Kunshan high tech Industrial Park Hanpu Road No. 989

Patentee before: Beautiful intelligence electronics (Kunshan) has company

CP03 Change of name, title or address