CN204375728U - For the encapsulating structure of sensitive chip - Google Patents

For the encapsulating structure of sensitive chip Download PDF

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Publication number
CN204375728U
CN204375728U CN201420839265.6U CN201420839265U CN204375728U CN 204375728 U CN204375728 U CN 204375728U CN 201420839265 U CN201420839265 U CN 201420839265U CN 204375728 U CN204375728 U CN 204375728U
Authority
CN
China
Prior art keywords
chip
substrate
encapsulating structure
sensitive chip
projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201420839265.6U
Other languages
Chinese (zh)
Inventor
郭小伟
龚臻
薛海冰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201420839265.6U priority Critical patent/CN204375728U/en
Application granted granted Critical
Publication of CN204375728U publication Critical patent/CN204375728U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning

Landscapes

  • Solid State Image Pick-Up Elements (AREA)

Abstract

The utility model relates to a kind of encapsulating structure for sensitive chip, belongs to technical field of semiconductor encapsulation.Described encapsulating structure comprises substrate (1); described substrate (1) is provided with opening (2); described opening (2) top is provided with chip (3); described chip (3) front arranges layer of transparent protecting glue (5); projection (4) is provided with in described transparent protective film (5); described chip (3) is electrically connected by projection (4) and substrate (1), and described chip (3) is filled with plastic packaging material (6) around.A kind of encapsulating structure for sensitive chip of the utility model, its adopts the mode of whirl coating or printing to carry out transparent adhesive tape coating at sensitive chip photosurface, can solve problem that traditional approach expands at paster process chips lower air and the high problem of substrate cost.

Description

For the encapsulating structure of sensitive chip
Technical field
The utility model relates to a kind of encapsulating structure for sensitive chip, belongs to technical field of semiconductor encapsulation.
Background technology
Traditional sensitive chip, generally can be used in the bonding circle encapsulant of chip circumference and on substrate, increase the process of clear glass or other light transmissive materials and structure to protect sensitive chip and to be provided for the region (see Fig. 7) of light penetration.The type encapsulation due between chip with substrate light transmissive material district for air and chip are connected by the encapsulant of chip circumference and bump and lower substrate, when paster upper plate, the air of beneath chips is added thermal expansion, may directly cause chip rupture or warpage of packaging assembly, or the problem that on substrate, clear material region is peeled off, product failure or life-span are significantly shortened.Which needs on substrate, increase clear glass or light transmissive material simultaneously, also makes the cost of manufacture of substrate improve.
Summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, a kind of encapsulating structure for sensitive chip is provided, its adopts the mode of whirl coating or printing to carry out transparent adhesive tape coating at sensitive chip photosurface, can solve the traditional approach problem that air expands in paster process and the high problem of substrate cost.
The purpose of this utility model is achieved in that a kind of encapsulating structure for sensitive chip; it comprises substrate; described substrate is provided with opening; described overthe openings is provided with chip; described chip front side arranges layer of transparent protecting glue; be provided with projection in described transparent protective film, described chip is connected with electrical property of substrate by projection, and described chip circumference is filled with plastic packaging material.
Lens are provided with in described opening.
Compared with prior art, the utility model has following beneficial effect:
1, the utility model passes through the mode of whirl coating or printing transparent protecting glue, protecting glue and chip photosensitive region are directly fitted, and by complete preservation below chip, blend compounds and substrate combine, transparent material conventional substrate needing increase can be saved, reduce the cost of manufacture of substrate;
2, the utility model is by the mode of whirl coating or printing transparent protecting glue, can solve that tradition is photosensitive to be encapsulated in air through Reflow Soldering time and to expand and cause the problem of product failure or the lost of life;
3, form lens at base openings place point transparent adhesive tape, not only can strengthen the penetrating light intensity of light, and lens and base openings suitability that transparent adhesive tape is formed are flexible, mounting process is simple, is also subject to high temperature CTE expansion effects little.
Accompanying drawing explanation
fig. 1 is the schematic diagram of a kind of encapsulating structure for sensitive chip of the utility model.
Fig. 2 ~ Fig. 6 is each operation schematic diagram of a kind of encapsulating structure process for sensitive chip of the utility model.
Fig. 7 is the schematic diagram of the encapsulating structure being conventionally used to sensitive chip.
Wherein:
Substrate 1
Opening 2
Chip 3
Projection 4
Transparent protective film 5
Plastic packaging material 6.
Embodiment
See Fig. 1; a kind of encapsulating structure for sensitive chip of the utility model; it comprises substrate 1; described substrate 1 is provided with opening 2; be provided with chip 3 above described opening 2, described chip 3 front arranges layer of transparent protecting glue 5, is provided with projection 4 in described transparent protective film 5; described chip 3 is electrically connected by projection 4 and substrate 1, is filled with plastic packaging material 6 around described chip 3.
Its process is as follows:
Step one, see Fig. 2, get a disk, layer of transparent protecting glue is applied by the mode of whirl coating or printing at disk bumping surface (chip photosensitive region), photosensitive region is used for for the protection of chip lug face, then the mode of Ultraviolet radiation or baking is used to make transparent protective film carry out one-step solidification, make transparent protective film together with disk strong bonded, the height of transparent protective film flushes a little less than projection or with projection;
Step 2, see Fig. 3, disk is divided into the single chips for load;
Step 3, see Fig. 4, flip-chip is just had on the substrate of opening to photosensitive area, and make chip lug and substrate output pin form electric connection by Reflow Soldering, meanwhile transparent protective film can soften and complete regelate, and the substrate that wherein photosensitive area has an opening can replace with transparency carrier;
Step 4, see Fig. 5, the protection of plastic packaging material plastic packaging is carried out to chip;
Step 5, carry out anti oxidation layer plating in step 4 plastic packaging metacoxal plate surface exposure metal surface outside;
Step 6, the product completing anti oxidation layer plating to be cut, form independently single encapsulating structure.
See Fig. 6, after step 6 completes, on base openings place point, lens can be formed by transparent adhesive tape.

Claims (2)

1. the encapsulating structure for sensitive chip; it is characterized in that: it comprises substrate (1); described substrate (1) is provided with opening (2); described opening (2) top is provided with chip (3); described chip (3) front arranges layer of transparent protecting glue (5); be provided with projection (4) in described transparent protective film (5), described chip (3) is electrically connected by projection (4) and substrate (1), and described chip (3) is filled with plastic packaging material (6) around.
2. a kind of encapsulating structure for sensitive chip according to claim 1, is characterized in that: described opening is provided with lens in (2).
CN201420839265.6U 2014-12-26 2014-12-26 For the encapsulating structure of sensitive chip Active CN204375728U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420839265.6U CN204375728U (en) 2014-12-26 2014-12-26 For the encapsulating structure of sensitive chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420839265.6U CN204375728U (en) 2014-12-26 2014-12-26 For the encapsulating structure of sensitive chip

Publications (1)

Publication Number Publication Date
CN204375728U true CN204375728U (en) 2015-06-03

Family

ID=53331923

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201420839265.6U Active CN204375728U (en) 2014-12-26 2014-12-26 For the encapsulating structure of sensitive chip

Country Status (1)

Country Link
CN (1) CN204375728U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485319A (en) * 2014-12-26 2015-04-01 江苏长电科技股份有限公司 Package structure for light-sensing chip and process method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485319A (en) * 2014-12-26 2015-04-01 江苏长电科技股份有限公司 Package structure for light-sensing chip and process method thereof
CN104485319B (en) * 2014-12-26 2017-09-26 江苏长电科技股份有限公司 Encapsulating structure and process for sensitive chip

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