CN203909230U

CN203909230U - Semiconductor chip test device

Info

Publication number: CN203909230U
Application number: CN201420328888.7U
Authority: CN
Inventors: 高新华
Original assignee: Individual
Current assignee: Individual
Priority date: 2014-06-19
Filing date: 2014-06-19
Publication date: 2014-10-29
Anticipated expiration: 2024-06-19

Abstract

The utility model relates to the field of semiconductor chip tests, in particular to a semiconductor chip test device, which is mainly composed of a test probe, a lead and a pedestal, and is used for completing the electrical connection of a sheet electrode and a measuring circuit. The semiconductor chip test device comprises a substrate, wherein silver paste layers are adhered on the substrate and to a chip with electrodes on two sides. According to the semiconductor chip test device, the silver paste layers are adhered on the substrate and to a chip with electrodes on two sides, the silver paste layers have the function of adsorbing the chip, so that the chip can be stably fixed on the substrate without moving around, the 100% accurate measurement can be achieved during the test process, and qualified products cannot be mistaken for defective products and scrapped; in addition, a diaphragm is arranged at the upper right of the chip, the stray light can be effectively eliminated, and the measurement accuracy of the chip is improved.

Description

A kind of semiconductor die testing device

Technical field

The utility model relates to semiconductor die testing field, relates to specifically a kind of semiconductor die testing device.

Background technology

Semiconductor die testing device is mainly used in the test of semicon industry, photoelectricity industry, integrated circuit and encapsulation.Be widely used in the research and development of the Precise Electric Measurement of complexity, high speed device, be intended to guarantee quality and reliability, and reduce the cost of research and development time and device fabrication.

Distinguish from function: temperature control type, vacuum type (ultralow temperature probe station), RF type, LCD flat panel type, Hall effect type, surface resistivity type.

Along with high-endization of electronic equipment now, miniaturization, the performance of the packaging and testing flow process to semi-conductor chip is had higher requirement, and particularly arrives mobile phone, PC is all the more so to the manufacture of consumer electronics.And in assembling product process, the most indispensable key is exactly precise and stable fast.Client, detecting the screening of naked crystalline substance of small chip, captures, mobile, in plug-in unit etc. and successive process, has run into many quality obstacles.In this process, must adopt high-end motion control to reach chip optical testing and packaging technology in conjunction with coordinating Vision Builder for Automated Inspection to complement each other together, use and enhance productivity.

In prior art, in chip testing process, chip is being all placed in pallet of monolithic, every test a slice all needs to repeat chip to pick up and put action, easily damages chip, the possibility that causes yield to decline, and positioning precision is bad, make proving installation often occur abnormality processing, pick up and put the non-cutting time that action need to be longer, the testing efficiency of proving installation is also very low.Be placed on substrate because chip is placed on chip, although be provided with chip put area mark on substrate, chip is due to manual operation, easily partially set region, causes chip testing defective, is equivalent to the chip that itself has been, tested one-tenth defective products, so just causes the waste of resource.

Therefore, semiconductor die testing device needs to improve.

Utility model content

For the deficiency in above-mentioned technology, the utility model provides that a kind of chip testing is stable, test probe contacts good semiconductor die testing device.

For solving the problems of the technologies described above, the utility model is realized by following scheme:

A kind of semiconductor die testing device, mainly formed by test probe, lead-in wire and pedestal, be used for the device of the electrical connection of plate electrode and metering circuit, it comprises a substrate, in described substrate, electrode is at the chip of bilateral, be pasted with silver slurry layer, described chip upper right side is provided with the diaphragm of eliminating parasitic light.

Further, pushed down subregion at the silver slurry layer of the chip left and right sides by chip.

Further, described silver slurry layer thickness is between 0.1-1mm.

Further, described diaphragm is placed between 80 °～85 °, chip upper right side.

The beneficial effects of the utility model are: in described substrate, electrode is at the chip of bilateral, be pasted with silver slurry layer, silver slurry layer has the effect of absorption chip, can be by very stable chip being fixed on substrate, can not make it touch, in test process, can reach absolutely Measurement accuracy, certified products can be used as to defective products again and be scrapped.Be provided with diaphragm in chip upper right side in addition, can effectively eliminate parasitic light, improve the measurement accuracy rate of chip.

Brief description of the drawings

Fig. 1 is that the utility model is measured chip schematic diagram.

Fig. 2 is the suprabasil chip of the utility model and silver slurry layer structural representation.

Mark in accompanying drawing: substrate 10; Chip 20; Silver slurry layer 30; Photometric detector 1; Diaphragm 3.

Embodiment

Below in conjunction with accompanying drawing, the utility model is elaborated.

The utility model is mainly made up of test probe, lead-in wire and pedestal, for completing the device of electrical connection of plate electrode and metering circuit.

Please refer to accompanying drawing 1,2, a kind of semiconductor die testing device of the present utility model, comprises a substrate 10, in described substrate 10, electrode is at the chip 20 of bilateral, is pasted with silver slurry layer 30.Silver slurry layer 30 in chip 20 left and right sides is pushed down subregion by chip 20.Described silver slurry layer 30 thickness are between 0.1-1mm.Described chip 20 upper right side are provided with the diaphragm 3 of eliminating parasitic light.

As shown in Figure 1, the relative spectral response of photometric detector 1 should be calibrated to the International Commission on Illumination with CIE) standard luminosity observer spectral luminous efficiency function V (λ) is consistent; When testing radiation parameter, should adopt the photo-detector without spectral selectivity.Test macro should be by proofreading and correct with standard apart from d and diaphragm D1.Measuring distance d must be greater than 5 times～10 times of photometric detector diameters.Require the mechanical axis of measured device by the center of detector aperture.

Test probe is pressed on the electrode of chip or on exit, completes the electrical connection with chip.The relative spectral response of photometric detector should be calibrated to the International Commission on Illumination with CIE) standard luminosity observer spectral luminous efficiency function V (λ) is consistent; When testing radiation parameter, should adopt the photo-detector without spectral selectivity.Test macro should be by proofreading and correct with standard apart from d and diaphragm D1.Measuring distance d must be greater than 5 times～10 times of photometric detector diameters.Require the mechanical axis of measured device by the center of detector aperture.For impulsive measurement, current source should provide the current impulse of desired amplitude, width and repetition rate.The detector rise time should be enough little with respect to pulse width, and system should be a peak value measurement instrument.

Described diaphragm is placed between 80 °～85 °, chip upper right side, this angle has very large contribution to the measurement data of chip, when chip testing, test probe meeting frequency modulated light, and luminous intensity is measured the result that all can affect chip last test because of the different errors of introducing of method conventionally.The unified calibration steps of regulation is the conforming guarantee of test result.Light chip by this standard method use test probe, recording chip 20 luminous intensity reading values by chip measuring system is I _v1.Supposing affects test probe to light the main factor of luminous intensity of chip is test probe, ; Here test probe influence coefficient, the virtual luminous intensity of chip. its expression does not have the luminous intensity of the desirable sheet of probe and lead effect.By this detection chip be encapsulated in TO5 standard shell, without any optical system.Measuring luminous intensity reading with standard luminous intensity test macro obtains , suppose that affecting the bright main factor of sheet is lead-in wire, this formula can be used for calibration chip test macro.

The foregoing is only preferred implementation of the present utility model; not thereby limit the scope of the claims of the present utility model; every equivalent structure or conversion of equivalent flow process that utilizes the utility model instructions and accompanying drawing content to do; or be directly or indirectly used in other relevant technical field, be all in like manner included in scope of patent protection of the present utility model.

Claims

1. a semiconductor die testing device, mainly formed by test probe, lead-in wire and pedestal, be used for the device of the electrical connection of plate electrode and metering circuit, it comprises a substrate (10), it is characterized in that:, electrode upper in described substrate (10) is at the chip (20) of bilateral, be pasted with silver slurry layer (30), described chip (20) upper right side is provided with the diaphragm (3) of eliminating parasitic light.

2. a kind of semiconductor die testing device according to claim 1, is characterized in that: the silver slurry layer (30) in chip (20) left and right sides is pushed down subregion by chip (20).

3. a kind of semiconductor die testing device according to claim 1, is characterized in that: described silver slurry layer (30) thickness is between 0.1-1mm.

4. a kind of semiconductor die testing device according to claim 1, is characterized in that: described diaphragm (3) is placed between 80 °～85 °, chip (20) upper right side.