CN106057696B - Diode photoelectric test method based on photodetachment - Google Patents
Diode photoelectric test method based on photodetachment Download PDFInfo
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- CN106057696B CN106057696B CN201610502868.0A CN201610502868A CN106057696B CN 106057696 B CN106057696 B CN 106057696B CN 201610502868 A CN201610502868 A CN 201610502868A CN 106057696 B CN106057696 B CN 106057696B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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Abstract
The invention discloses a kind of diode photoelectric test method based on photodetachment, suitable for the wafer test of diode, array is disposed with multiple chips in single-wafer.The method includes carrying out electrical testing to chip described each of on the wafer using at least one set of test probe, to obtain the electrical parameter of each chip；Determine test spacing, which is at least to be spaced a chips；Chip to be measured is chosen from the wafer by the test spacing；Photosensitiveness test is successively carried out to the chip to be measured using one group of test probe, to obtain the photosensitiveness parameter of each chip to be measured；The photosensitiveness parameter for not surveying chip is determined according to the photosensitiveness parameter for the chip to be measured surveyed.The present invention is based on the uniform characteristic of photosensitiveness parameter distribution of single-wafer, the photosensitiveness parameter of the unselected chip obtained in such a way that logic calculates according to the photosensitiveness parameter of the chip of selection is very accurate.
Description
Technical field
The present invention relates to diode field, in particular to a kind of diode photoelectric test method based on photodetachment.
Background technique
As gan-based compound light emitting diode (English: Lighting Emitting Diode, abbreviation: LED) exists
Display and the extensive use of lighting area, recent years, the quantity required of LED showed geometric progression increase, this is just to LED's
Production efficiency and the quality of production propose requirements at the higher level.
In the manufacturing process of the diodes such as LED, need to carry out the wafer of diode photosensitiveness parameter and electrical parameter
Test.With the development of technology, also have and the light that multiple chip positive and negative electrodes carry out multiple chips is connected using multiple groups test probe
Electrical testing.Every measuring device can connect multiple groups test probe, usually three groups.Every group of test probe includes that two tests are visited
Needle, the corresponding chips of one group of test probe.
The method that existing multiple groups test probe carries out photoelectricity test is: firstly, the chip on wafer is surveyed according to every
The group number grouping for the test probe that amount equipment is connected, such as every group includes 3 chips；Then, it will be connect with more measuring devices
Multiple groups test probe prick simultaneously the N electrodes of corresponding multiple chips in P electrode and connect the positive and negative electrode of chip to crystalline substance
All chips on circle carry out complete photoelectric properties test.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
First, as chip size is smaller and smaller, the chip in single-wafer is more and more, thus visits when using multiple groups test
When needle tests multiple chips simultaneously, not only it is easier to block the luminous zone of chip, thus greatly reduces the test of photosensitiveness parameter
Accuracy, and the test of the photosensitiveness parameter of adjacent chip can interfere with each other, to further affect the survey of photosensitiveness parameter
Try accuracy.Second, the test probe that when test contacts with the N of chip, P electrode will receive the impact of test current or voltage and
Loss is generated, when multiple groups test probe is repeatedly used for testing the photosensitiveness parameter of all chips on multiple wafers, is surveyed
The loss for souning out needle is increasing, and the test probe being lost obviously will affect the accuracy of the photosensitiveness parameter of test.
Summary of the invention
In order to solve problems in the prior art, the embodiment of the invention provides a kind of diode photoelectricity based on photodetachment
Test method.The technical solution is as follows:
The embodiment of the invention provides a kind of diode photoelectric test method based on photodetachment, suitable for diode
Wafer test, array is disposed with multiple chips in single-wafer, which comprises
Electrical testing is carried out to chip described each of on the wafer using at least one set test probe, it is each to obtain
The electrical parameter of the chip；
Determine test spacing, the test spacing is at least to be spaced a chips；
Chip to be measured is chosen from the wafer by the test spacing；
Photosensitiveness test is successively carried out to the chip to be measured using one group of test probe, to obtain each chip to be measured
Photosensitiveness parameter；
The photosensitiveness parameter for not surveying chip is determined according to the photosensitiveness parameter for the chip to be measured surveyed.
In an implementation of the embodiment of the present invention, the photosensitiveness parameter for the chip to be measured that the basis has been surveyed is true
The step of making the photosensitiveness parameter for not surveying chip, comprising: the photosensitiveness parameter for the chip to be measured surveyed according to adjacent two,
The photosensitiveness parameter for not surveying chip between two adjacent chips to be measured, the institute surveyed are calculated in a manner of gradual change
The photosensitiveness parameter and the photosensitiveness parameter for not surveying chip for stating chip to be measured constitute arithmetic progression.
In an implementation of the embodiment of the present invention, adjacent two chips to be measured surveyed are respectively positioned on same
Row.
In another implementation of the embodiment of the present invention, adjacent two chips to be measured surveyed are respectively positioned on together
One column.
In another implementation of the embodiment of the present invention, adjacent two chips to be measured surveyed are respectively positioned on institute
State wafer radially.
In another implementation of the embodiment of the present invention, the photosensitiveness parameter for the chip to be measured that the basis has been surveyed
The step of determining the photosensitiveness parameter for not surveying chip, comprising: using the photosensitiveness parameter for the chip to be measured surveyed as positioned at
The photosensitiveness parameter for not surveying chip around the chip to be measured surveyed.
In an implementation of the embodiment of the present invention, around the chip to be measured surveyed do not survey chip with
The chip by chip to be measured surveyed.
In another implementation of the embodiment of the present invention, chip is not surveyed around the chip to be measured surveyed
With the chip chamber to be measured surveyed every 1-2 chips.
In an implementation of the embodiment of the present invention, the electrical testing of each chip includes: by one group
Two test probes in test probe are respectively connected to the P electrode and N electrode of the chip；To two test probes
It is passed through rated current or voltage rating；The electrical parameter of a chip is measured using the electrical measuring device.
In an implementation of the embodiment of the present invention, each chip to be measured the photosensitiveness test include: by
Two test probes in one group of test probe are respectively connected to the P electrode and N electrode of a chip to be measured；Described in two
Test probe is passed through rated current or voltage rating；Using the photosensitiveness ginseng of measurement of optical property device measuring one chip to be measured
Number.
In an implementation of the embodiment of the present invention, the electrical parameter includes: cut-in voltage Vfin, operating voltage
Vf, reverse leakage current IrWith breakdown reverse voltage Vr。
In an implementation of the embodiment of the present invention, the photosensitiveness parameter includes: brightness Iv, operating voltage Vf, main value
Wavelength Wd, peak wavelength Wp, half-wavelength HW, cie color x coordinate CIE-x and cie color y-coordinate CIE-y.
Technical solution provided in an embodiment of the present invention has the benefit that
In test, firstly, carrying out electrical testing to all chips in single-wafer using multiple groups test probe, institute is obtained
There is the electrical parameter of chip；Then, a part of core is chosen according to fixed interval from all chips using one group of test probe
Piece carries out photosensitiveness test, obtains the photosensitiveness parameter of the chip of selection；Finally, the distribution of the photosensitiveness parameter based on single-wafer is special
The photosensitiveness parameter of point, the i.e. uniform and adjacent 2-3 chips of the photosensitiveness parameter distribution of single-wafer is close, to be measured using what is surveyed
The photosensitiveness parameter of chip accurately determines the photosensitiveness parameter of unselected chip.Therefore, on the one hand, due to selection chip it
Between have certain intervals and test photosensitiveness parameter when only used one group of test probe, thus reduce test probe block adjacent chips
Luminous zone area and adjacent chips photosensitiveness test interfere with each other, to improve the accuracy of measurement；On the other hand,
Due to being that selected part chip carries out photosensitiveness test, to reduce the access times of test probe, and then reduces test and visit
The loss of needle keeps the photosensitiveness parameter of test more acurrate.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is the structural schematic diagram of the wafer of diode provided in an embodiment of the present invention；
Fig. 2 is the partial enlarged view of the part A of the wafer for the diode that Fig. 1 is provided；
Fig. 3 is the schematic diagram for the electrical parameter using multiple groups test probe test chip that the embodiment of the present invention 1 provides；
Fig. 4 is the schematic diagram of the photosensitiveness parameter for one group of test probe test chip of use that the embodiment of the present invention 1 provides；
Fig. 5 is the flow chart for the light emitting diode photoelectric test method based on photodetachment that the embodiment of the present invention 1 provides；
Fig. 6 is the flow chart for the electrical testing that the embodiment of the present invention 1 provides；
Fig. 7 is the flow chart for the photosensitiveness test that the embodiment of the present invention 1 provides.
Fig. 8 is the flow chart for the light emitting diode photoelectric test method based on photodetachment that the embodiment of the present invention 2 provides.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
For the ease of the description of embodiment, below first simply introduce the wafer of diode.As shown in Figure 1, wafer 10
Outside be circle, array is disposed with multiple chips in single-wafer.Specifically, by taking one of part A of wafer 10 as an example,
As shown in Fig. 2, wafer 10 is equipped with multiple chips 20, each chip 20 includes P electrode 21 and N electrode 22.Light on wafer 10
Property parameter distribution is uniform.
The photoelectric test method of diode provided by the invention is suitable for all scale chips, is especially adapted for use in small size
The photoelectricity test of chip, such as 5.5mil chip.
Embodiment 1
The embodiment of the present invention 1 provides a kind of light emitting diode photoelectric test method of photodetachment, is suitable for diode
Wafer test, referring to Fig. 5, this method comprises:
Step 101: electrical testing is carried out to all chips on wafer using at least one set of test probe, it is each to obtain
The electrical parameter of chip.
In an implementation of the embodiment of the present invention, using one group of test probe successively to all chips on wafer
Electrical testing is carried out, to obtain the electrical parameter of each chip.
In another implementation of the embodiment of the present invention, using multiple groups test probe to all chips on wafer into
Row electrical testing can be accomplished in the following manner:
The first, multiple chips are divided according to the group of the test probe of every electrical measuring device connection is several
Group, the quantity of chip described in every group are identical as the group number of the test probe that electrical property measuring device described in every connects；
The second, the multiple groups test probe successively by every electrical measuring device connection is respectively connected to corresponding every group of institute
It states in chip, to more device of testing electrical properties be connect with all chips on wafer, simultaneously to every on the wafer
A chip carries out electrical testing, to obtain the electrical parameter of each chip.
In another implementation of the embodiment of the present invention, using multiple groups test probe to all chips on wafer into
Row electrical testing can be accomplished in the following manner:
The first, multiple chips are divided according to the group of the test probe of every electrical measuring device connection is several
Group, the quantity of chip described in every group are identical as the group number of the test probe that electrical property measuring device described in every connects；
The second, using the test probe of an electrical measuring device connection successively test every group described in chip
Electrical parameter, to obtain the electrical parameter of each chip.
For example, as shown in figure 3, every electrical measuring device can connect in one of the embodiment of the present invention 1 implementation
Three groups of test probes are connect, every group of test probe includes two test probes.When grouping, since every electrical measuring device can connect
Three groups of test probes, thus every three chips are divided into one group.When test, three groups of test probes are respectively connected in three chips.To
All chips all access after one group of test probe, while carrying out electrical testing to all chips.
In a kind of implementation in embodiments of the present invention, wafer is the wafer drawn before splitting.
In another implementation in embodiments of the present invention, wafer is the wafer drawn after splitting.
With reference to Fig. 6, the electrical testing of one single chip can be realized using following manner:
Step 1011: the first test probe 31 in one group of test probe is accessed to the P electrode of one single chip；
Step 1012: the second test probe 32 in one group of test probe is accessed to the N electrode of one single chip；
Step 1013: being passed through rated current or voltage rating to the first test probe 31 and the second test probe 32；
Step 1014: using the electrical parameter of electrical measuring device measurement one single chip.
Wherein, electrical parameter includes: cut-in voltage Vfin, operating voltage Vf, reverse leakage current IrWith breakdown reverse voltage Vr。
Step 102: determining test spacing.
Wherein, test spacing is determined by the product characteristic and technique accuracy of wafer.In the present embodiment, between the test
Away from being at least to be spaced a chips.
Step 103: chip to be measured is chosen from wafer by test spacing.
Step 104: photosensitiveness test successively being carried out to chip to be measured using one group of test probe, to obtain each chip to be measured
Photosensitiveness parameter.
As shown in fig. 7, the photosensitiveness test of single chip to be measured can be realized using following manner:
Step 1041: the first test probe 31 in one group of test probe is accessed to the P electrode of single chip to be measured；
Step 1042: the second test probe 32 in one group of test probe is accessed to the N electrode of single chip to be measured；
Step 1043: being passed through rated current or voltage rating to the first test probe 31 and the second test probe 32；
Step 1044: using the photosensitiveness parameter of the single chip to be measured of measurement of optical property device measuring.
Wherein, photosensitiveness parameter includes: brightness Iv, operating voltage Vf, main value wavelength Wd, peak wavelength Wp, half-wavelength HW、CIE
Coloration x coordinate CIE-x and cie color y-coordinate CIE-y.
Step 105: the photosensitiveness parameter for not surveying chip is determined according to the photosensitiveness parameter for the chip to be measured surveyed.
In the present embodiment 1, specifically, according to the photosensitiveness parameter of adjacent two surveyed chip to be measured with the side of gradual change
Formula calculates the photosensitiveness parameter for not surveying chip between two adjacent chips to be measured, the photosensitiveness ginseng for the chip to be measured surveyed
Number and the photosensitiveness parameter for not surveying chip constitute arithmetic progression.Between the tolerance of the arithmetic progression and two adjacent chips to be measured
The quantity for not surveying chip is related.
Further, adjacent two chips to be measured surveyed are respectively positioned on same row.As shown in figure 4, being located at X-axis side
Upwards.
Further, adjacent two chips to be measured surveyed are respectively positioned on same row, as shown in figure 4, being located at Y-axis side
Upwards.
Further, adjacent two chips to be measured surveyed are respectively positioned on the wafer radially.
In an implementation of the embodiment of the present invention, in order to which the photoelectricity for conveniently and accurately obtaining all chips is joined
Number can obtain the opposite of chip corresponding with electrical parameter and photosensitiveness parameter when testing electrical parameter and photosensitiveness parameter simultaneously
Coordinate.The process specifically includes the following steps:
(a) it is scanned by electrical measuring device and determines the coordinate value of every chips on wafer and measure every chips simultaneously
Electrical parameter；
(b) determine that the coordinate value of chip to be measured simultaneously measures the photosensitiveness ginseng of chip to be measured simultaneously by the scanning of measurement of optical property equipment
Number；
(c) the photosensitiveness parameter of chip is not surveyed according to the photosensitiveness coaptation of chip to be measured and is scanned by measurement of optical property equipment
Determine the coordinate value for not surveying chip；
(d) according to identical coordinate value, merge the electrical parameter and photosensitiveness parameter of every chips, to obtain every on wafer
The final photoelectric parameter of chips.
In addition, can also first carry out photosensitiveness test, then carry out electrical testing in the present embodiment.
In the present invention, diode to be measured can be the diode with different function, such as Light-Emitting Diode, GaN base
Light emitting diode or storage chip.
The electrical measuring device and measurement of optical property equipment mentioned in the present embodiment are all existing measuring devices in industry.
The embodiment of the present invention has the benefit that in test, firstly, using multiple groups test probe in single-wafer
All chips carry out electrical testing, obtain the electrical parameter of all chips；Then, using one group of test probe from all chips
In choose a part of chip according to fixed interval and carry out photosensitiveness test, obtain the photosensitiveness parameter of the chip of selection；Finally, being based on
The characteristic distributions of the photosensitiveness parameter of single-wafer, i.e. the uniform and adjacent 2-3 chips of the photosensitiveness parameter distribution of single-wafer
Photosensitiveness parameter is close, and the photosensitiveness parameter of unselected chip is accurately determined using the photosensitiveness parameter for the chip to be measured surveyed.
Therefore, on the one hand, due to only having used one group of test probe when having certain intervals and test photosensitiveness parameter between the chip of selection, because
And reduce test probe block adjacent chips luminous zone area and adjacent chips photosensitiveness test interfere with each other, thus
Improve the accuracy of measurement；On the other hand, due to being that selected part chip carries out photosensitiveness test, to reduce test probe
Access times, and then reduce test probe loss, make test photosensitiveness parameter it is more acurrate.
Embodiment 2
A kind of light emitting diode photoelectric test method for photodetachment that the embodiment of the present invention 2 provides is suitable for diode
Wafer test, referring to Fig. 8, this method comprises:
Step 201: electrical testing is carried out to all chips on wafer using at least one set of test probe, it is each to obtain
The electrical parameter of chip.
In an implementation of the embodiment of the present invention, using one group of test probe successively to all chips on wafer
Electrical testing is carried out, to obtain the electrical parameter of each chip.
In another implementation of the embodiment of the present invention, using multiple groups test probe to all chips on wafer into
Row electrical testing can be accomplished in the following manner:
The first, multiple chips are divided according to the group of the test probe of every electrical measuring device connection is several
Group, the quantity of chip described in every group are identical as the group number of the test probe that electrical property measuring device described in every connects；
The second, the multiple groups test probe successively by every electrical measuring device connection is respectively connected to corresponding every group of institute
It states in chip, to more device of testing electrical properties be connect with all chips on wafer, simultaneously to every on the wafer
A chip carries out electrical testing, to obtain the electrical parameter of each chip.
In another implementation of the embodiment of the present invention, using multiple groups test probe to all chips on wafer into
Row electrical testing can be accomplished in the following manner:
The first, multiple chips are divided according to the group of the test probe of every electrical measuring device connection is several
Group, the quantity of chip described in every group are identical as the group number of the test probe that electrical property measuring device described in every connects；
The second, using the test probe of an electrical measuring device connection successively test every group described in chip
Electrical parameter, to obtain the electrical parameter of each chip.
For example, as shown in figure 3, every electrical measuring device can connect in one of the embodiment of the present invention 1 implementation
Three groups of test probes are connect, every group of test probe includes two test probes.When grouping, since every electrical measuring device can connect
Three groups of test probes, thus every three chips are divided into one group.When test, three groups of test probes are respectively connected in three chips.To
All chips all access after one group of test probe, while carrying out electrical testing to all chips.
In a kind of implementation in embodiments of the present invention, wafer is the wafer drawn before splitting.
In another implementation in embodiments of the present invention, wafer is the wafer drawn after splitting.
The implementation of the electrical testing of the one single chip of the present embodiment is same as Example 1, and details are not described herein again.
Step 202: determining test spacing.
Wherein, test spacing is determined by the product characteristic and technique accuracy of wafer.In the present embodiment, between the test
Away from being at least to be spaced a chips.
Step 203: chip to be measured is chosen from wafer by test spacing.
Step 204: photosensitiveness test successively being carried out to chip to be measured using one group of test probe, to obtain each chip to be measured
Photosensitiveness parameter.
The implementation of the photosensitiveness test of the single chip to be measured of the present embodiment is same as Example 1, and details are not described herein again.
Step 205: the photosensitiveness parameter for not surveying chip is determined according to the photosensitiveness parameter for the chip to be measured surveyed.
In the present embodiment, specifically, using the photosensitiveness parameter for the chip to be measured surveyed as positioned at the chip to be measured surveyed
The photosensitiveness parameter for not surveying chip of surrounding.
The chip chamber to be measured not surveying chip and having surveyed around the chip to be measured surveyed is preferably located at every 1-
2 chips.
It is highly preferred that being located at the chip by chip to be measured not surveying chip Yu having surveyed around the chip to be measured surveyed.
In an implementation of the embodiment of the present invention, in order to which the photoelectricity for conveniently and accurately obtaining all chips is joined
Number can obtain the opposite of chip corresponding with electrical parameter and photosensitiveness parameter when testing electrical parameter and photosensitiveness parameter simultaneously
Coordinate.The process is identical as the process of embodiment 1, and details are not described herein again.
In addition, can also first carry out photosensitiveness test, then carry out electrical testing in the present embodiment.
In the present invention, diode to be measured can be the diode with different function, such as light emitting diode or GaN base
Light emitting diode.
The electrical measuring device and measurement of optical property equipment mentioned in the present embodiment are all existing measuring devices in industry.
The embodiment of the present invention has the benefit that in test, firstly, using multiple groups test probe in single-wafer
All chips carry out electrical testing, obtain the electrical parameter of all chips；Then, using one group of test probe from all chips
In choose a part of chip according to fixed interval and carry out photosensitiveness test, obtain the photosensitiveness parameter of the chip of selection；Finally, being based on
The characteristic distributions of the photosensitiveness parameter of single-wafer, i.e. the uniform and adjacent 2-3 chips of the photosensitiveness parameter distribution of single-wafer
Photosensitiveness parameter is close, and the photosensitiveness parameter of unselected chip is accurately determined using the photosensitiveness parameter for the chip to be measured surveyed.
Therefore, on the one hand, due to only having used one group of test probe when having certain intervals and test photosensitiveness parameter between the chip of selection, because
And reduce test probe block adjacent chips luminous zone area and adjacent chips photosensitiveness test interfere with each other, thus
Improve the accuracy of measurement；On the other hand, due to being that selected part chip carries out photosensitiveness test, to reduce test probe
Access times, and then reduce test probe loss, make test photosensitiveness parameter it is more acurrate.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of diode photoelectric test method based on photodetachment, suitable for the wafer test of diode, in single-wafer
Array is disposed with multiple chips, which is characterized in that the described method includes:
Electrical testing is carried out to chip described each of on the wafer using at least one set test probe, it is each described to obtain
The electrical parameter of chip；
Determine test spacing, the test spacing is at least to be spaced a chips；
Chip to be measured is chosen from the wafer by the test spacing；
Photosensitiveness test is successively carried out to the chip to be measured using one group of test probe, to obtain the light of each chip to be measured
Property parameter；
The photosensitiveness parameter for not surveying chip is determined according to the photosensitiveness parameter for the chip to be measured surveyed,
The step of photosensitiveness parameter for the chip to be measured that the basis has been surveyed determines the photosensitiveness parameter for not surveying chip, comprising:
The photosensitiveness parameter for the chip to be measured surveyed according to adjacent two is calculated in a manner of gradual change positioned at two adjacent institutes
The photosensitiveness parameter for not surveying chip between chip to be measured is stated, the photosensitiveness parameter for the chip to be measured surveyed and described does not survey chip
Photosensitiveness parameter constitute arithmetic progression.
2. the method according to claim 1, wherein adjacent two chips to be measured surveyed are respectively positioned on together
One row perhaps adjacent two chips to be measured surveyed be respectively positioned on same row or adjacent two have been surveyed it is described to
It surveys chip and is respectively positioned on the wafer radially.
3. the method according to claim 1, wherein the photosensitiveness parameter for the chip to be measured that the basis has been surveyed
The step of determining the photosensitiveness parameter for not surveying chip, comprising:
Chip is not surveyed using the photosensitiveness parameter for the chip to be measured surveyed as around the chip to be measured surveyed
Photosensitiveness parameter.
4. according to the method described in claim 3, not surveying chip it is characterized in that, being located at around the chip to be measured surveyed
With the chip by chip to be measured surveyed.
5. according to the method described in claim 3, not surveying chip it is characterized in that, being located at around the chip to be measured surveyed
With the chip chamber to be measured surveyed every 1-2 chips.
6. the method according to claim 1, wherein the electrical testing of each chip includes:
Two test probes in one group of test probe are respectively connected to the P electrode and N electrode of the chip；
Rated current or voltage rating are passed through to two test probes；
The electrical parameter of a chip is measured using electrical measuring device.
7. the method according to claim 1, wherein the photosensitiveness test of each chip to be measured includes:
Two test probes in one group of test probe are respectively connected to the P electrode and N electrode of a chip to be measured；
Rated current or voltage rating are passed through to two test probes；
Using the photosensitiveness parameter of measurement of optical property device measuring one chip to be measured.
8. method according to any one of claims 1-7, which is characterized in that the electrical parameter includes: cut-in voltage
Vfin, operating voltage Vf, reverse leakage current IrWith breakdown reverse voltage Vr。
9. method according to any one of claims 1-7, which is characterized in that the photosensitiveness parameter includes: brightness Iv, work
Make voltage Vf, main value wavelength Wd, peak wavelength Wp, half-wavelength HW, cie color x coordinate CIE-x and cie color y-coordinate CIE-y.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102280395A (en) * | 2011-09-02 | 2011-12-14 | 华灿光电股份有限公司 | Grouping test method for photoelectric parameters of light emitting diode |
| CN104360256A (en) * | 2014-10-21 | 2015-02-18 | 华灿光电(苏州）有限公司 | Diode photoelectricity test method |
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| TW201027645A (en) * | 2009-01-09 | 2010-07-16 | Qing-Biao Lin | A wafer packaging detection method with little or no ink dot |
| US8476918B2 (en) * | 2010-04-28 | 2013-07-02 | Tsmc Solid State Lighting Ltd. | Apparatus and method for wafer level classification of light emitting device |
| CN102568965B (en) * | 2010-12-16 | 2016-01-06 | 上海明科电气有限公司 | Overcurrent protection combined electrical surge protector |
-
2016
- 2016-06-30 CN CN201610502868.0A patent/CN106057696B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102280395A (en) * | 2011-09-02 | 2011-12-14 | 华灿光电股份有限公司 | Grouping test method for photoelectric parameters of light emitting diode |
| CN104360256A (en) * | 2014-10-21 | 2015-02-18 | 华灿光电(苏州）有限公司 | Diode photoelectricity test method |
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