CN116031273A - Wafer and method for manufacturing micro light-emitting diode chip - Google Patents

Abstract

The application provides a wafer and a method for manufacturing a miniature light-emitting diode chip. The wafer comprises a plurality of test units, and a first test electrode and a second test electrode which are arranged on the periphery of the test units. The test unit comprises a first interconnection line, a second interconnection line and a plurality of micro light emitting diode chips distributed in an array. Each micro light emitting diode chip has a first electrode and a second electrode. The first electrode, the first interconnection line and the first test electrode are electrically connected, and the second electrode, the second interconnection line and the second test electrode are electrically connected. The circumference side of the miniature LED chip is provided with a plurality of cutting channels. The first test electrode and the second test electrode are arranged in the cutting channel. When testing the test unit, all the micro light emitting diode chips in the unit can be tested at the same time, so that the test efficiency is improved. In addition, the voltages applied to each micro light emitting diode chip are the same, so that the test can be performed under the same test condition, thereby improving the accuracy of the test result.

Description

Wafer and method for manufacturing micro light-emitting diode chip

Technical Field

The present disclosure relates to semiconductor technology, and more particularly, to a wafer and a method for manufacturing a micro light emitting diode chip.

Background

Since Micro light emitting diodes (Micro Light Emitting Diode, micro LEDs) have advantages of self-luminescence, high efficiency, high color gamut, high contrast, etc., they are called as the most potential next generation display technology following organic light emitting diodes. Typically, after micro led chips are fabricated on a wafer, the chips need to be tested to determine if they are acceptable and their electrical characteristics are evaluated.

Currently the main test methods include photoluminescence test methods and electroluminescence test methods. Specifically, the electroluminescence test method adopts a power-on test, namely, the probe is contacted with the electrode of the miniature light-emitting diode chip to supply power to the chip, so that the performance of the chip is tested. However, as the size of the micro light emitting diode chip is smaller, the existing probe is liable to pierce the electrode of the chip, resulting in breakage of the chip. In addition, when multiple micro light emitting diode chips need to be tested simultaneously, multiple probes are needed to test accordingly, so that the positioning accuracy requirement on the probes is higher, and the structure of the wafer test system is more complex.

Disclosure of Invention

The application provides a wafer and a method for manufacturing micro light emitting diode chips, so that a plurality of micro light emitting diode chips on the wafer are tested at the same time, and the efficiency and the accuracy of wafer testing are improved.

In a first aspect, the present application provides a wafer. The wafer comprises a plurality of test units, a first test electrode and a second test electrode. Specifically, the first test electrode and the second test electrode are disposed on the peripheral side of the test unit. The test unit comprises a plurality of micro light emitting diode chips, a first interconnection line and a second interconnection line. Wherein the plurality of micro light emitting diode chips are distributed in an array. Each micro light emitting diode chip is provided with a first electrode and a second electrode, wherein the first electrode is electrically connected with the first interconnection line, and the second electrode is electrically connected with the second interconnection line. The first interconnection line is electrically connected with the first test electrode, and the second interconnection line is electrically connected with the second test electrode. The circumference side of each micro light emitting diode chip is provided with a plurality of cutting channels, so the circumference side of the test unit is also provided with a plurality of cutting channels, and the first test electrode and the second test electrode are arranged in the cutting channels.

In the wafer test process, one probe is in contact with and electrically connected with a first test electrode in the tested unit, and the other probe is in contact with and electrically connected with a second test electrode, so that a plurality of micro light emitting diode chips of the tested unit are simultaneously electrified, and the wafer test efficiency is improved. In addition, the voltage drop between the two electrodes of each micro light emitting diode chip is the same, so that the error of the test result can be reduced when each micro light emitting diode chip is tested under the same voltage condition. In addition, the first test electrode and the second test electrode are arranged by utilizing the cutting channel at the peripheral side of the test unit, so that the space of the miniature light-emitting diode chip is not occupied, and the space utilization rate of the wafer can be increased.

Specifically, the layout of the dicing streets is not limited. For example, the dicing lanes may include a plurality of first dicing lanes extending in a first direction and arranged in parallel. The first test electrode can be arranged in the first cutting channel; alternatively, the second test electrode may be disposed within the first scribe line; alternatively, the first and second test electrodes may be disposed within the first scribe line. The test unit is arranged between the first test electrode and the second test electrode. By adopting the layout mode, the first test electrode and the second test electrode extend along the first direction and are arranged in parallel, so that the pattern design on the wafer can be simplified, and the process for manufacturing the wafer is reduced.

The dicing street may further comprise a plurality of second dicing streets. The second cutting channels extend along a second direction and are arranged in parallel, and the second direction is perpendicular to the first direction. The first interconnection line and the second interconnection line are arranged on the second cutting channel. In the technical scheme, the first interconnection line and the second interconnection line utilize the second cutting channel between the micro light emitting diodes, and the space of the micro light emitting diodes on the wafer is not occupied, so that the space utilization rate of the wafer is further improved.

The plurality of test units may include a plurality of first test units and a plurality of second test units alternately arranged in the second direction. In a specific technical solution, adjacent first test units and second test units may share the same first test electrode, or adjacent first test units and second test units may share the same second test electrode. That is, one first test electrode or one second test electrode may be disposed in the first scribe line between the adjacent first test unit and second test unit, so that the space between the test units may be shortened to increase the space utilization on the wafer.

In a further embodiment, two first test electrodes or two second test electrodes may be provided in the first scribe line between adjacent first and second test units.

Alternatively, in other embodiments, a first test electrode and a second test electrode may be disposed in the first scribe line between the adjacent first test unit and second test unit.

In the above technical solution, the same test electrode is not shared between the adjacent first test unit and second test unit, that is, each test unit may correspond to one first test electrode and one second test electrode. When a selected test unit is tested, the probe can be directly contacted with the first test electrode and the second test electrode corresponding to the test unit, so that the test unit can be rapidly and accurately positioned.

The first test electrode in each cutting channel is of an integrated structure, and the second test electrode in each cutting channel is of an integrated structure, so that the pattern design of the wafer and the process for manufacturing the wafer can be simplified.

The first test electrode, the second test electrode, the first interconnection line, the second interconnection line, and the first electrode and the second electrode of the micro light emitting diode chip are fabricated in the same layer, so as to simplify the wafer fabrication steps.

In a second aspect, the present application provides a method of fabricating a micro light emitting diode chip. The method comprises the following steps:

preparing a wafer on a substrate base plate;

testing the miniature light emitting diode chip of the wafer;

removing the first test electrode, the second test electrode, the first interconnection line and the second interconnection line;

and cutting the wafer to form a plurality of independent miniature light-emitting diode chips.

The wafer of the first aspect is adopted to manufacture the independent micro light emitting diode chips, on one hand, the first test electrode, the second test electrode, the first interconnecting wire and the second interconnecting wire for testing do not occupy the space of the micro light emitting diode chips on the wafer, and the dicing channels among the micro light emitting diode chips are utilized, so that the space utilization rate of the wafer is improved; on the other hand, when testing the wafer, the probe of the wafer testing system is not required to be in direct contact with the micro light emitting diode chip with the first testing electrode and the second testing electrode, so that the probe can be prevented from damaging the micro light emitting diode chip.

In addition, when the wafer test is performed, the plurality of micro light emitting diode chips in the test unit can be tested at the same time, so that the test efficiency is improved. And, because each micro light emitting diode chip is electrically connected with the first test electrode and the second test electrode respectively, the voltage applied to each micro light emitting diode chip in the test unit is equal. Therefore, under the same voltage condition, the light power and the wavelength of the micro light emitting diode chip are uniform, so that the accuracy of a test result can be improved, and when a bad micro light emitting diode chip appears, the micro light emitting diode chip can be accurately positioned.

In a specific technical scheme, the first test electrode, the second test electrode, the first interconnection line, the second interconnection line, the first electrode and the second electrode are manufactured in the same layer, so that the pattern design of the wafer and the wafer manufacturing process can be simplified.

Drawings

FIG. 1 is a schematic view of a wafer;

FIG. 2 is a schematic view of a wafer according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a test unit according to an embodiment of the present application;

FIG. 4 is a schematic view of another exemplary structure of a wafer according to an embodiment of the present disclosure;

FIG. 5 is a schematic view of another exemplary structure of a wafer according to an embodiment of the present disclosure;

FIG. 6 is a schematic view of another exemplary structure of a wafer according to an embodiment of the present disclosure;

FIG. 7 is a schematic view of another exemplary structure of a wafer according to an embodiment of the present disclosure;

FIG. 8 is a flow chart of a method of fabricating a micro light emitting diode chip in an embodiment of the present application;

fig. 9 is a schematic diagram of a wafer testing system according to an embodiment of the present application.

Reference numerals:

01-wafer; 02-a micro light emitting diode chip;

10-wafer; 11-a test unit;

12-a first test electrode; 13-a second test electrode;

14-a first scribe line; 15-a second scribe line;

90-wafer test system; 91-a power supply;

92-probe; 93-a workbench;

94-beam splitters; 95-an image collector;

96-integrating sphere; 97-spectrometer;

98-power meter; 99-computer;

11 a-a first test unit; 11 b-a second test unit;

111-micro light emitting diode chips; 112-a first interconnect line;

113-a second interconnect line; 114-a first electrode;

115-a second electrode; 116-conducting wires;

931—a table motion control system; 961-integrating sphere motion control system.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings.

Fig. 1 is a schematic view of a wafer. In the process of manufacturing individual micro led chips, as shown in fig. 1, a plurality of micro led chips 02 are first manufactured on a single wafer 01. Each micro light emitting diode chip 02 may be any one of a red micro light emitting diode chip, a green micro light emitting diode chip, or a blue micro light emitting diode chip. Then, each micro led chip 02 is transferred from the wafer 01, resulting in an individual micro led chip.

In order to ensure that the chip package finally mounted on the circuit board can work normally, after the micro led chips 02 are fabricated on the wafer 01, a wafer test is generally performed to identify whether each micro led chip 02 can work normally or not and evaluate the electrical characteristics thereof. Through wafer testing, defective products of the chips can be identified, and can be removed when the micro light emitting diode chips 02 are transferred, so that the yield of the chips is improved.

In the process of testing the wafer 01 by adopting the electroluminescence test method, each micro light emitting diode chip 02 on the wafer 01 is tested by a probe. Specifically, each micro led chip 02 has two electrode terminals. For one micro light emitting diode chip 02, one probe is contacted with one electrode terminal of the micro light emitting diode chip 02, and the other probe is contacted with the other electrode terminal of the micro light emitting diode chip 02, and then the two probes electrify the micro light emitting diode chip 02 to work, so that the performance of the micro light emitting diode chip 02 can be tested.

However, with the continuous development of semiconductor technology, the size of the micro light emitting diode chip is becoming smaller and smaller. Likewise, the size of the electrode terminals is also becoming smaller and smaller. When the probe contacts with the electrode terminal, the probe is extremely easy to pierce the electrode terminal, thereby causing damage to the micro light emitting diode chip and reducing the yield of the chip.

In addition, as the size of the micro led chips decreases, the number of micro led chips formed on the same wafer increases. This requires higher positioning accuracy of the probes and the ability to test a greater number of chips simultaneously, which is difficult to meet with existing wafer test systems.

Therefore, the wafer and the method for manufacturing the micro light emitting diode chips are provided, so that the plurality of micro light emitting diode chips on the wafer are tested at the same time, and the efficiency and the accuracy of wafer testing are improved.

In the embodiments of the present application, the micro led chip refers to a chip fabricated on a wafer and not transferred. And after the wafer test is completed, transferring the micro light emitting diode chips from the wafer to obtain independent micro light emitting diode chips. Wherein, a red micro light emitting diode chip, a green micro light emitting diode chip and a blue micro light emitting diode chip can be combined to form a group of micro light emitting diode chips capable of emitting white light.

Fig. 2 is a schematic structural diagram of a wafer according to an embodiment of the present application. As shown in fig. 2, the wafer 10 includes a plurality of test units 11, a first test electrode 12, and a second test electrode 13, wherein the first test electrode 12 and the second test electrode 13 are disposed at a peripheral side of the test units 11. Specifically, fig. 3 is a schematic structural diagram of a test unit in an embodiment of the present application. As shown in fig. 3, each test unit 11 includes a plurality of micro light emitting diode chips 111, first interconnection lines 112, and second interconnection lines 113. The plurality of micro led chips 111 are distributed in an array in the test unit 11, for example, may be distributed in a rectangular array, a triangular array, or a concentric array, which is not particularly limited in this application. Each micro light emitting diode chip 111 has a first electrode 114 and a second electrode 115. In each test unit 11, one end of the first interconnection line 112 is electrically connected to the first test electrode 12, and the first electrodes 114 of all the micro light emitting diode chips 111 are electrically connected to the first interconnection lines 112, respectively; one end of the second interconnection line 113 is electrically connected to the second test electrode 13, and the second electrodes 115 of all the micro light emitting diode chips 111 are electrically connected to the second interconnection line 113, respectively. For example, in one embodiment, the first test unit 11a and the second test unit 11b are provided on both sides of the test unit 11, respectively. The first interconnect line 112 is connected to the first test electrode 12, and the second interconnect line 113 is connected to the second test electrode 13. In the wafer test process, for the test unit 11 to be tested, one probe of the wafer test system is in contact with and electrically connected to the first test electrode 12 on one side of the test unit 11, and the other probe is in contact with and electrically connected to the second test electrode 13 on the other side of the test unit 11, so that the first test electrode 12, the first interconnection line 112, the first electrode 114, the second electrode 115, the second interconnection line 113 and the second test electrode 13 are electrically communicated, and the micro light emitting diode chip 111 in the test unit 11 is tested.

It should be noted that the specific number of the micro led chips 111 in the test unit 11 is not limited, and for example, a single test unit 11 may include tens or hundreds of thousands of micro led chips 111. For example, taking a 4 inch wafer 10 as an example, the wafer 10 may include 800 thousands of micro led chips 111, and each test unit 11 may include 10 tens of thousands of micro led chips 111. Therefore, when the wafer test is performed, the single test unit 11 is tested, which is equivalent to simultaneously testing tens or hundreds of thousands of micro light emitting diode chips 111, which not only can remarkably improve the efficiency of the wafer test, but also can reduce the number of probes required, simplify the wafer test system, and thereby reduce the cost of the wafer test.

To facilitate transferring the micro led chips 111 after the wafer test is completed, the positions of the plurality of dicing streets are generally designed by using the gaps between the micro led chips 111. Moreover, due to the presence of the scribe lines, all the test cells 11 on the wafer 10 are independent of each other. As shown in fig. 2, in some embodiments of the present application, the dicing streets may include a plurality of first dicing streets 14. The first dicing street 14 extends along the first direction a and is disposed on the peripheral side of the micro light emitting diode chip 111. Alternatively, as shown in fig. 3, in other embodiments of the present application, the streets may include a plurality of first streets 14 and a plurality of second streets 15. The first dicing street 14 and the second dicing street 15 are disposed on the peripheral side of the micro light emitting diode chip 111, wherein the first dicing street 14 extends along a first direction a, and the second dicing street 15 extends along a second direction B, and the first direction a is perpendicular to the second direction B. That is, the peripheral side of the test unit 11 may be provided with both the first dicing lane 14 and the second dicing lane 15.

In the above embodiment, the first test electrode 12 and the second test electrode 13 are arranged in the dicing channels on the peripheral side of the test unit 11, and the width may be 20 micrometers, 30 micrometers, 50 micrometers, or 80 micrometers, for example. In this way, the first and second test electrodes 12 and 13 do not need to occupy the positions of the micro light emitting diode chips 111 within the test unit 11, so that the footprint of the micro light emitting diode chips 111 can be increased as much as possible when the wafer 10 is designed.

With continued reference to fig. 2, in some embodiments of the present application, the peripheral side of the test unit 11 is provided with a plurality of first dicing lanes 14 extending along the first direction a. The first dicing lane 14 may have the first test electrode 12 disposed therein, or the first dicing lane 14 may have the second test electrode 13 disposed therein, or the first dicing lane 14 may have the first test electrode 12 and the second test electrode 13 disposed therein. In the embodiment of the present application, the test unit 11 is disposed between the first test electrode 12 and the second test electrode 13. Therefore, when the selected test unit 11 needs to be tested, the probe of the wafer test system is in contact with and electrically connected to the first test electrode 12 and the second test electrode 13 adjacent to the test unit 11, and the probe does not need to be in contact with the first electrode 114 and the second electrode 115 of the micro light emitting diode chip 111, so that the probe can be prevented from damaging the electrodes of the micro light emitting diode chip 111.

With continued reference to fig. 3, in each test unit 11, the first electrode 114 of each micro led chip 111 is connected to the first interconnect line 112 by a wire 116, and the first interconnect line 112 is connected to the first test electrode 12; the second electrode 115 of each micro light emitting diode chip 111 is connected to the second interconnection line 113 through a wire 116, and the second interconnection line 113 is connected to the second test electrode 13. When a selected test unit 11 is tested, each micro led chip 111 within the test unit 11 is in electrical communication with the first test electrode 12 and the second test electrode 13, respectively, and forms a loop with the circuitry of the wafer test system. In other words, from the circuit point of view, the plurality of micro light emitting diode chips 111 in the test unit 11 are connected in parallel to each other. Therefore, the voltage applied to each micro light emitting diode chip 111 in the test unit 11 is the same, that is, the voltage drop between the two electrodes of each micro light emitting diode chip 111 is the same. In this way, all the micro led chips 111 in the test unit 11 can be tested under the same voltage condition, so that the power and wavelength of the micro led chips 111 are uniform, and errors of test results are avoided, so that the misjudgment rate of the micro led chips 111 can be reduced, and the test results are more accurate.

In one embodiment, as shown in fig. 3, the first interconnect line 112 and the second interconnect line 113 may also be disposed in the second scribe line 15, and the width of the first interconnect line 112 and the second interconnect line 113 may be 3 microns, 6 microns, 7 microns or 9 microns, for example, in order to increase the space utilization of the wafer 10. This makes it possible to use the space between the micro light emitting diode chips 111 without reducing the micro light emitting diode chips 111 to provide the first and second interconnection lines 112 and 113. The first and second interconnection lines 112 and 113 extend in the second direction B and are alternately arranged in the first direction a. That is, along the first direction a, a first interconnection line 112 is provided at one side of the micro light emitting diode chip 111, and a first electrode 114 of the micro light emitting diode chip 111 is connected to the first interconnection line 112 through a wire 116; the other side of the micro light emitting diode chip 111 is provided with a second interconnection line 113, and a second electrode 115 of the micro light emitting diode chip 111 is connected to the second interconnection line 113 through a wire 116.

With continued reference to fig. 2, in a specific embodiment, the peripheral side of the test unit 11 is provided with only the first dicing streets 14 extending along the first direction a. In the wafer 10 of this embodiment, the test units 11 are located between adjacent first scribe lines 14. The first test electrode 12 may be disposed in the first scribe line 14 on one side of the test unit 11, and the second test electrode 13 may be disposed in the first scribe line 14 on the other side of the test unit 11. Stated another way, the first test electrode 12 and the second test electrode 13 may be disposed on opposite sides of the test unit 11.

Fig. 4 is a schematic view of another structure of a wafer according to an embodiment of the present application. As shown in fig. 4, in another specific embodiment, the peripheral side of the test unit 11 may be provided with a plurality of first dicing lanes 14 extending in the first direction a, and a plurality of second dicing lanes 15 extending in the second direction B. Wherein, the first test electrode 12 may be disposed in the first scribe line 14, and the second test electrode 13 may be disposed in the second scribe line 15. In other words, in this embodiment, the first test electrode 12 and the second test electrode 13 may be disposed at adjacent both sides of the test unit 11. Different layouts of the test unit 11, the first test electrode 12 and the second test electrode 13 will be described below.

With continued reference to fig. 2, the plurality of test units 11 of the wafer 10 may include a plurality of first test units 11a and a plurality of second test units 11B alternately arranged along the second direction B. The peripheral side of the test unit 11 is provided with a plurality of first dicing lanes 14 extending in the first direction a. Specifically, between the adjacent first test unit 11a and second test unit 11b, the first scribe line 14 may be provided with one first test electrode 12 and one second test electrode 13. For example, in a specific embodiment, the first test electrode 12, the first test unit 11a, the second test electrode 13, the first test electrode 12, the second test unit 11B, and the second test electrode 13 may be sequentially disposed in the second direction B. Thus, each test unit 11 may correspond to one first test electrode 12 and one second test electrode 13. When testing a selected test unit 11, the probes may be in direct contact with the first test electrode 12 and the second test electrode 13 corresponding to the test unit 11, so that the test unit 11 may be positioned more precisely. In addition, the first and second test electrodes 12 and 13 are disposed at a distance from each other to avoid a short circuit of the first and second test electrodes 12 and 13.

Fig. 5 is a schematic view of another structure of a wafer according to an embodiment of the present application. As shown in fig. 5, the plurality of test units 11 of the wafer 10 may include a plurality of first test units 11a and a plurality of second test units 11B alternately arranged in the second direction B. The peripheral side of the test unit 11 is provided with a plurality of first dicing lanes 14 extending in the first direction a. Specifically, between the adjacent first test unit 11a and second test unit 11b, the first scribe line 14 may be provided with two first test electrodes 12 or two second test electrodes 13. That is, the test electrode is not shared between the adjacent first and second test units 11a and 11b. For example, in a specific embodiment, the first test electrode 12, the first test unit 11a, the second test electrode 13, the second test unit 11B, and the first test electrode 12 may be sequentially disposed in the second direction B.

Fig. 6 is a schematic view of another structure of a wafer according to an embodiment of the present application. As shown in fig. 6, only one first test electrode 12 may be provided in the first scribe line 14 between the adjacent first test unit 11a and second test unit 11b. That is, adjacent first test cells 11a and second test cells 11b may share the same first test electrode 12. Alternatively, a second test electrode 13 may be disposed in the first scribe line 14, that is, the first test unit 11a and the second test unit 11b may share the same second test electrode 13. It will be appreciated that in a particular embodiment, one first scribe line 14 is provided with one first test electrode 12 and the other first scribe line 14 is provided with one second test electrode 13 in any two adjacent first scribe lines 14. With this structural design, adjacent test units 11 can share the same test electrode, so as to reduce the space between the test units 11, thereby increasing the space utilization rate on the wafer 10. In addition, only one test electrode is arranged in one first cutting channel 14, so that the manufacturing cost of the wafer 10 can be reduced, and the manufacturing process of the wafer 10 can be simplified.

In the embodiment of the present application, the specific shape of the test unit 11 is not limited, and may be, for example, a bar shape, a rectangle shape, a circle shape, or an irregular shape. In other embodiments, as shown in fig. 5 and 6, the test cells 11 may be rectangular, and a plurality of test cells 11 on the wafer 10 are distributed in an array. Fig. 7 is a schematic view of another structure of a wafer according to an embodiment of the present application. As shown in fig. 7, in some embodiments, the test units 11 may be strip-shaped, and a plurality of test units 11 on the wafer 10 are disposed in parallel.

In the above embodiment, the first test electrodes 12 of the test cells 11 adjacent in the first direction a may be of a unitary structure, and the second test electrodes 13 of the test cells 11 adjacent in the first direction a may be of a unitary structure. In other words, the first test electrode 12 and the second test electrode 13 are stripe-shaped for easy fabrication. For example, in one particular embodiment, the wafer 10 includes a first test unit 11a, a second test unit 11b, a first test electrode 12, and a second test electrode 13. The first test unit 11a, the second test unit 11B, the first test electrode 12, and the second test electrode 13 are each in a stripe shape, and are sequentially arranged in the second direction B in the order of the first test electrode 12, the first test unit 11a, the second test electrode 13, the second test unit 11B, and the first test electrode 12.

In the embodiment of the present application, since the first test electrode 12, the second test electrode 13, the first interconnection line 112 and the second interconnection line 113 may be made of the same metal material as the first electrode 114 and the second electrode 115 of the micro light emitting diode chip 111, the first test electrode 12, the second test electrode 13, the first interconnection line 112 and the second interconnection line 113 may be fabricated on the same layer as the first electrode 114 and the second electrode 115, so as to simplify the steps of fabricating the wafer 10.

Fig. 8 is a flowchart of a method for fabricating a micro led chip according to an embodiment of the present application, and the micro led chip package is fabricated by the micro led chip 111 of the wafer 10. As shown in fig. 8, the method may include:

step S101, preparing the wafer of the above embodiment on the substrate.

In this step S101, the fabricated wafer 10 includes a plurality of test cells 11, a first test electrode 12, and a second test electrode 13. The test unit 11 includes a plurality of micro light emitting diode chips 111, a first interconnection line 112, and a second interconnection line 113, wherein each micro light emitting diode chip 111 has a first electrode 114 and a second electrode 115. Specifically, the first test electrode 12, the second test electrode 13, the first interconnect line 112 and the second interconnect line 113 may be made of a different metal material than the first electrode 114 and the second electrode 115. In this case, the micro light emitting diode chip 111 may be fabricated first, and then the first interconnection line 112, the second interconnection line 113, the first test electrode 12, and the second test electrode 13 may be fabricated. Alternatively, the first test electrode 12, the second test electrode 13, the first interconnect line 112 and the second interconnect line 113 may be made of the same metal material as the first electrode 114 and the second electrode 115, so that the first test electrode 12, the second test electrode 13, the first interconnect line 112 and the second interconnect line 113 may be made of the same layer as the first electrode 114 and the second electrode 115, that is, the first test electrode 12, the second test electrode 13, the first interconnect line 112, the second interconnect line 113, the first electrode 114 and the second electrode 115 may be made simultaneously by the same process, thereby simplifying the manufacturing steps.

Step S102, testing the micro LED chip of the wafer.

The electrical characteristics of the micro led chip 111 were tested using a wafer test system. In the testing process, the probe is directly contacted and electrically connected with the first test electrode 12 and the second test electrode 13 adjacent to the tested test unit 11, so that the test unit 11 is electrified to judge whether the micro light emitting diode chips 111 in the test unit 11 are qualified or not, and the electrical characteristics of the micro light emitting diode chips 111 are evaluated.

Step S103, removing the first test electrode, the second test electrode, the first interconnect line and the second interconnect line.

In this step S103, since the first test electrode 12, the second test electrode 13, the first interconnect line 112, and the second interconnect line 113 are fabricated on the substrate, the first test electrode 12, the second test electrode 13, the first interconnect line 112, and the second interconnect line 113 may be removed along with the substrate when the substrate is peeled off. Alternatively, the first test electrode 12, the second test electrode 13, the first interconnect line 112 and the second interconnect line 113 may be removed by an etching technique, for example, by a chemical method after photolithography. In this way, the problems of the first electrode 114 and the second electrode 115 being separated from the micro light emitting diode chip 111 or broken wires can be avoided. Meanwhile, in step S103, the conductive line 116 between the first electrode 114 and the first interconnect line 112, and the conductive line 116 between the second electrode 115 and the second interconnect line 113 may also be removed together with the first interconnect line 112 and the second interconnect line 113.

Step S104, dicing the wafer to form a plurality of independent micro LED chips.

After the wafer test is completed, the wafer 10 is diced, so that the micro light emitting diode chips 111 are transferred from the wafer 10, and independent micro light emitting diode chips are obtained.

By adopting the wafer 10 of the above embodiment to manufacture the individual micro light emitting diode chips, on one hand, the first test electrode 12, the second test electrode 13, the first interconnect line 112 and the second interconnect line 113 for testing do not occupy the space of the micro light emitting diode chips 111 on the wafer 10, but use the dicing channels between the micro light emitting diode chips 111, thereby improving the space utilization of the wafer 10; on the other hand, when testing the wafer 10, the probes of the wafer test system do not need to be in direct contact with the micro light emitting diode chips 111 with the first test electrodes 12 and the second test electrodes 13, so that the probes can be prevented from damaging the micro light emitting diode chips 111.

In addition, when the wafer test is performed, the plurality of micro led chips 111 in the test unit 11 can be tested at the same time, thereby improving the test efficiency. And, since each micro light emitting diode chip 111 is electrically connected to the first test electrode 12 and the second test electrode 13, respectively, the voltages applied to each micro light emitting diode chip 111 within the test unit 11 are equal. Therefore, under the same voltage condition, the optical power and the wavelength of the micro light emitting diode chip 111 are relatively uniform, so that the accuracy of the test result can be improved, and when a bad micro light emitting diode chip 111 occurs, the micro light emitting diode chip 111 can be accurately positioned.

Fig. 9 is a schematic diagram of a wafer testing system according to an embodiment of the present application. As shown in fig. 9, the wafer test system 90 includes a power supply 91, a probe 92, a stage 93, a beam splitter 94, an image collector 95, an integrating sphere 96, a spectrometer 97, a power meter 98, and a computer 99. Specifically, the stage 93 is used to carry the wafer 10 to be tested. In some embodiments, the platen 93 may be provided with a temperature control system for controlling the temperature of the wafer 10. In addition, the stage 93 may be further provided with a stage motion control system 931 for controlling the stage 93 to move when the wafer 10 is placed on the stage 93 so that the light beam emitted from the micro led chip 111 of the wafer 10 can be incident on the beam splitter 94. The probe 92 is electrically connected to the power source 91 for electrically connecting with the first test electrode 12 and the second test electrode 13 of the micro led chip 111 of the wafer 10.

When the micro led chip 111 is powered on, the micro led chip 111 operates. A portion of the light beam emitted from the led chip 111 passes through the beam splitter 94 and is directed to the image collector 95, so that a technician can directly observe the led chips 111 that emit light normally, with weak light emission, and without light emission through the image collector 95, and collect the total power and wavelength data of all led chips 111 in the test unit 11. Then, by analyzing the total power and wavelength data, the specific position of the micro light emitting diode chip 111 with the light power problem can be judged, and data is provided for the screening of the subsequent micro light emitting diode chip 111.

Other part of the light beam emitted from the micro led chip 111 passes through the beam splitter 94 and then enters the integrating sphere 96. Integrating sphere 96 analyzes the incoming beam and may transmit the analyzed parameters to spectrometer 97, power meter 98 and computer 99 for detailed evaluation.

Wafer test system 90 may also include an integrating sphere motion control system 961 for controlling the movement of integrating sphere 96 so that it can receive the optical signals emitted by optical splitter 94. And, when a problem occurs in the overall wavelength in the test unit 11, the displacement of the integrating sphere 96 can be controlled by the integrating sphere motion control system 961, so that the integrating sphere 96 precisely scans the wavelength of the micro led chip 111 in the test unit 11, thereby precisely finding out the specific position of the micro led chip 111 with the problem.

In the above-described embodiment, the electrical characteristics of the micro led chip 111 can be evaluated by the spectroscope 94 using the image collector 95, the spectroscope 97, and the power meter 98 at the same time.

The terminology used in the above embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in another embodiment," "in some embodiments," "in other embodiments," and the like in various places throughout this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. The wafer is characterized by comprising a plurality of test units, a first test electrode and a second test electrode, wherein the first test electrode and the second test electrode are arranged on the periphery of the test units, and the wafer comprises the following components:

the test unit comprises a plurality of micro light emitting diode chips, a first interconnecting wire and a second interconnecting wire, wherein the micro light emitting diode chips are distributed in an array, each micro light emitting diode chip is provided with a first electrode and a second electrode, the first electrode is electrically connected with the first interconnecting wire, and the second electrode is electrically connected with the second interconnecting wire;

the periphery of the miniature light emitting diode chip is provided with a cutting channel, the first test electrode and the second test electrode are arranged in the cutting channel, the first interconnection line is electrically connected with the first test electrode, and the second interconnection line is electrically connected with the second test electrode.

2. The wafer of claim 1, wherein the scribe line comprises a plurality of first scribe lines extending in a first direction and disposed in parallel, the first test electrode and/or the second test electrode disposed within the first scribe line;

the test unit is arranged between the first test electrode and the second test electrode.

3. The wafer of claim 2, wherein the scribe line further comprises a plurality of second scribe lines extending in a second direction and disposed in parallel, the second direction being perpendicular to the first direction, the first interconnect line and the second interconnect line disposed within the second scribe line.

4. The wafer of claim 2 or 3, wherein the plurality of test cells comprises a plurality of first test cells and a plurality of second test cells alternately arranged along a second direction, the second direction being perpendicular to the first direction;

one of the first test electrode or the second test electrode is arranged in the first cutting channel between the adjacent first test unit and the second test unit.

5. The wafer of claim 2 or 3, wherein the plurality of test cells comprises a plurality of first test cells and a plurality of second test cells alternately arranged along a second direction, the second direction being perpendicular to the first direction;

two first test electrodes or two second test electrodes are arranged in the first cutting channel between the adjacent first test units and the second test units.

6. The wafer of claim 2 or 3, wherein the plurality of test cells comprises a plurality of first test cells and a plurality of second test cells alternately arranged along a second direction, the second direction being perpendicular to the first direction;

and one first test electrode and one second test electrode are arranged in the first cutting channel between the adjacent first test unit and the second test unit.

7. The wafer of any one of claims 1 to 6, wherein the first test electrode within each scribe line is a unitary structure and the second test electrode within each scribe line is a unitary structure.

8. The wafer of any one of claims 1-7, wherein the first test electrode, the second test electrode, the first interconnect line, the second interconnect line, and the first electrode and the second electrode are co-layer fabricated.

9. A method of fabricating a micro light emitting diode chip, comprising:

preparing the wafer according to any one of claims 1 to 8 on a substrate base plate;

testing the miniature light emitting diode chip of the wafer;

removing the first test electrode, the second test electrode, the first interconnection line and the second interconnection line;

and cutting the wafer to form a plurality of independent miniature light-emitting diode chips.

10. The method of claim 9, wherein the first test electrode, the second test electrode, the first interconnect line, the second interconnect line, the first electrode, and the second electrode are fabricated in the same layer.

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