CN203733822U - Double-silicon wafer lamination solar cell - Google Patents
Double-silicon wafer lamination solar cell Download PDFInfo
- Publication number
- CN203733822U CN203733822U CN201320838091.7U CN201320838091U CN203733822U CN 203733822 U CN203733822 U CN 203733822U CN 201320838091 U CN201320838091 U CN 201320838091U CN 203733822 U CN203733822 U CN 203733822U
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- China
- Prior art keywords
- layer
- silicon
- junction
- solar cell
- polysilicon
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/546—Polycrystalline silicon PV cells
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- Photovoltaic Devices (AREA)
Abstract
The utility model discloses a double-silicon wafer lamination solar cell comprising two polycrystalline silicon or monocrystalline silicon PN junction layers, which are in a superposed serial connection. The upper surface of the upper polycrystalline silicon or monocrystalline silicon PN junction layer is provided with a top electrode layer, and the lower surface is provided with a connecting layer. The lower surface of the lower polycrystalline silicon or monocrystalline silicon PN junction layer is provided with a bottom electrode layer, and the upper surface is provided with a connecting layer. The two polycrystalline silicon or monocrystalline silicon PN junction layers are in a superposed serial connection by the connecting layers. The double-silicon wafer lamination solar cell is advantageous in that by comparing with the common single PN junction monocrystalline silicon or polycrystalline silicon cells, the conversion efficiency can be increased by more than 50-70%, and the actual cost per watt is slightly increased, but the unit area efficiency can be greatly increased.
Description
Technical field
The utility model relates to solar cell, relates in particular to a kind of two silicon wafer lamination solar cell.
Background technology
Developing solar energy is one of the mankind's main approach of solving energy crisis, environmental crisis, and the exploitation of green high-efficient solar cell is key technology and the link of extensive use solar energy.Current silica-based battery comprises that the photoelectric conversion efficiency of hull cell and silicon chip battery is not high, wherein the photoelectric conversion efficiency of ripe business-like polycrystal silicon cell and monocrystalline silicon battery is respectively 15～18.5% and 16.5～19.5%, and real economy is worth limited with saving.
Utility model content
The purpose of this utility model, exactly in order to address the above problem, provides a kind of two silicon wafer lamination solar cell.
In order to achieve the above object, the utility model has adopted following technical scheme: a kind of two silicon wafer lamination solar cells, comprise two polysilicons or the monocrystal silicon PN junction layer of overlapped in series, upper strata polysilicon or monocrystal silicon PN junction layer be provided with top layer electrode layer above, be provided with articulamentum below; Below lower floor's polysilicon or monocrystal silicon PN junction layer, be provided with bottom electrode layer, be provided with articulamentum above; Two polysilicons or monocrystal silicon PN junction layer are by articulamentum overlapped in series separately.
Described polysilicon or monocrystal silicon PN junction layer comprise N-type or the P type basic unit of polysilicon or monocrystalline silicon and are attached to P type or the n type diffused layer in basic unit, the thickness of every polysilicon or monocrystal silicon PN junction layer is 200～2000 nanometers, and wherein the thickness of the N-type of polysilicon or monocrystalline silicon or P type basic unit is 30～300 microns.
Described two polysilicons or monocrystal silicon PN junction layer are by the series connection that unanimously superposes of PN junction direction, and described articulamentum is TCO or ITO transparent conductive material thin layer, and thickness is 10～1000 nanometers.
Described top layer electrode layer comprises internal layer antireflection film layer and top layer TCO conductive film layer, and the thickness of antireflection film layer is 1～150 nanometer, and the thickness of TCO conductive film layer is 20～2000 nanometers.
Described bottom electrode layer comprises internal layer aluminum oxide film rete or silicon oxide film layer and top layer metal level.
Described metal level is double-metal layer structure.
The utility model is than common monolithic PN junction monocrystalline silicon or polycrystal silicon cell, and conversion efficiency increases more than 50～70%, and actual every watt of cost slightly increases, but unit are usefulness significantly increases.
Brief description of the drawings
Fig. 1 is the basic structure schematic diagram of the two silicon wafer lamination solar cells of the utility model.
Embodiment
Referring to Fig. 1, the two silicon wafer lamination solar cells of the utility model, comprise two polysilicons or the monocrystal silicon PN junction layer 1 and 2 of overlapped in series, upper strata polysilicon or monocrystal silicon PN junction layer 1 be provided with top layer electrode layer 3 above, be provided with articulamentum 4 below; Below lower floor's polysilicon or monocrystal silicon PN junction layer 2, be provided with bottom electrode layer 5, be provided with articulamentum 6 above; Two polysilicons or monocrystal silicon PN junction layer are by articulamentum overlapped in series separately.
Above-mentioned two polysilicons or monocrystal silicon PN junction layer 1 and 2 respectively comprise N-type or the P type basic unit 11,21 of polysilicon or monocrystalline silicon and are attached to P type or the n type diffused layer 12,22 in basic unit, the thickness of every polysilicon or monocrystal silicon PN junction layer is 200-2000 nanometer, and wherein the thickness of the N-type of polysilicon or monocrystalline silicon or P type basic unit is 30-300 micron.
Above-mentioned two polysilicons or monocrystal silicon PN junction layer are by the series connection that unanimously superposes of PN junction direction, and its articulamentum 4 and 6 is TCO or ITO transparent conductive material thin layer, and thickness is 10～1000 nanometers.
Top layer electrode layer 3 in the utility model comprises internal layer antireflection film layer 31 and top layer TCO conductive film layer 32, and the thickness of antireflection film layer is 1～150 nanometer, and the thickness of TCO conductive film layer is 20～2000 nanometers.
Bottom electrode layer 5 in the utility model comprises internal layer aluminum oxide film rete 51 or silicon oxide film layer and top layer metal level 52.This metal level can adopt double-metal layer structure.
Of the present utility model pair of silicon wafer lamination solar cell can utilize existing polysilicon or polysilicon photovoltaic cells production line (equipment) to manufacture, and actual process is also relatively simpler.Each rete in battery can pass through the techniques such as physical vapor deposition, sputter and chemical vapour deposition (CVD) to be made.
Claims (6)
1. two silicon wafer lamination solar cells, is characterized in that, comprise two polysilicons or the monocrystal silicon PN junction layer of overlapped in series, upper strata polysilicon or monocrystal silicon PN junction layer be provided with top layer electrode layer above, be provided with articulamentum below; Below lower floor's polysilicon or monocrystal silicon PN junction layer, be provided with bottom electrode layer, be provided with articulamentum above; Two polysilicons or monocrystal silicon PN junction layer are by articulamentum overlapped in series separately.
2. as claimed in claim 1 pair of silicon wafer lamination solar cell, it is characterized in that: described polysilicon or monocrystal silicon PN junction layer comprise N-type or the P type basic unit of polysilicon or monocrystalline silicon and be attached to P type or the n type diffused layer in basic unit, the thickness of every polysilicon or monocrystal silicon PN junction layer is 200～2000 nanometers, and wherein the thickness of the N-type of polysilicon or monocrystalline silicon or P type basic unit is 30～300 microns.
3. as claimed in claim 1 pair of silicon wafer lamination solar cell, it is characterized in that: described two polysilicons or monocrystal silicon PN junction layer are by the series connection that unanimously superposes of PN junction direction, described articulamentum is TCO or ITO transparent conductive material thin layer, and thickness is 10～1000 nanometers.
4. as claimed in claim 1 pair of silicon wafer lamination solar cell, it is characterized in that: described top layer electrode layer comprises internal layer antireflection film layer and top layer TCO conductive film layer, the thickness of antireflection film layer is 1～150 nanometer, and the thickness of TCO conductive film layer is 20～2000 nanometers.
5. as claimed in claim 1 pair of silicon wafer lamination solar cell, is characterized in that: described bottom electrode layer comprises internal layer aluminum oxide film rete or silicon oxide film layer and top layer metal level.
6. as claimed in claim 5 pair of silicon wafer lamination solar cell, is characterized in that: described metal level is double-metal layer structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320838091.7U CN203733822U (en) | 2013-12-18 | 2013-12-18 | Double-silicon wafer lamination solar cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320838091.7U CN203733822U (en) | 2013-12-18 | 2013-12-18 | Double-silicon wafer lamination solar cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203733822U true CN203733822U (en) | 2014-07-23 |
Family
ID=51203870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320838091.7U Expired - Fee Related CN203733822U (en) | 2013-12-18 | 2013-12-18 | Double-silicon wafer lamination solar cell |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203733822U (en) |
-
2013
- 2013-12-18 CN CN201320838091.7U patent/CN203733822U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140723 Termination date: 20151218 |
|
| EXPY | Termination of patent right or utility model |