CN203707114U - Chip-packaging piece made through method of tin-dipping silver-copper alloy - Google Patents
Chip-packaging piece made through method of tin-dipping silver-copper alloy Download PDFInfo
- Publication number
- CN203707114U CN203707114U CN201220738023.9U CN201220738023U CN203707114U CN 203707114 U CN203707114 U CN 203707114U CN 201220738023 U CN201220738023 U CN 201220738023U CN 203707114 U CN203707114 U CN 203707114U
- Authority
- CN
- China
- Prior art keywords
- chip
- tin layer
- inner pin
- tin
- salient point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- Wire Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The utility model discloses a chip-packaging piece made through a method of tin-dipping silver-copper alloy, and the piece mainly consists of an inner pin for a frame, a tin layer, a metal convex point, a chip, and a plastic package body. The metal convex point is formed by the surface of a pressure zone of the chip through the method of tin-dipping silver-copper alloy. A welding zone of the inner pin with the metal convex point is provided with the electroplated tin layer. The tin layer is disposed on the inner pin, and the metal convex point is disposed on the tin layer. The chip is disposed on the metal convex point. The plastic package body covers the inner pin, the tin layer, the metal convex point and the chip completely. The metal convex point, the tin layer and the inner pin form a power and signal channel for a circuit. The piece provided by the utility model is low in cost, and is high in efficiency.
Description
Technical field
The utility model belongs to integrated antenna package technical field, specifically a kind of single-chip package part that utilizes wicking yellow gold method to make.
Background technology
The fast development of microelectric technique, the increase of integrated circuit complexity, most of function of an electronic system all may be integrated in (being SOC (system on a chip)) in a single-chip, and this just correspondingly requires microelectronics Packaging to have higher performance, more lead-in wire, closeer intraconnections, less size or larger chip chamber, larger heat dissipation function, better electrical property, higher reliability, lower single lead-in wire cost etc.Chip package process is changed to wafer level packaging by chip package one by one, and wafer chip level chip encapsulation technology---WLCSP has just in time met these requirements, has formed noticeable WLCSP technique.
Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging, be called for short WLCSP), it is wafer stage chip packaged type, (first cutting again envelope is surveyed to be different from traditional chip package mode, and after encapsulation, at least increase the volume of former chip 20%), this kind of state-of-the-art technology is first on full wafer wafer, to carry out packaging and testing, then just cuts into IC particle one by one, and therefore the volume after encapsulation is equal to the life size of the naked crystalline substance of IC.The packaged type of WLCSP, not only dwindles significantly memory modules size, and meets the high density demand of running gear for body space; In the performance of usefulness, more promote speed and the stability of transfer of data on the other hand.In traditional WLCSP technique, adopt sputter, photoetching, electroplating technology or silk screen printing on wafer, to carry out the mint-mark of circuit.Existing technique is brushed tin cream on chip PAD, then (framework or substrate) is zinc-plated on chip carrier, and then Reflow Soldering forms effective connection.This method can produce higher production cost, and fabrication cycle is longer.Be unfavorable for the realization of product volume production.
Utility model content
The utility model is for above-mentioned existing WLCSP defect, a kind of single-chip package part that utilizes wicking yellow gold method to make proposing, this packaging part is in the time making, use SAC alloy, thereby the high temperature tin ball on chip PAD about chip nip metal A l or Cu Surface Creation 5~50um, i.e. metal salient point layer.No longer adopt traditional sputter, photoetching or silk screen printing, have the advantages that cost is low, efficiency is high.
The technical solution of the utility model is: a kind of single-chip package part that utilizes wicking yellow gold method to make is mainly made up of frame inner pin, tin layer, metal salient point, chip and plastic-sealed body; Described metal salient point adopts wicking yellow gold method to form by the nip surface of chip, the tin layer that the weld zone of described frame inner pin and metal salient point has one deck to electroplate, it on frame inner pin, is tin layer, on tin layer, be on metal salient point, metal salient point, to be that chip, described plastic-sealed body have surrounded frame inner pin, tin layer, metal salient point, chip, chip, metal salient point, tin layer, frame inner pin have formed power supply and the signalling channel of circuit.
A kind of manufacture craft of single-chip package part of utilizing wicking yellow gold method to make is carried out according to following steps: wafer wicking yellow gold forms high temperature tin ball metal salient point, wafer reduction scribing, framework corresponding region tin coating, upper core, Reflow Soldering, plastic packaging, solidifies afterwards, tin, printing, separation of products, inspection, packaging.
brief description of the drawings
Fig. 1 IC chip vertical view;
Single PAD cutaway view on Fig. 2 IC chip;
Cutaway view after Fig. 3 PAD plating salient point;
Fig. 4 framework profile;
The positive PAD corresponding region tin coating figure of Fig. 5 framework;
Product profile after core in Fig. 6 single-chip package;
Fig. 7 single-chip package plastic packaged products profile;
In figure, 1 is that frame inner pin, 2 and 3 is that tin layer, 4 is that metal salient point, 5 is that chip, 6 is that plastic-sealed body, 7 is that metal A l or Cu, 8 are SAC alloy.
Embodiment
As shown in the figure, a kind of single-chip package part that utilizes wicking yellow gold method to make is mainly made up of frame inner pin 1, tin layer 2, metal salient point 4, chip 5 and plastic-sealed body 6; Described metal salient point 4 adopts wicking yellow gold method to form by the nip surface of chip 5; the tin layer 2 that the weld zone of described frame inner pin 1 and metal salient point 4 has one deck to electroplate; it on frame inner pin 1, is tin layer 2; it on tin layer 2, is metal salient point 4; it on metal salient point 4, is chip 5; described plastic-sealed body 6 has surrounded frame inner pin 1, tin layer 2, metal salient point 4, chip 5; and form together the entirety of circuit; plastic-sealed body 6 has played support and protective effect to chip 5, and chip 5, metal salient point 4, tin layer 2, frame inner pin 1 have formed power supply and the signalling channel of circuit.Described tin layer 2 and tin layer 3 are equal to.
As shown in the figure, a kind of manufacture craft of the single-chip package part that utilizes the making of wicking yellow gold method, carry out in accordance with the following steps:
The first step, wicking yellow gold form high temperature tin ball metal salient point: chip PAD immerses in SAC alloy 8, described SAC alloy 8 ratios are tin---90%, silver---8%, Cu---2%, thereby 4 layers of the metal salient points about chip 5 nip metal A l or Cu7 Surface Creation 5~50um, it has replaced traditional sputter, photoetching or silk-screen printing technique, has low cost, high efficiency feature;
Second step, attenuate: thickness thinning is to 50 μ m~200 μ m, and roughness is Ra 0.10mm~0.05mm;
The 3rd step, scribing: the above wafer of 150 μ m is with common scribing process, but thickness wafer below 150 μ m, used double-pole scribing machine and technique thereof;
The 4th step, framework corresponding region tin coating: on frame inner pin 1, the tin layer 2 of one deck 2~50um is electroplated in PAD corresponding region, on chip 5 nips, metal salient point 4 thickness enough in the situation that, can be selected not zinc-plated on frame inner pin 1;
The 5th step, upper core: when upper core, chip 5 is turned around, adopt the technique of Flip-Chip, the metal salient point on chip 54 is welded on framework, do not use DAF film or scolder to connect here, but directly the each metal salient point 4 of chip 5 nip is connected with framework pin; When pressure welding, without routing, in upper core, just complete conducting, the interconnection between chip 4 and pin;
The 6th step, Reflow Soldering: melt tin, object is that good the metal salient point 4 on chip 5 nips and frame inner pin 1 are welded together;
The 7th step, plastic packaging, solidify afterwards, printing, separation of products, inspection, packaging etc. are all identical with common process;
The 8th step, tin, if NiPdAu framework it goes without doing tin.
Claims (1)
1. a single-chip package part that utilizes wicking yellow gold method to make, is characterized in that: be mainly made up of frame inner pin (1), tin layer (2), metal salient point (4), chip (5) and plastic-sealed body (6); The tin layer (2) that the weld zone of described frame inner pin (1) and metal salient point (4) has one deck to electroplate, on frame inner pin (1), be tin layer (2), on tin layer (2), be metal salient point (4), on metal salient point (4), be chip (5), described plastic-sealed body (6) has surrounded frame inner pin (1), tin layer (2), metal salient point (4), chip (5), and chip (5), metal salient point (4), tin layer (2), frame inner pin (1) have formed power supply and the signalling channel of circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201220738023.9U CN203707114U (en) | 2012-12-28 | 2012-12-28 | Chip-packaging piece made through method of tin-dipping silver-copper alloy |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201220738023.9U CN203707114U (en) | 2012-12-28 | 2012-12-28 | Chip-packaging piece made through method of tin-dipping silver-copper alloy |
Publications (1)
Publication Number | Publication Date |
---|---|
CN203707114U true CN203707114U (en) | 2014-07-09 |
Family
ID=51057513
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201220738023.9U Expired - Fee Related CN203707114U (en) | 2012-12-28 | 2012-12-28 | Chip-packaging piece made through method of tin-dipping silver-copper alloy |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN203707114U (en) |
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2012
- 2012-12-28 CN CN201220738023.9U patent/CN203707114U/en not_active Expired - Fee Related
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140709 Termination date: 20201228 |