CN106783790A - There is one kind low resistance three-dimension packaging structure and its process is lost - Google Patents
There is one kind low resistance three-dimension packaging structure and its process is lost Download PDFInfo
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- CN106783790A CN106783790A CN201611192139.6A CN201611192139A CN106783790A CN 106783790 A CN106783790 A CN 106783790A CN 201611192139 A CN201611192139 A CN 201611192139A CN 106783790 A CN106783790 A CN 106783790A
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- plastic packaging
- circuit layer
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- power device
- plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/117—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention relates to one kind there is low resistance three-dimension packaging structure and its process is lost, the described method comprises the following steps：Step one, take metallic carrier；Step 2, metal carrier surface preplating layers of copper；Step 3, plating metal outer pin；Step 4, epoxy resin plastic packaging；Step 5, plating the first metallic circuit layer；Step 6, the first conducting metal post of plating；Step 7, the attachment of the first power device；Step 8, plastic packaging；Step 9, plating the second metallic circuit layer；Step 10, the second conducting metal post of plating；Step 11, the attachment of the second power device；Step 12, plastic packaging；Step 13, plating the 3rd metallic circuit layer；Step 14, plastic packaging；Step 15, carrier etching windowing；Step 10 six, plating anti-oxidant metal layer；Step 10 seven, cutting finished product.The present invention can save the processing step of the back of the body plating metal when power device makes, and save chip cost, and using etch process flow after first encapsulating, power device be imbedded inside substrate, increase the integrated level of whole encapsulating structure.
Description
Technical field
The present invention relates to one kind there is low resistance three-dimension packaging structure and its process is lost, belong to semiconductor packages skill
Art field.
Background technology
In the middle of integrated circuit, power device is an important application field, and so-called power device is exactly by integrated
The working method of electric power controls the work of power electronic device, and high-power output, power are provided using power electronic device
Device is typically operated under conditions of high voltage, high current, generally possesses that high pressure, operating current be big, itself dissipated power is big
The features such as.In general, power device is electrically connected on substrate by way of welding, so this requires power device
Back face metalization makes contact electrode part have good in electrical contact and increases heat dispersion, and back face metalization is power device
Very important technology in part manufacturing process, its quality has requirement very high to reliability, and its technological requirement is also considerably complicated, first
The material selection of first back of the body plating metal will consider the adhesiveness with silicon material, if adhesiveness is bad, cavity is more when forming contact, glues
Knot mechanical strength not enough, increases the thermal contact resistance on interface；Also need to consider in addition wafer, wafer solder and bottom each layer it
Between thermally matched degree, that is, need ensure layers of material between thermal coefficient of expansion it is close, if thermal expansion coefficient difference is larger,
Gap is easily formed between back of the body metal cladding and silicon layer, its unfailing performance is reduced.Particularly with the size wafer of thickness of thin greatly
For procedure for processing it is more difficult, be easy to occur the problem of wafer rupture in processing procedure, so as to reduce production yield.
The content of the invention
The technical problems to be solved by the invention are directed to above-mentioned prior art and provide a kind of three-dimensional with low resistance loss
Encapsulating structure and its process, power device save the processing step of the back of the body plating metal when making, save chip cost, and
And using etch process flow after first encapsulating, power device is imbedded inside substrate, increase the integrated level of whole encapsulating structure, system
It is electrically connected with power device directly electroplating on surface metal in journey, it is possible to decrease resistance loss.
The present invention the used technical scheme that solves the above problems is：It is a kind of that three-dimension packaging structure is lost with low resistance
Process, the described method comprises the following steps：
Step one, take metallic carrier
Step 2, metal carrier surface preplating layers of copper
Step 3, plating metal outer pin
Metal outer pin is formed by plating in metallic carrier front；
Step 4, epoxy resin plastic packaging,
Plastic packaging protection is carried out using epoxide resin material in metal outer pin outer peripheral areas, and makes to draw outside metal by surface grinding
Expose plastic packaging material surface in pin top；
Step 5, plating the first metallic circuit layer
On the plastic packaging material surface of step 4 the first metallic circuit layer is formed by electroplating；
Step 6, the first conducting metal post of plating
By electroplating the first conducting metal post of formation on the first metallic circuit layer of step 5；
Step 7, the attachment of the first power device
The first power device is mounted on the first metallic circuit layer；
Step 8, plastic packaging
First metallic circuit layer, the first conducting metal post and the first power device outer peripheral areas are carried out into plastic packaging using plastic packaging material,
And the first conducting metal post and the first power device back side is exposed plastic packaging material surface by surface grinding；
Step 9, plating the second metallic circuit layer
The second metallic circuit layer is formed by electroplating on the plastic packaging material surface of step 8, is led first by the second metallic circuit layer
Electric metal post and the first power device back side are connected；
Step 10, the second conducting metal post of plating
By electroplating the second conducting metal post of formation on the second metallic circuit layer of step 9；
Step 11, the attachment of the second power device
The second power device is mounted on the second metallic circuit layer；
Step 12, plastic packaging
Second metallic circuit layer, the second conducting metal post and the second power device outer peripheral areas are carried out into plastic packaging using plastic packaging material,
And the second conducting metal post and the second power device back side is exposed plastic packaging material surface by surface grinding；
Step 13, plating the 3rd metallic circuit layer
The 3rd metallic circuit layer is formed by electroplating on the plastic packaging material surface of step 12, by the 3rd metallic circuit layer by second
Conducting metal post and the second power device back side are connected；
Step 14, plastic packaging
3rd metallic circuit layer outer peripheral areas are carried out into plastic packaging using plastic packaging material,
Step 15, carrier etching windowing
Windowing is etched at the metallic carrier back side, exposes the metal outer pin back side；
Step 10 six, plating anti-oxidant metal layer
Anti-oxidant metal layer is formed by plating at the metal outer pin back side exposed；
Step 10 seven, cutting finished product
The semi-finished product that step 10 six completes to electroplate anti-oxidant metal layer are carried out into cutting operation, is made originally with array aggregate side
More than cuttings of the plastic packaging module that formula is integrated are independent, and being obtained, there is low resistance loss three-dimension packaging knot to constitute
Product.
Copper layer thickness in step 2 is at 2 ~ 10 microns.
The preparation method of layers of copper is chemical deposition, electro-deposition or vapour deposition in step 2.
The material of the metal outer pin and metallic circuit layer is copper, aluminium or nickel, and the material of the anti-oxidant metal layer is adopted
With gold, nickel gold, NiPdAu or tin.
Plastic packaging mode uses the mode of mould encapsulating mode, spraying equipment spraying method, pad pasting mode or brush coating.
Engraving method in step 15 is using copper chloride or the etch process of iron chloride.
There is one kind low resistance three-dimension packaging structure is lost, and it includes the first metallic circuit layer, first metallic circuit
Layer front is provided with the first conducting metal post and the first power device, and the first metallic circuit layer back side is provided with outside metal draws
Pin, the metal outer pin outer peripheral areas are encapsulated with pre-packaged material, the first metallic circuit layer, the first conducting metal post and the
One power device outer peripheral areas are encapsulated with the first plastic packaging material, and the first conducting metal capital end and the first power device back side are revealed
Go out the first plastic packaging material, the first plastic packaging material surface is provided with the second metallic circuit layer, the first conducting metal capital end and
It is connected by the second metallic circuit layer between the first power device back side, being provided with second on the second metallic circuit layer leads
Electric metal post and the second power device, the second metallic circuit layer, the second conducting metal post and the second power device periphery bag
Envelope has the second plastic packaging material, and the second plastic packaging material surface is provided with the 3rd metallic circuit layer, the 3rd metallic circuit layer periphery
It is encapsulated with the 3rd plastic packaging material.
Compared with prior art, the advantage of the invention is that：
1st, the power device used in the present invention saves the manufacturing process that metal is electroplated at the back side when chip manufacturing, saves
Complicated chip fabrication technique, can improve chip production yield together, save chip cost；
2nd, packaging process of the invention is to imbed in substrate power device down, then electroplates gold at the power device back side
Belong to layer to be electrically connected with, can so reduce because of the problem that chip thickness ruptures caused by excessively thin, and metal level
Design freedom it is high, can have relatively low resistance loss, and manufacture craft is simple, heat dispersion is also relatively good；
3rd, power device can be imbedded in packaging process of the invention, it is also possible to needed to imbed different type according to function
Component, increase the integrated level of whole encapsulation.
Brief description of the drawings
Fig. 1 ~ Figure 38 is a kind of each operation schematic diagram that three-dimension packaging structural manufacturing process method is lost with low resistance of the present invention.
Figure 39 is a kind of schematic diagram that three-dimension packaging structure is lost with low resistance of the present invention.
Wherein：
Layers of copper 1
Metallic carrier 2
Anti oxidation layer 3
Metal outer pin 4
Pre-packaged material 5
Conductive layer 6
First metallic circuit layer 7
First metal salient point 8
First conducting metal post 9
First plastic packaging material 10
First power device 11
Second metallic circuit layer 12
Second metal salient point 13
Second power device 14
Second conducting metal post 15
Second plastic packaging material 16
3rd metallic circuit layer 17
3rd plastic packaging material 18.
Specific embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
As shown in figure 39, there is the one kind in the present embodiment low resistance three-dimension packaging structure is lost, and it includes the first metal
Line layer 7,7 front of the first metallic circuit layer are provided with the first conducting metal post 9 and the first power device 11, described first
7 back side of metallic circuit layer are provided with metal outer pin 4, and the outer peripheral areas of metal outer pin 4 are encapsulated with pre-packaged material 5, described
First metallic circuit the 7, first conducting metal post 9 of layer and the outer peripheral areas of the first power device 11 are encapsulated with the first plastic packaging material 10, institute
State the top of the first conducting metal post 9 and the back side of the first power device 11 and expose the first plastic packaging material 10, the table of the first plastic packaging material 10
Face is provided with the second metallic circuit layer 12, passes through between the top of the first conducting metal post 9 and the back side of the first power device 11
Second metallic circuit layer 12 is connected, and the second conducting metal post 15 and the second power are provided with the second metallic circuit layer 12
Device 14, the second metallic circuit 12, second conducting metal post 15 of layer and the periphery of the second power device 14 are encapsulated with the second modeling
Envelope material 16, the surface of the second plastic packaging material 16 is provided with the 3rd metallic circuit layer 17, the periphery bag of the 3rd metallic circuit layer 17
The plastic packaging materials 18 of Feng You tri-.
Its process is as follows：
Step one, take metallic carrier
Referring to Fig. 1, the suitable metallic carrier of a piece of thickness is taken, the purpose that this sheet material is used is for circuit makes and circuit Rotating fields
Support is provided, the material of this sheet material is main based on metal material, and the material of metal material can be copper material, and iron material is stainless
The metallics of steel or other electrically conductive functions；
Step 2, metal carrier surface preplating layers of copper
Referring to Fig. 2, in metal carrier surface preplating layers of copper, copper layer thickness at 2 ~ 10 microns, preparation method can be chemical deposition,
Electro-deposition or vapour deposition；
Step 3, photoetching operation
Referring to Fig. 3, the photoresist that can be exposed development is pasted or printed in the metallic carrier front of preplating layers of copper and the back side,
To protect follow-up electroplated metal layer process operation, and the photoresist of metal carrier surface is exposed using exposure imaging equipment
Light, development and removal part photoresist, the graphics field electroplated into row metal outer pin with exposing metal carrier surface to need,
Photoresist can be photoresistance film, or photoresist；
Step 4, plating metal outer pin
Referring to Fig. 4, metallic carrier front removes and electroplated in the region of part photoresist metal outer pin, gold in step 4
Category outer pin material is typically copper, aluminium, nickel etc., or other conducting metal materials；
Step 5, removal photoresist
Referring to Fig. 5, the photoresistance film of metal carrier surface is removed, the method for removing photoresistance film can be softened and be adopted using chemical medicinal liquid
Photoresistance film is removed with the method for high pressure water washing；
Step 6, epoxy resin plastic packaging,
Referring to Fig. 6, plastic packaging protection, ring are carried out using epoxide resin material in the positive metal outer pin outer peripheral areas of metallic carrier
Oxygen resin material can have filler or species without filler according to product performance selection, and plastic packaging mode can be filled using mould
The mode of glue mode, spraying equipment spraying method, pad pasting mode or brush coating；
Step 7, surface grinding
Referring to Fig. 7, epoxy resin surface grinding is carried out after epoxy resin plastic packaging is completed, it is therefore an objective to reveal metal outer pin top
Go out the thickness of plastic-sealed body surface and control epoxy resin；
It is prepared by step 8, epoxy resin surface conductive layer
Referring to Fig. 8, epoxy resin surface after grinding carries out conductive layer preparation；Conductive layer can be metal class material, such as nickel,
Titanium, copper, silver etc., it is also possible to make radio frequency macromolecular material, such as polyaniline, polypyrrole, polythiophene.Depositional mode is usual
It is chemical deposition, vapour deposition, sputtering etc.；
Step 9, photoetching operation
Referring to Fig. 9, the photoresist that can be exposed development is pasted or printed in step 8 metallic carrier front, and using exposure
Developing apparatus is exposed to photoresist, develops and removal part photoresist, is carried out with exposing metal carrier surface needs
The graphics field of the first metallic circuit layer plating, photoresist can be photoresistance film, or photoresist；
Step 10, plating the first metallic circuit layer
Referring to Figure 10, metallic carrier front removes and electroplated in the region of part photoresist the first metallic circuit in step 9
Layer, the first metallic circuit layer material is typically copper, aluminium, nickel etc., or other conducting metal materials；
Step 11, photoetching operation
Referring to Figure 11, the photoresist that can be exposed development is pasted or printed in step 10 metallic carrier front, and using exposure
Photodevelopment equipment is exposed to photoresist, develop and removal part photoresist, with expose metal carrier surface need into
The graphics field of the first conducting metal of row post plating, photoresist can be photoresistance film, or photoresist；
Step 12, the first conducting metal post of plating
Referring to Figure 12, the first conducting metal is electroplated in the region of metallic carrier front removal part photoresist in the step 11
Post, conducting and connection that the first conducting metal post is used between three-dimension packaging structure；
Step 13, removal photoresist
Referring to Figure 13, the photoresistance film of metal carrier surface is removed, the method for removing photoresistance film can be softened simultaneously using chemical medicinal liquid
Photoresistance film is removed using the method for high pressure water washing；
Step 14, fast-etching
Referring to Figure 14, the conductive layer that removal metallic carrier front is exposed；
Step 15, the attachment of the first power device
Referring to Figure 15, the first power device and the chip needed for other, the first power device are mounted on the first metallic circuit layer
Part can be control chip or MOS chips；
Step 10 six, plastic packaging
Referring to Figure 16, the metallic carrier front in step 15 is carried out into plastic packaging using plastic packaging material, plastic packaging mode can use mould
Have encapsulating mode, compression encapsulating, spraying method or use pad pasting mode, described can using has packing material or no-arbitrary pricing thing
The epoxy resin of matter；
Step 10 seven, surface grinding
Referring to Figure 17, epoxy resin surface grinding is carried out after epoxy resin plastic packaging is completed, it is therefore an objective to make the first conducting metal post
With the thickness that plastic-sealed body surface and control epoxy resin are exposed in the first power device top；
It is prepared by step 10 eight, epoxy resin surface conductive layer
Referring to Figure 17, the epoxy resin surface after the grinding of step 10 seven carries out conductive layer preparation；Conductive layer can be metal class
Material, such as nickel, titanium, copper, silver, it is also possible to make radio frequency macromolecular material, such as polyaniline, polypyrrole, polythiophene.It is heavy
Product mode is usually chemical deposition, vapour deposition, sputtering etc.；
Step 10 nine, photoetching operation
Referring to Figure 19, the photoresist that can be exposed development, and profit are pasted or printed in the metallic carrier front of step 10 eight
Photoresist is exposed with exposure imaging equipment, is developed and removal part photoresist, needed with exposing metal carrier surface
The graphics field of the second metallic circuit layer plating is carried out, photoresist can be photoresistance film, or photoresist；
Step 2 ten, plating the second metallic circuit layer
Referring to Figure 20, metallic carrier front removes and electroplated in the region of part photoresist the second metal wire in step 10 nine
, be connected for the first conducting metal post and the first power device top by the second metallic circuit layer by road floor, metallic circuit layer material
Material is typically copper, aluminium, nickel etc., or other conducting metal materials；
Step 2 11, photoetching operation
Referring to Figure 21, the photoresist that can be exposed development is pasted or printed in the metallic carrier front of step 2 ten, and utilize
Exposure imaging equipment is exposed to photoresist, develops and removal part photoresist, to expose metal carrier surface needs
The graphics field of the second conducting metal post plating is carried out, photoresist can be photoresistance film, or photoresist；
Step 2 12, the second conducting metal post of plating
Referring to Figure 22, the second conductive gold is electroplated in the region of metallic carrier front removal part photoresist in the step 2 11
Category post, conducting and connection that the second conducting metal post is used between three-dimension packaging structure；
Step 2 13, removal photoresist
Referring to Figure 23, the photoresistance film of metal carrier surface is removed, the method for removing photoresistance film can be softened simultaneously using chemical medicinal liquid
Photoresistance film is removed using the method for high pressure water washing；
Step 2 14, fast-etching
Referring to Figure 24, the conductive layer that removal metallic carrier front is exposed；
Step 2 15, the attachment of the second power device
Referring to Figure 25, the second power device is mounted on the second metallic circuit layer, the second power device is control chip or MOS cores
Piece；
Step 2 16, plastic packaging
Referring to Figure 26, the metallic carrier front in step 2 15 is carried out into plastic packaging using plastic packaging material, plastic packaging mode can be used
Mould encapsulating mode, compression or use pad pasting mode at encapsulating, spraying method, and described can using has packing material or no-arbitrary pricing
The epoxy resin of material；
Step 2 17, surface grinding
Referring to Figure 27, epoxy resin surface grinding is carried out after epoxy resin plastic packaging is completed, it is therefore an objective to make the second conducting metal post
With the thickness that plastic-sealed body surface and control epoxy resin are exposed in the second power device top；
It is prepared by step 2 18, epoxy resin surface conductive layer
Referring to Figure 27, the epoxy resin surface after the grinding of step 2 17 carries out conductive layer preparation；Conductive layer can be metal
Class material, such as nickel, titanium, copper, silver, it is also possible to make radio frequency macromolecular material, such as polyaniline, polypyrrole, polythiophene.
Depositional mode is usually chemical deposition, vapour deposition, sputtering etc.；
Step 2 19, photoetching operation
Referring to Figure 29, the photoresist that can be exposed development is pasted or printed in the metallic carrier front of step 2 18, and
Photoresist is exposed using exposure imaging equipment, is developed and removal part photoresist, to expose metal carrier surface
Need to carry out the graphics field that the 3rd metallic circuit layer is electroplated, photoresist can be photoresistance film, or photoresist；
Step 3 ten, plating the 3rd metallic circuit layer
Referring to Figure 30, metallic carrier front removes and electroplated in the region of part photoresist the 3rd metal in step 2 19
, be connected for the second conducting metal post and the second power device top by the 3rd metallic circuit layer by line layer, metallic circuit layer
Material is typically copper, aluminium, nickel etc., or other conducting metal materials；
Step 3 11, removal photoresist
Referring to Figure 31, the photoresistance film of metal carrier surface is removed, the method for removing photoresistance film can be softened simultaneously using chemical medicinal liquid
Photoresistance film is removed using the method for high pressure water washing；
Step 3 12, fast-etching
Referring to Figure 32, the conductive layer that removal metallic carrier front is exposed；
Step 3 13, plastic packaging
Referring to Figure 33, the metallic carrier front in step 3 12 is carried out into plastic packaging using plastic packaging material, plastic packaging mode can be used
Mould encapsulating mode, compression or use pad pasting mode at encapsulating, spraying method, and described can using has packing material or no-arbitrary pricing
The epoxy resin of material；
Step 3 14, photoetching operation
Referring to Figure 34, the photoresist that can be exposed development is pasted or printed at the metallic carrier back side of step 3 13, and
Photoresist is exposed using exposure imaging equipment, is developed and removal part photoresist, to expose metal carrier surface
The graphics field that needs are etched, photoresist can be photoresistance film, or photoresist.
The etching windowing of step 3 15, carrier
Referring to Figure 35, the region of metallic carrier back side removal part photoresist carries out chemical etching and opens in step 3 14
Window, engraving method can be using copper chloride or the etch process of iron chloride；
Step 3 16, removal photoresist
Referring to Figure 36, the photoresistance film of metal carrier surface is removed, the method for removing photoresistance film can be softened simultaneously using chemical medicinal liquid
Photoresistance film is removed using the method for high pressure water washing；
Step 3 17, plating anti-oxidant metal layer
Referring to Figure 37, after removing photoresist in step 3 16, the exposed metal surface of metal carrier surface is carried out
Anti-oxidant metal layer is electroplated, such as gold, nickel gold, NiPdAu, tin；
Step 3 18, cutting finished product
Referring to Figure 38, the semi-finished product that step 3 17 completes plating anti-oxidant metal layer are carried out into cutting operation, made originally with battle array
More than cuttings of the plastic packaging module that column aggregate mode is integrated are independent, and being obtained, there is low resistance three-dimensional is lost
Encapsulating structure finished product.
In addition to the implementation, present invention additionally comprises having other embodiment, all use equivalents or equivalence replacement
The technical scheme that mode is formed, all should fall within the scope of the hereto appended claims.
Claims (2)
1. it is a kind of with low resistance be lost three-dimension packaging structure process, it is characterised in that methods described include following step
Suddenly：
Step one, take metallic carrier
Step 2, metal carrier surface preplating layers of copper
Step 3, plating metal outer pin
Metal outer pin is formed by plating in metallic carrier front；
Step 4, epoxy resin plastic packaging,
Plastic packaging protection is carried out using epoxide resin material in metal outer pin outer peripheral areas, and makes to draw outside metal by surface grinding
Expose plastic packaging material surface in pin top；
Step 5, plating the first metallic circuit layer
On the plastic packaging material surface of step 4 the first metallic circuit layer is formed by electroplating；
Step 6, the first conducting metal post of plating
By electroplating the first conducting metal post of formation on the first metallic circuit layer of step 5；
Step 7, the attachment of the first power device
The first power device is mounted on the first metallic circuit layer；
Step 8, plastic packaging
First metallic circuit layer, the first conducting metal post and the first power device outer peripheral areas are carried out into plastic packaging using plastic packaging material,
And the first conducting metal post and the first power device back side is exposed plastic packaging material surface by surface grinding；
Step 9, plating the second metallic circuit layer
The second metallic circuit layer is formed by electroplating on the plastic packaging material surface of step 8, is led first by the second metallic circuit layer
Electric metal post and the first power device back side are connected；
Step 10, the second conducting metal post of plating
By electroplating the second conducting metal post of formation on the second metallic circuit layer of step 9；
Step 11, the attachment of the second power device
The second power device is mounted on the second metallic circuit layer；
Step 12, plastic packaging
Second metallic circuit layer, the second conducting metal post and the second power device outer peripheral areas are carried out into plastic packaging using plastic packaging material,
And the second conducting metal post and the second power device back side is exposed plastic packaging material surface by surface grinding；
Step 13, plating the 3rd metallic circuit layer
The 3rd metallic circuit layer is formed by electroplating on the plastic packaging material surface of step 12, by the 3rd metallic circuit layer by second
Conducting metal post and the second power device back side are connected；
Step 14, plastic packaging
3rd metallic circuit layer outer peripheral areas are carried out into plastic packaging using plastic packaging material,
Step 15, carrier etching windowing
Windowing is etched at the metallic carrier back side, exposes the metal outer pin back side；
Step 10 six, plating anti-oxidant metal layer
Anti-oxidant metal layer is formed by plating at the metal outer pin back side exposed；
Step 10 seven, cutting finished product
The semi-finished product that step 10 six completes to electroplate anti-oxidant metal layer are carried out into cutting operation, is made originally with array aggregate side
More than cuttings of the plastic packaging module that formula is integrated are independent, and being obtained, there is low resistance loss three-dimension packaging knot to constitute
Product.
It is 2. a kind of that there is low resistance three-dimension packaging structure is lost, it is characterised in that：It includes the first metallic circuit layer（7）, it is described
First metallic circuit layer（7）Front is provided with the first conducting metal post（9）With the first power device（11）, first metal wire
Road floor（7）The back side is provided with metal outer pin（4）, the metal outer pin（4）Outer peripheral areas are encapsulated with pre-packaged material（5）, institute
State the first metallic circuit layer（7）, the first conducting metal post（9）With the first power device（11）Outer peripheral areas are encapsulated with the first plastic packaging
Material（10）, the first conducting metal post（9）Top and the first power device（11）Expose the first plastic packaging material in the back side（10）, it is described
First plastic packaging material（10）Surface is provided with the second metallic circuit layer（12）, the first conducting metal post（9）Top and the first work(
Rate device（11）By the second metallic circuit layer between the back side（12）It is connected, the second metallic circuit layer（12）On be provided with
Second conducting metal post（15）With the second power device（14）, the second metallic circuit layer（12）, the second conducting metal post
（15）With the second power device（14）Periphery is encapsulated with the second plastic packaging material（16）, second plastic packaging material（16）Surface is provided with
Three metallic circuits layer（17）, the 3rd metallic circuit layer（17）Periphery is encapsulated with the 3rd plastic packaging material（18）.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611192139.6A CN106783790A (en) | 2016-12-21 | 2016-12-21 | There is one kind low resistance three-dimension packaging structure and its process is lost |
| PCT/CN2017/116046 WO2018113573A1 (en) | 2016-12-21 | 2017-12-14 | Three-dimensional packaging structure having low resistance loss and process method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611192139.6A CN106783790A (en) | 2016-12-21 | 2016-12-21 | There is one kind low resistance three-dimension packaging structure and its process is lost |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106783790A true CN106783790A (en) | 2017-05-31 |
Family
ID=58893651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611192139.6A Pending CN106783790A (en) | 2016-12-21 | 2016-12-21 | There is one kind low resistance three-dimension packaging structure and its process is lost |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN106783790A (en) |
| WO (1) | WO2018113573A1 (en) |
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| WO2018113573A1 (en) * | 2016-12-21 | 2018-06-28 | 江苏长电科技股份有限公司 | Three-dimensional packaging structure having low resistance loss and process method therefor |
| CN112349603A (en) * | 2019-08-07 | 2021-02-09 | 天芯互联科技有限公司 | Manufacturing method of power device, power device and electronic equipment |
| CN112992874A (en) * | 2019-12-17 | 2021-06-18 | 天芯互联科技有限公司 | Manufacturing method of packaging structure and packaging structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112864022B (en) * | 2019-11-26 | 2024-03-22 | 天芯互联科技有限公司 | Manufacturing method of packaging structure and packaging structure |
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Also Published As
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| WO2018113573A1 (en) | 2018-06-28 |
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