CN112366197A - Lead frame for chip packaging, preparation method and chip packaging structure - Google Patents
Lead frame for chip packaging, preparation method and chip packaging structure Download PDFInfo
- Publication number
- CN112366197A CN112366197A CN202011273348.XA CN202011273348A CN112366197A CN 112366197 A CN112366197 A CN 112366197A CN 202011273348 A CN202011273348 A CN 202011273348A CN 112366197 A CN112366197 A CN 112366197A
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- layer
- base island
- solder resist
- resist ink
- electrode
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title abstract description 16
- 229910000679 solder Inorganic materials 0.000 claims abstract description 125
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000011159 matrix material Substances 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 294
- 239000002585 base Substances 0.000 claims description 128
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 65
- 239000011889 copper foil Substances 0.000 claims description 63
- 239000002184 metal Substances 0.000 claims description 63
- 229910052751 metal Inorganic materials 0.000 claims description 63
- 238000004519 manufacturing process Methods 0.000 claims description 33
- 239000003513 alkali Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 25
- 238000007747 plating Methods 0.000 claims description 23
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 238000005260 corrosion Methods 0.000 claims description 11
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 239000002131 composite material Substances 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 239000004332 silver Substances 0.000 claims description 8
- 239000011135 tin Substances 0.000 claims description 8
- 229910052718 tin Inorganic materials 0.000 claims description 8
- 230000007797 corrosion Effects 0.000 claims description 7
- 239000002253 acid Substances 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 10
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000010953 base metal Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a lead frame for chip packaging, a preparation method and a chip packaging structure. The lead frame comprises a bearing sheet, a first solder resist ink layer and a plurality of unit circuits arranged in a matrix, wherein each unit circuit comprises a plurality of electrodes, and each electrode comprises a top electrode and a bottom electrode; the top electrode is arranged on the top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer comprises a bottom electrode hole corresponding to the electrode, the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the bearing sheet is detachably adhered to the first solder resist ink layer and the bottom surface of the bottom electrode. The lead frame of the invention has the advantages of few preparation process steps, simple process and lower cost.
Description
[ technical field ]
The invention relates to chip packaging, in particular to a lead frame for chip packaging, a preparation method and a chip packaging structure.
[ background art ]
The lead frame mainly functions as a carrier for providing mechanical support for the chip, and is used as a conductive medium for connecting the chip circuit inside and outside to form an electric signal path and a heat dissipation path for dissipating heat generated during the operation of the chip together with the package shell.
The invention with the application number of CN202010538887.5 discloses a lead frame for chip packaging and a preparation method thereof. The lead frame comprises a substrate, a base island and a plurality of pins arranged around the periphery of the base island, wherein the base island comprises an upper base island arranged above the substrate, a lower base island arranged below the substrate, a penetrating substrate and a metal island for connecting the upper base island with the lower base island, the pins comprise an upper pin arranged above the substrate, a lower pin arranged below the substrate, a penetrating substrate and a metal column for connecting the upper pin with the lower pin. The electrophoretic resin is filled in the groove etched by the copper foil as a substrate, the copper foil is etched by covering a photosensitive film, the depth of the groove etched by the copper foil is difficult to match with the thickness of the electrophoretic resin, the curing process of the electrophoretic resin can generate great influence on the film removing performance of the photosensitive layer, and the plating cylinder of the electrophoretic process needs strict maintenance.
[ summary of the invention ]
The invention aims to provide a lead frame which has fewer preparation process steps and simple process.
The invention also aims to solve the technical problem of providing the lead frame preparation method which has fewer preparation process steps and simple process.
The invention also aims to solve the technical problem of providing a chip packaging structure with few steps and simple process for manufacturing the lead frame.
In order to solve the technical problems, the invention adopts the technical scheme that the lead frame for chip packaging comprises a bearing sheet, a first solder resist ink layer and a plurality of unit circuits arranged according to a matrix, wherein each unit circuit comprises a plurality of electrodes, and each electrode comprises a top electrode and a bottom electrode; the top electrode is arranged on the top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer comprises a bottom electrode hole corresponding to the electrode, the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the bearing sheet is detachably adhered to the first solder resist ink layer and the bottom surface of the bottom electrode.
In the lead frame, the unit circuit comprises a base island, the base island comprises an upper base island and a lower base island, and the upper base island is arranged on the top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer comprises a base island hole, and the lower base island is arranged in the base island hole; the top of the lower base island is fixed on the bottom surface of the upper base island; the bearing sheet is detachably adhered to the bottom surface of the lower base island.
In the lead frame, the transverse size of the top electrode is larger than that of the bottom electrode, and the top electrode completely covers the bottom electrode hole; the transverse size of the upper base island is larger than that of the lower base island, and the upper base island completely covers the base island hole; the height of the upper base island is the same as the height of the top electrode.
In the lead frame, the top electrode comprises the copper foil layer arranged on the top surface of the first solder resist ink layer and the weldable metal layer electroplated on the top surface of the copper foil layer; the bottom electrode comprises a bottom electrode hole filled in the first solder resist ink layer, an alkali corrosion resistant metal layer electroplated on the bottom surface of the top electrode and a weldable metal layer electroplated on the bottom surface of the alkali corrosion resistant metal layer.
In the lead frame, the upper base island comprises the copper foil layer arranged on the top surface of the first solder resist ink layer and the weldable metal layer electroplated on the top surface of the copper foil layer; the lower base island comprises an alkali-resistant metal layer which is filled in the base island holes of the first solder-resistant ink layer and is plated on the bottom surface of the upper base island.
The lead frame is characterized in that the alkali corrosion resistant metal layer is a nickel plating layer, a tin plating layer and a silver plating layer or a composite plating layer of at least two of nickel, tin and silver, and the weldable metal layer is a composite plating layer of at least two of a copper plating layer, a nickel plating layer, a tin plating layer, a silver plating layer, an gold plating layer or a copper plating layer, a nickel plating layer, a tin plating layer, a silver plating layer and a gold plating layer.
The lead frame comprises a second solder resist ink layer, wherein the second solder resist ink layer covers the first solder resist ink layer and the top electrode; the second solder resist ink layer includes a window, and the pad of the top electrode is disposed in the window of the second solder resist ink layer.
The preparation method of the lead frame comprises the following steps:
801) pasting a bearing film on the top surface of the copper foil, and printing a first solder resist ink layer on the bottom surface of the copper foil;
802) photoetching a bottom electrode hole on the first solder mask ink layer, plating a metal layer on the bottom surface of the copper foil in the bottom electrode hole, and forming a bottom electrode filled in the bottom electrode hole;
803) the bearing sheet is detachably adhered to the first solder resist ink layer and the bottom surface of the bottom electrode;
804) stripping the carrier film on the top surface of the copper foil, and covering a photosensitive layer on the top surface of the copper foil;
805) the photosensitive layer is subjected to photoetching to manufacture a hollow pattern corresponding to the top electrode, the copper foil is etched, and the top electrode is formed above the first solder resist ink layer.
The preparation method comprises the following steps:
901) the unit circuit comprises a base island, wherein the base island comprises an upper base island and a lower base island; in step 802, a base island hole corresponding to each unit circuit is photo-etched on the first solder resist ink layer, and a metal layer is plated on the bottom surface of the copper foil in the base island hole to form a lower base island filled in the base island hole;
902) in step 803, the carrier sheet is simultaneously releasably adhered to the bottom surface of the lower base island;
903) in step 805, the pattern formed by photolithography of the photosensitive layer includes a pattern corresponding to the upper base island, and when the copper foil is etched, the upper base island is simultaneously formed on the first solder resist ink layer.
The preparation method comprises the following steps:
1001) in step 805, the physical part of the photo-sensitive layer hollow pattern corresponds to the shape of the top electrode;
1002) performing acid etching on the copper foil, and etching the copper foil exposed out of the hollow pattern;
1003) and removing the photosensitive layer, and plating a weldable metal layer on the copper foil remained after etching to form the top electrode.
The preparation method comprises the following steps:
1101) in step 805, the hollow portion of the hollow pattern of the photosensitive layer corresponds to the shape of the top electrode;
1102) electroplating an alkali-corrosion-resistant weldable metal layer on the top surface of the copper foil at the hollow part of the photosensitive layer;
1103) and removing the photosensitive layer, carrying out alkaline etching on the copper foil, etching the weldable metal layer which is not plated with the alkaline etching resistance and the exposed copper foil to form the top electrode.
In the above preparation method, after step 805 is completed, a second solder resist ink layer is printed over the first solder resist ink layer and the top electrode; the second solder resist ink layer includes a window, and the pad of the top electrode is disposed in the window of the second solder resist ink layer.
A chip packaging structure comprises a chip, a packaging adhesive layer, a plurality of electrodes and a first solder resist ink layer, wherein the electrodes comprise top electrodes and bottom electrodes, and the top electrodes are arranged on the top surface of the first solder resist ink layer; the first solder resist ink layer comprises a bottom electrode hole corresponding to the electrode, and the bottom electrode hole is positioned right below the top electrode; the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the packaging adhesive layer covers the first solder resist ink layer and the top electrode, the chip is packaged in the packaging adhesive layer, and the plurality of electrodes of the chip are electrically connected with the plurality of top electrodes respectively.
The lead frame of the invention has the advantages of few preparation process steps, simple process and lower cost.
[ description of the drawings ]
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic view of step 1 of a lead frame manufacturing method according to embodiment 2 of the present invention.
Fig. 2 is a schematic view of the first step of step 2 of the lead frame manufacturing method according to embodiment 2 of the present invention.
Fig. 3 is a schematic view of the second step of step 2 of the lead frame manufacturing method of embodiment 2 of the present invention.
Fig. 4 is a schematic view of step 3 of a lead frame manufacturing method according to embodiment 2 of the present invention.
Fig. 5 is a schematic view of the first step of step 4 of the lead frame manufacturing method according to embodiment 2 of the present invention.
Fig. 6 is a schematic view of the second step of step 4 of the lead frame manufacturing method of embodiment 2 of the present invention.
Fig. 7 is a schematic view of step 5 of a lead frame manufacturing method according to embodiment 2 of the present invention.
Fig. 8 is a schematic view of the first step of step 6 of the lead frame manufacturing method according to embodiment 2 of the present invention.
Fig. 9 is a schematic view of the second step of step 6 of the lead frame manufacturing method of embodiment 2 of the present invention.
Fig. 10 is a schematic view of step 7 of the lead frame manufacturing method according to embodiment 2 of the present invention.
Fig. 11 is a structural view of a lead frame in embodiment 1 of the present invention.
Figure 12 is a structural diagram of a flip LED chip package structure according to embodiment 4 of the present invention,
fig. 13 is a schematic view of step 5 of a lead frame manufacturing method according to embodiment 3 of the present invention.
Fig. 14 is a schematic view of lead frame manufacturing method step 6 according to embodiment 3 of the present invention.
Fig. 15 is a schematic view of the first step of step 7 of the lead frame manufacturing method according to embodiment 3 of the present invention.
Fig. 16 is a schematic view of the second step of step 7 of the lead frame manufacturing method of embodiment 3 of the present invention.
Fig. 17 is a structural view of another form of the lead frame according to embodiment 1 of the present invention.
Fig. 18 is a schematic view of the first step of step 1 of the lead frame manufacturing method according to embodiment 6 of the present invention.
Fig. 19 is a schematic view of the second step of step 1 of the lead frame manufacturing method according to embodiment 6 of the present invention.
Fig. 20 is a schematic view of step 2 of a lead frame manufacturing method according to embodiment 6 of the present invention.
Fig. 21 is a schematic view of lead frame manufacturing method step 3 according to embodiment 6 of the present invention.
Fig. 22 is a schematic view of lead frame manufacturing method step 4 according to embodiment 6 of the present invention.
Fig. 23 is a schematic view of lead frame manufacturing method step 5 according to embodiment 6 of the present invention.
Fig. 24 is a structural view of a lead frame in embodiment 5 of the present invention.
Fig. 25 is a schematic view of lead frame manufacturing method step 1 according to embodiment 7 of the present invention.
Fig. 26 is a schematic view of step 2 of the lead frame manufacturing method according to embodiment 7 of the present invention.
Fig. 27 is a schematic view of lead frame manufacturing method step 3 according to embodiment 7 of the present invention.
Fig. 28 is a structural view of another form of a lead frame according to embodiment 5 of the present invention.
Fig. 29 is a structural diagram of a package structure in which a chip is mounted in embodiment 8 of the present invention.
[ detailed description of the invention ]
The structure of a unit circuit of a lead frame for chip packaging in embodiment 1 of the present invention is shown in fig. 11, and includes a carrier sheet 2, a solder resist ink layer 3, a second solder resist ink layer, and a plurality of unit circuits arranged in a matrix, where each unit circuit includes two electrodes, and the electrodes include a top electrode 11 and a bottom electrode 12. The top electrode 11 is arranged on the top surface of the solder resist ink layer 3. The solder resist ink layer 3 includes two bottom electrode holes 31 corresponding to each unit circuit, the bottom electrodes 12 are arranged in the bottom electrode holes 31, and the tops of the bottom electrodes 12 are fixed on the bottom surface of the top electrode 11. The carrier sheet 2 is releasably adhered to the solder resist ink layer 3 and the bottom surface of the bottom electrode 12.
In the present embodiment, the lateral dimension of the top electrode 11 is larger than the lateral dimension of the bottom electrode 12, the top electrode 11 can cover the bottom electrode hole 31 on the whole, and the structural feature is mainly to block the corrosion of the alkali solution to the bottom electrode 12 during the alkali etching to protect the bottom electrode 12, and when the bottom electrode 12 is made of alkali-resistant metal, it is not necessary that the top electrode 11 cover the bottom electrode hole 31 on the whole.
The top electrode 11 comprises a copper foil layer 1 disposed on the top surface of the solder resist ink layer 3 and a solderable metal layer 112 plated on the top surface of the copper foil layer 1, the solderable metal layer 112 on the top surface of the copper foil layer 1 may cover the entire outer surface of the top electrode 11, and the solderable metal layer 112 on the top surface of the copper foil layer 1 may cover only the outer surface of the solder pad portion of the top electrode 11. The bottom electrode 12 includes an alkali-resistant metal layer 121 plated on the bottom surface of the top electrode 11 and a solderable metal layer 122 plated on the bottom surface of the alkali-resistant metal layer 121, which are filled in the bottom electrode hole 31 of the solder resist ink layer 3.
The alkali-resistant metal layer 121 may be a nickel-plated layer, a tin-plated layer, a silver-plated layer, or a composite plated layer of at least two of nickel, tin, and silver, and the solderable metal layer 122 may be a tin-plated layer, a silver-plated layer, or a gold-plated layer.
The solder resist ink layer 7 is covered over the solder resist ink layer 3 and the top electrode 11. The solder resist ink layer 7 is opened with a window, and the pad portion of the top electrode 11 is disposed in the window of the second solder resist ink.
1) as shown in fig. 1, a carrier film 10 is attached to the top surface of a copper foil 1, and photosensitive ink is printed on the bottom surface of the copper foil 1 to form a solder resist ink layer 3.
2) As shown in fig. 2, two bottom electrode holes 31 are photo-etched for each unit circuit on the solder resist ink layer 3. As shown in fig. 3, the bottom surface of copper foil 1 is plated with a metal layer in bottom electrode hole 31, thereby forming bottom electrode 12 filled in bottom electrode hole 31. The metal layer plated on the bottom electrode 12 includes an alkali-resistant metal layer 121 plated on the bottom surface of the top electrode 11 and a solderable metal layer 122 plated on the bottom surface of the alkali-resistant metal layer 121. The alkali-resistant metal layer 121 may be a nickel-plated layer, a tin-plated layer, a silver-plated layer, or a composite plated layer of at least two of nickel, tin, and silver, and the solderable metal layer 122 may be a tin-plated layer, a silver-plated layer, or a gold-plated layer.
3) As shown in fig. 4, the carrier sheet 2 is releasably adhered to the solder resist ink layer 3 and the bottom surface of the bottom electrode 12.
4) As shown in fig. 5, the carrier film 10 on the top surface of the copper foil 1 is peeled off, and as shown in fig. 6, the top surface of the copper foil 1 is covered with the photosensitive layer 6.
5) As shown in fig. 7, the photosensitive layer is patterned by photolithography to form a hollow pattern corresponding to each unit circuit top electrode 11, and the remaining solid portion 61 of the hollow pattern of the photosensitive layer corresponds to the shape of the top electrode 11.
6) As shown in fig. 8, the copper foil 1 is subjected to acid etching to etch away the copper foil 1 with the hollow pattern exposed, and as shown in fig. 9, the photosensitive layer 6 is removed to form a main portion of the top electrode 11.
7) As shown in fig. 10, the solder resist ink layer 7 is printed over the solder resist ink layer 3 and the main portion of the top electrode 11. The solder resist ink layer 7 opens the window 71, and the pad portion 111 of the top electrode 11 is exposed in the window of the second solder resist ink.
8) As shown in fig. 11, the pad portion 111 of the top electrode 11 is plated with a solderable metal layer 112, and the solderable metal layer 112 may be a tin-plated layer, a silver-plated layer, or a gold-plated layer, to obtain a lead frame according to embodiment 1 of the present invention.
5) as shown in fig. 13, the photosensitive layer 6 is patterned by photolithography to form a hollow pattern corresponding to each unit circuit top electrode 11, and the hollow portion 62 of the photosensitive layer hollow pattern corresponds to the top electrode 11.
6) As shown in fig. 14, an alkali-resistant solderable metal layer 112 is plated on the top surface of the copper foil 1 at the hollow portion of the photosensitive layer, and the alkali-resistant solderable metal layer 112 may be a tin-plated layer, a silver-plated layer, or a gold-plated layer.
7) The photosensitive layer is removed as shown in fig. 15, and then, as shown in fig. 16, the copper foil 1 is subjected to alkaline etching, and the solderable metal layer 112 whose top surface is not plated with alkaline etching resistance is etched away with the exposed copper foil 1, thereby forming the top electrode 11.
8) As shown in fig. 17, the solder resist ink layer 7 is printed over the solder resist ink layer 3 and the main portion of the top electrode 11. The solder resist ink layer 7 opens the window 71, and the pad portion 111 of the top electrode 11 is exposed in the window 71 of the solder resist ink layer 7, to obtain another form of the lead frame of embodiment 1 of the present invention.
The packaging structure of the flip LED chip in embodiment 4 of the present invention is shown in fig. 12, and includes an LED chip 8A, a packaging adhesive layer 9, two electrodes, a solder resist ink layer 3, and a solder resist ink layer 7. The electrodes comprise a top electrode 11 and a bottom electrode 12, the top electrode 11 being arranged on the top surface of the solder resist ink layer 3. The solder resist ink layer 3 includes a bottom electrode hole 31 corresponding to the electrode, and the bottom electrode hole 31 is located directly below the top electrode 11. The bottom electrode 12 is disposed in the bottom electrode hole 31, and the top of the bottom electrode 12 is fixed to the bottom surface of the top electrode 11. The solder resist ink layer 7 is covered over the solder resist ink layer 3 and the top electrode 11. The solder resist ink layer 7 is opened with a window, and the pad portion 111 of the top electrode 11 is arranged in the window of the second solder resist ink. The two electrodes of the flip LED chip 8A are soldered to the pad portions 111 of the two top electrodes 11, respectively. The encapsulating glue layer 9 covers over the solder resist ink layer 7, the pad portion 111 of the top electrode 11 and the flip LED chip 8A.
Embodiment 5 of the present invention a lead frame for chip packaging is structured as shown in fig. 24, which is different from embodiment 1 in that a unit circuit includes a base island including an upper base island 13 and a lower base island 14, the upper base island 13 is disposed on the top surface of a solder resist ink layer 3, and the height of the upper base island 13 is the same as that of a top electrode 11. The solder resist ink layer 3 has a base island hole 32 corresponding to each unit circuit, and the lower base island 14 is disposed in the base island hole 32. The top of the lower base island 14 is fixed on the bottom surface of the upper base island 13. The carrier sheet 2 is releasably attached to the bottom surfaces of the lower base island 14 in addition to the solder resist ink layer 3 and the bottom electrode 12.
The upper base island 13 has a lateral dimension greater than that of the lower base island 14, and the upper base island 13 may entirely cover the base island hole 32. Also, this structural feature is mainly to prevent the alkali from corroding the lower base island 14 during the alkali etching process to protect the lower base island 14, and when the lower base island 14 is made of alkali-resistant metal, it is not necessary that the upper base island 13 entirely cover the base island holes 32.
The upper base island 13 includes a copper foil layer disposed on top of the solder resist ink layer 3 and a solderable metal layer 132 plated on top of the copper foil layer. The lower base island 14 includes a base metal layer 141 plated on the bottom surface of the upper base island 13 and a solderable metal layer 142 plated on the bottom surface of the base metal layer 141, which are filled in the base island hole 32 of the solder resist ink layer 3. When the alkali etching process is used, the base metal layer 141 is made of an alkali-resistant metal. The alkali-corrosion-resistant metal layer 141 may be a nickel-plated layer, a tin-plated layer, a silver-plated layer, or a composite plating layer of at least two of nickel, tin, and silver, and the solderable metal layer 142 may be a composite plating layer of at least two of a copper-plated layer, a nickel-plated layer, a tin-plated layer, a silver-plated layer, a gold-plated layer, or a copper-plated layer, a nickel-plated layer, a tin-plated layer, a silver-plated layer, and a gold-plated layer.
The solder resist ink layer 7 covers over the solder resist ink layer 3, the top electrode 11 and the upper base island 13. The solder resist ink layer 7 is opened with a plurality of windows 71, and the pad portions of the top electrodes 11 and the pad portions of the upper base islands 13 are respectively arranged in the windows 71 of the solder resist ink layer 7.
Embodiment 6 of the present invention is a method for manufacturing a lead frame in embodiment 5, and has many points in common with the method for manufacturing a lead frame in embodiment 2, for example, the following points are mainly different from the method for manufacturing a lead frame in embodiment 2:
1) as shown in fig. 18 and 19, in step 2 of example 2, in addition to the bottom electrode hole 31 being etched on the solder resist ink layer 3, the bottom surface of the copper foil 1 is plated with a metal layer in the bottom electrode hole 31 to form the bottom electrode 12 filled in the bottom electrode hole 31, the base island hole 32 corresponding to each unit circuit is etched on the solder resist ink layer 3, and the bottom surface of the copper foil 1 is plated with a metal layer in the base island hole 32 to form the lower base island 14 filled in the base island hole 32.
2) As shown in fig. 20, in step 3 of example 2, the carrier sheet 2 is simultaneously releasably adhered to the bottom surface of the lower base island 14.
3) As shown in fig. 21, in step 5 of example 2, the photosensitive layer 6 is patterned by photolithography to form hollow patterns corresponding to the top electrode 11 and the upper base island 13, and the remaining solid portions 61 of the photosensitive layer hollow patterns correspond to the shapes of the top electrode 11 and the upper base island 13, respectively.
4) As shown in fig. 22, in step 6 of example 2, the copper foil 1 is subjected to acid etching, and the copper foil 1 with the hollow pattern exposed is etched away to form a main portion of the upper base island 13 in addition to a main portion of the top electrode 11.
5) As shown in fig. 23, the photosensitive layer 6 is removed, and in step 7 of embodiment 2, the pad portions of the top electrode 11 and the upper base island 13 are simultaneously plated with the solderable metal layers 112 and 132.
6) As shown in fig. 24, in step 7 of example 2, the solder resist ink layer 7 is printed over the solder resist ink layer 3, the top electrode 11 main portion and the upper base island 13 main portion. The solder resist ink layer 7 is provided with a plurality of windows 71, and the pad portion of the top electrode 11 and the pad portion of the upper base island 13 are respectively exposed in the windows 71 of the solder resist ink layer 7, so as to obtain the lead frame of embodiment 5 of the present invention.
Inventive example 7 is still another method for manufacturing a lead frame of example 5, wherein alkaline etching is used, and compared with the acid etching method of example 6, the steps 1 and 2 are the same, but the metal layer plated on the lower base island 14 is an alkali corrosion resistant metal layer. The main difference is after step 3:
1) unlike the step 3 of the embodiment 6, as shown in fig. 25, the photosensitive layer 6 is patterned by photolithography to form a hollow pattern corresponding to the top electrode 11, and the hollow portion 62 of the photosensitive layer hollow pattern corresponds to the top electrode 11 and the upper base island 13.
2) As shown in fig. 26, the top surface of the copper foil 1 is plated with the alkali-resistant solderable metal layers 112 and 132 in the hollowed-out portion 62 of the photosensitive layer, and the alkali-resistant solderable metal layers 112 and 132 may be a tin-plated layer, a silver-plated layer, or a gold-plated layer.
3) As shown in fig. 27, the photosensitive layer 6 is removed, the copper foil 1 is subjected to alkaline etching, the solderable metal layers 112 and 132, the top surfaces of which are not plated with alkaline etching resistance, are etched away, and the exposed copper foil 1 is etched away to form the top electrode 11 and the upper base island 13.
4) As shown in fig. 28, the solder resist ink layer 7 is printed over the solder resist ink layer 3, the body of the top electrode 11 and the body of the upper base island 13. The solder resist ink layer 7 is opened with a plurality of windows 71, and the pad portion of the top electrode 11 and the pad portion of the upper base island 13 are respectively exposed in the windows 71 of the second solder resist ink, so as to obtain another form of the lead frame of embodiment 5 of the present invention.
A packaging structure of a normal chip in embodiment 8 of the present invention is shown in fig. 29, and includes a normal chip 8B, a packaging adhesive layer 9, a base island, a plurality of electrodes, a solder resist ink layer 3, and a solder resist ink layer 7. A plurality of electrodes are arranged at the periphery of the base island. The base islands include an upper base island 13 and a lower base island 14, and the electrodes include a top electrode 11 and a bottom electrode 12. The upper base island 13 and the top electrode 11 are arranged on the top surface of the solder resist ink layer 3. The solder resist ink layer 3 includes a base electrode hole 31 having a base island hole 32 corresponding to the electrode. The base island hole 32 is located right below the upper base island 13, and the lower base island 14 is arranged in the base island hole 32; the top of the lower base island 14 is fixed on the bottom surface of the upper base island 13. The bottom electrode hole 31 is located directly below the top electrode 11. The bottom electrode 12 is disposed in the bottom electrode hole 31, and the top of the bottom electrode 12 is fixed to the bottom surface of the top electrode 11. The solder resist ink layer 7 covers over the solder resist ink layer 3, the upper base island 13 and the top electrode 11. The solder resist ink layer 7 is opened with a plurality of windows, and the pad of the upper base island 13 and the pad of the top electrode 11 are respectively arranged in the windows of the solder resist ink layer 7. The bottom surface of the front chip 8B is soldered to the pad of the upper base island 13, and the plurality of electrodes of the front chip 8B are electrically connected to the pads of the corresponding top electrodes 11 by gold wires 8C, respectively. The encapsulation glue layer 9 covers the solder resist ink layer 7, the top electrode 11 pad and the flip chip 8B.
In the preparation method of the lead frame in the embodiment of the invention, the electrophoretic resin substrate is replaced by the solder resist ink layer, the thickness of the printed solder resist ink layer is easy to control, the copper foil does not need to be etched for filling the electrophoretic resin substrate, the solder resist ink layer adopts the photosensitive ink layer, the bottom electrode hole and the base island hole are formed by photoetching on the photosensitive ink layer without additionally covering a photosensitive film, and the plating cylinder of the electrophoretic process does not need to be maintained, so that the whole process is simple and the cost is lower.
Claims (13)
1. A lead frame for chip packaging comprises a bearing sheet and a plurality of unit circuits arranged in a matrix, wherein each unit circuit comprises a plurality of electrodes, and each electrode comprises a top electrode and a bottom electrode; the solder mask is characterized by comprising a first solder mask ink layer, wherein a top electrode is arranged on the top surface of the first solder mask ink layer; corresponding to each unit circuit, the first solder resist ink layer comprises a bottom electrode hole corresponding to the electrode, the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the bearing sheet is detachably adhered to the first solder resist ink layer and the bottom surface of the bottom electrode.
2. The lead frame according to claim 1, wherein the cell circuit includes a base island including an upper base island and a lower base island, the upper base island being disposed on a top surface of the first solder resist ink layer; corresponding to each unit circuit, the first solder resist ink layer comprises a base island hole, and the lower base island is arranged in the base island hole; the top of the lower base island is fixed on the bottom surface of the upper base island; the bearing sheet is detachably adhered to the bottom surface of the lower base island.
3. The lead frame of claim 1, wherein the top electrode has a lateral dimension greater than a lateral dimension of the bottom electrode, the top electrode completely covering the bottom electrode hole; the transverse size of the upper base island is larger than that of the lower base island, and the upper base island completely covers the base island hole; the height of the upper base island is the same as the height of the top electrode.
4. The lead frame of claim 1, wherein the top electrode comprises a copper foil layer disposed on a top surface of the first solder resist ink layer and a solderable metal layer plated on a top surface of the copper foil layer; the bottom electrode comprises a bottom electrode hole filled in the first solder resist ink layer, an alkali corrosion resistant metal layer electroplated on the bottom surface of the top electrode and a weldable metal layer electroplated on the bottom surface of the alkali corrosion resistant metal layer.
5. The lead frame of claim 2, wherein the upper base island includes a copper foil layer disposed on top of the first solder resist ink layer and a solderable metal layer plated on top of the copper foil layer; the lower base island comprises an alkali-resistant metal layer which is filled in the base island holes of the first solder-resistant ink layer and is plated on the bottom surface of the upper base island.
6. The lead frame according to claim 4 or 5, wherein the alkali-corrosion-resistant metal layer is a nickel-plated layer, a tin-plated layer, a silver-plated layer, or a composite plated layer of at least two of nickel, tin, and silver, and the solderable metal layer is a copper-plated layer, a nickel-plated layer, a tin-plated layer, a silver-plated layer, a gold-plated layer, or a composite plated layer of at least two of a copper-plated layer, a nickel-plated layer, a tin-plated layer, a silver-plated layer, and a gold-plated layer.
7. The lead frame of claim 1, comprising a second solder resist ink layer overlying the first solder resist ink layer and the top electrode; the second solder resist ink layer includes a window, and the pad of the top electrode is disposed in the window of the second solder resist ink layer.
8. A method of making the lead frame of claim 1, comprising the steps of:
801) pasting a bearing film on the top surface of the copper foil, and printing a first solder resist ink layer on the bottom surface of the copper foil;
802) photoetching a bottom electrode hole on the first solder mask ink layer, plating a metal layer on the bottom surface of the copper foil in the bottom electrode hole, and forming a bottom electrode filled in the bottom electrode hole;
803) the bearing sheet is detachably adhered to the first solder resist ink layer and the bottom surface of the bottom electrode;
804) stripping the carrier film on the top surface of the copper foil, and covering a photosensitive layer on the top surface of the copper foil;
805) the photosensitive layer is subjected to photoetching to manufacture a hollow pattern corresponding to the top electrode, the copper foil is etched, and the top electrode is formed above the first solder resist ink layer.
9. The method of claim 8, comprising the steps of:
901) the unit circuit comprises a base island, wherein the base island comprises an upper base island and a lower base island; in step 802, a base island hole corresponding to each unit circuit is photo-etched on the first solder resist ink layer, and a metal layer is plated on the bottom surface of the copper foil in the base island hole to form a lower base island filled in the base island hole;
902) in step 803, the carrier sheet is simultaneously releasably adhered to the bottom surface of the lower base island;
903) in step 805, the pattern formed by photolithography of the photosensitive layer includes a pattern corresponding to the upper base island, and when the copper foil is etched, the upper base island is simultaneously formed on the first solder resist ink layer.
10. The method of claim 6, comprising the steps of:
1001) in step 805, the physical part of the photo-sensitive layer hollow pattern corresponds to the shape of the top electrode;
1002) performing acid etching on the copper foil, and etching the copper foil exposed out of the hollow pattern;
1003) and removing the photosensitive layer, and plating a weldable metal layer on the copper foil remained after etching to form the top electrode.
11. The method of claim 8, comprising the steps of:
1101) in step 805, the hollow portion of the hollow pattern of the photosensitive layer corresponds to the shape of the top electrode;
1102) electroplating an alkali-corrosion-resistant weldable metal layer on the top surface of the copper foil at the hollow part of the photosensitive layer;
1103) and removing the photosensitive layer, carrying out alkaline etching on the copper foil, etching the weldable metal layer which is not plated with the alkaline etching resistance and the exposed copper foil to form the top electrode.
12. The method of claim 8, wherein after step 805 is completed, a second solder resist ink layer is printed over the first solder resist ink layer and the top electrode; the second solder resist ink layer includes a window, and the pad of the top electrode is disposed in the window of the second solder resist ink layer.
13. A chip packaging structure comprises a chip, a packaging adhesive layer and a plurality of electrodes, and is characterized by comprising a first solder resist ink layer, wherein the electrodes comprise a top electrode and a bottom electrode, and the top electrode is arranged on the top surface of the first solder resist ink layer; the first solder resist ink layer comprises a bottom electrode hole corresponding to the electrode, and the bottom electrode hole is positioned right below the top electrode; the bottom electrode is arranged in the bottom electrode hole, and the top of the bottom electrode is fixed on the bottom surface of the top electrode; the packaging adhesive layer covers the first solder resist ink layer and the top electrode, the chip is packaged in the packaging adhesive layer, and the plurality of electrodes of the chip are electrically connected with the plurality of top electrodes respectively.
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| CN202011273348.XA CN112366197A (en) | 2020-11-13 | 2020-11-13 | Lead frame for chip packaging, preparation method and chip packaging structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113629033A (en) * | 2021-08-11 | 2021-11-09 | 深圳市鼎华芯泰科技有限公司 | Lead frame for chip packaging, preparation method and chip packaging structure |
| CN114883292A (en) * | 2022-05-05 | 2022-08-09 | 深圳市鼎华芯泰科技有限公司 | IC carrier plate for chip packaging, preparation method thereof and chip packaging structure |
| CN115340784A (en) * | 2022-08-15 | 2022-11-15 | 广州华星光电半导体显示技术有限公司 | Solder resist ink with reflection performance, circuit board and display device |
-
2020
- 2020-11-13 CN CN202011273348.XA patent/CN112366197A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113629033A (en) * | 2021-08-11 | 2021-11-09 | 深圳市鼎华芯泰科技有限公司 | Lead frame for chip packaging, preparation method and chip packaging structure |
| CN114883292A (en) * | 2022-05-05 | 2022-08-09 | 深圳市鼎华芯泰科技有限公司 | IC carrier plate for chip packaging, preparation method thereof and chip packaging structure |
| CN115340784A (en) * | 2022-08-15 | 2022-11-15 | 广州华星光电半导体显示技术有限公司 | Solder resist ink with reflection performance, circuit board and display device |
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