CN102842560A - Wafer level chip scale package (WLCSP) multiple chip stackable packaging piece and packaging method thereof - Google Patents
Wafer level chip scale package (WLCSP) multiple chip stackable packaging piece and packaging method thereof Download PDFInfo
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- CN102842560A CN102842560A CN2012103065738A CN201210306573A CN102842560A CN 102842560 A CN102842560 A CN 102842560A CN 2012103065738 A CN2012103065738 A CN 2012103065738A CN 201210306573 A CN201210306573 A CN 201210306573A CN 102842560 A CN102842560 A CN 102842560A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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Abstract
The invention relates to a wafer level chip scale package (WLCSP) multiple chip stackable packaging piece and a packaging method thereof and belongs to the technical field of integrated circuit (IC) packaging. A plastic package body surrounds pins inside a frame, an upper layer IC chip, a lower layer IC chip, dice bonding glue, a metal protruded point, a tin layer, solder and a bonding wire to form circuit integrity. The plastic package body which plays the roles of supporting and protecting the upper layer IC chip, the lower layer IC chip and the bonding wire surrounds the pins inside the frame, the tin layer, the solder, the metal protruded point and the upper layer IC chip to form the circuit integrity. The upper layer IC chip, the lower layer IC chip, the bonding wire, the metal protruded point, the solder, the tin layer and the substrate form power and signal paths of a circuit. By adopting the metallic coating protruded point different from the past and the solder to weld every protruded point of the chip with frame pins, in the process of bonding, routing is not needed, and therefore breakover and mutual connection between the chip and the pins can be achieved directly. Thus, the WLCSP multiple chip stackable packaging piece and the packaging method thereof have the advantages of being low in cost and high in efficiency.
Description
Technical field
The present invention relates to a kind of WLCSP multi-chip stacking packaging part and method for packing thereof, belong to integrated circuit encapsulation technology field.
Background technology
The fast development of microelectric technique; The increase of integrated circuit complexity; The most function of an electronic system all possibly be integrated in (being SOC(system on a chip)) in the single-chip, and this just correspondingly requires microelectronics Packaging to have higher performance, more lead-in wire, closeer intraconnections, littler size or bigger chip chamber, bigger heat dissipation function, better electrical property, higher reliability, lower single lead-in wire cost etc.Chip package process is changed to wafer level packaging by Chip Packaging one by one, and wafer chip level chip encapsulation technology---WLCSP has just in time satisfied these requirements, has formed noticeable WLCSP technology.
Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging; Be called for short WLCSP), promptly the wafer stage chip packaged type is different from (the envelope survey again of cutting earlier of traditional Chip Packaging mode; And increase the volume of former chip 20% after the encapsulation at least); This kind state-of-the-art technology is on the full wafer wafer, to carry out packaging and testing earlier, just cut into IC particle one by one then, so volume after being encapsulated promptly is equal to the life size of the naked crystalline substance of IC.The packaged type of WLCSP, shorten product sizes significantly not only, and meet the high density demand of running gear for the body space; In the performance of usefulness, more promoted the speed and stability of transfer of data on the other hand.In traditional WLCSP technology, adopt sputter, photoetching, electroplating technology or silk screen printing on wafer, to carry out the mint-mark of circuit.Following flow process is the operating procedure of the wafer of accomplishing preceding road technology being carried out the WLCSP encapsulation:
(1) separator flow process (Isolation Layer)
(2) contact hole flow process (Contact Hole)
(3) pad lower metal layer flow process (UBM Layer)
(4) for electroplating the photoetching flow process (Photolithography for Plating) of preparing
(5) electroplate flow process (Plating)
(6) flow process (Resist Romoval) is removed on the barrier layer
Tradition WLCSP complex manufacturing process, high to the accuracy requirement of plating and photoetching, and cost is higher.
Summary of the invention
The present invention be directed to above-mentioned existing WLCSP defective workmanship, propose a kind of WLCSP multi-chip stacking packaging part and method for packing thereof, adopt the plating salient point of chemical plating metal salient point, sputter, photoetching, plating or silk-screen printing technique different from the past; Simultaneously; Utilize scolder with each salient point of chip and the welding of framework pin, during pressure welding, without routing; Directly accomplished conducting, interconnection between chip and pin, this multi-chip stacking packaging part has low cost, high-efficiency characteristics.
The technical scheme that the present invention adopts: a kind of WLCSP multi-chip stacking packaging part comprises bonding wire 8, the plastic-sealed body 9 of 1 of tin layer 2 on frame inner pin 1, the frame inner pin, scolder 3, metal salient point 4, upper strata IC chip 5, bonding die glue or glue film 6, the IC of lower floor chip 7, the IC of lower floor chip 7 and frame inner pin; It is whole that plastic-sealed body 9 has surrounded frame inner pin 1, upper strata IC chip 5, the IC of lower floor chip 7, bonding die glue 6, metal salient point 4, tin layer 2, scolder 3, bonding wire 8 has constituted circuit; Plastic-sealed body 9 that upper strata IC chip 5, the IC of lower floor chip 7, bonding wire 8 have been played support and protective effect has surrounded the integral body that frame inner pin 1, tin layer 2, scolder 3, metal salient point 4, upper strata IC chip 5 have constituted circuit, and upper strata IC chip 5, the IC of lower floor chip 7, bonding wire 8, metal salient point 4, scolder 3, tin layer 2 and frame inner pin 1 have constituted the power supply and the signalling channel of circuit.
Described bonding die glue 6 usefulness glue films replace; Bonding wire 8 is gold thread or copper cash.
A kind of method for packing of WLCSP multi-chip stacking packaging part, can carry out according to following steps:
The first step, wafer attenuate;
The thickness of wafer attenuate is 50 μ m～200 μ m, roughness Ra 0.10mm～0.30mm;
Second step, plating salient point;
Chip nip metal A u or Cu surface plating 2～50um metal salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The above wafer of 150 μ m adopts common scribing process; The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer of one deck 2～50um on frame inner pin 1;
The 5th goes on foot, goes up core
During last core, the IC of lower floor chip 7 turns around, adopts the technology of Flip-Chip, utilizes scolder that each salient point of chip and framework pin are welded; Upper strata IC chip 5 adopts bonding die glue 6 and lower floor's chip 7 to bond together;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together gold thread on IC chip 5 nips and frame inner pin 1 through melting tin;
The 7th step, pressure welding;
Be connected pressure welding between upper strata chip 7 and the frame inner pin with bonding wire 8;
The 8th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 9th step, tinization.
Described framework adopts the NiPdAu framework then need not do the tin processing.
Beneficial effect of the present invention:
(1) adopt the plating salient point, chemical plating metal salient point, sputter, photoetching, plating or silk-screen printing technique different from the past have low cost, high-efficiency characteristics.
(2) technology of employing Flip-Chip does not use the DAF film bonding, but adopts scolder with each salient point of chip and the welding of framework pin, during pressure welding, without routing, in last core, has just accomplished conducting, interconnection between chip and pin.
Description of drawings
Fig. 1 is a structural representation of the present invention;
Among the figure: tin layer, 3-scolder, 4-metal salient point, 5-IC chip, 6-bonding die glue, 7-IC chip, 8-bonding wire, 9-plastic-sealed body on 1-frame inner pin, the 2-frame inner pin.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further specified, understand to make things convenient for the technical staff.
As shown in Figure 1: a kind of WLCSP multi-chip stacking packaging part comprises bonding wire 8, the plastic-sealed body 9 of 1 of tin layer 2 on frame inner pin 1, the frame inner pin, scolder 3, metal salient point 4, upper strata IC chip 5, bonding die glue or glue film 6, the IC of lower floor chip 7, the IC of lower floor chip 7 and frame inner pin; It is whole that plastic-sealed body 9 has surrounded frame inner pin 1, upper strata IC chip 5, the IC of lower floor chip 7, bonding die glue 6, metal salient point 4, tin layer 2, scolder 3, bonding wire 8 has constituted circuit; Plastic-sealed body 9 that upper strata IC chip 5, the IC of lower floor chip 7, bonding wire 8 have been played support and protective effect has surrounded the integral body that frame inner pin 1, tin layer 2, scolder 3, metal salient point 4, upper strata IC chip 5 have constituted circuit, and upper strata IC chip 5, the IC of lower floor chip 7, bonding wire 8, metal salient point 4, scolder 3, tin layer 2 and frame inner pin 1 have constituted the power supply and the signalling channel of circuit.
Described bonding die glue 6 usefulness glue films replace; Bonding wire 8 is gold thread or copper cash.
Embodiment 1
A kind of method for packing of WLCSP multi-chip stacking packaging part, can carry out according to following steps:
The first step, wafer attenuate;
The thickness of wafer attenuate is 50 μ m, roughness Ra 0.10mm;
Second step, plating salient point;
Chip nip metal A u surface plating 2um metal salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer of one deck 2um on frame inner pin 1;
The 5th goes on foot, goes up core
During last core, the IC of lower floor chip 7 turns around, adopts the technology of Flip-Chip, utilizes scolder that each salient point of chip and framework pin are welded; Upper strata IC chip 5 adopts bonding die glue 6 and lower floor's chip 7 to bond together;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together gold thread on IC chip 5 nips and frame inner pin 1 through melting tin;
The 7th step, pressure welding;
Be connected pressure welding between upper strata chip 7 and the frame inner pin with bonding wire 8;
The 8th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 9th step, tinization.
A kind of method for packing of WLCSP multi-chip stacking packaging part, can carry out according to following steps:
The first step, wafer attenuate;
The thickness of wafer attenuate is 130 μ m, roughness Ra 0.20mm;
Second step, plating salient point;
Chip nip metal Cu surface plating 25um metal salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer of one deck 25um on frame inner pin 1;
The 5th goes on foot, goes up core
During last core, the IC of lower floor chip 7 turns around, adopts the technology of Flip-Chip, utilizes scolder that each salient point of chip and framework pin are welded; Upper strata IC chip 5 adopts bonding die glue 6 and lower floor's chip 7 to bond together;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together gold thread on IC chip 5 nips and frame inner pin 1 through melting tin;
The 7th step, pressure welding;
Be connected pressure welding between upper strata chip 7 and the frame inner pin with bonding wire 8;
The 8th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 9th step, tinization.
Embodiment 3
A kind of method for packing of WLCSP multi-chip stacking packaging part, can carry out according to following steps:
The first step, wafer attenuate;
The thickness of wafer attenuate is 200 μ m, roughness Ra 0.30mm;
Second step, plating salient point;
Chip nip metal A u or Cu surface plating 50um metal salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The above wafer of 150 μ m adopts common scribing process;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer of one deck 50um on frame inner pin 1;
The 5th goes on foot, goes up core
During last core, the IC of lower floor chip 7 turns around, adopts the technology of Flip-Chip, utilizes scolder that each salient point of chip and framework pin are welded; Upper strata IC chip 5 adopts bonding die glue 6 and lower floor's chip 7 to bond together;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together gold thread on IC chip 5 nips and frame inner pin 1 through melting tin;
The 7th step, pressure welding;
Be connected pressure welding between upper strata chip 7 and the frame inner pin with bonding wire 8;
The 8th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 9th step, tinization.
Embodiment 4
A kind of method for packing of WLCSP multi-chip stacking packaging part is coated with Au or Cu metal salient point 4 and tin layer 2, if then it goes without doing the tin processing of NiPdAu framework.
Claims (5)
1. a WLCSP multi-chip stacking packaging part is characterized in that: comprise bonding wire, plastic-sealed body between tin layer on frame inner pin, the frame inner pin, scolder, metal salient point, upper strata IC chip, bonding die glue, the IC of lower floor chip, the IC of lower floor chip and frame inner pin; Be coated with the tin layer with the metal salient point welding region on the frame inner pin; The nip plating metal on surface salient point of IC chip; The tin layer adopts the mode of flip-chip to weld together with scolder on metal salient point and the frame inner pin; Plastic-sealed body that upper strata IC chip, the IC of lower floor chip, bonding wire have been played support and protective effect has surrounded the integral body that frame inner pin, tin layer, scolder, metal salient point, upper strata IC chip have constituted circuit, and upper strata IC chip, the IC of lower floor chip, bonding wire, metal salient point, scolder, tin layer and frame inner pin have constituted the power supply and the signalling channel of circuit.
2. a kind of WLCSP multi-chip stacking packaging part according to claim 1, it is characterized in that: bonding die glue replaces with glue film.
3. a kind of WLCSP multi-chip stacking packaging part according to claim 1, it is characterized in that: bonding wire is gold thread or copper cash.
4. the method for packing of a WLCSP multi-chip stacking packaging part, it is characterized in that: method for packing carries out according to following steps:
The first step, wafer attenuate;
The thickness of wafer attenuate is 50 μ m～200 μ m, roughness Ra 0.10mm～0.30mm;
Second step, plating salient point;
Chip nip metal A u or Cu surface plating 2～50um metal salient point on the full wafer wafer;
The 3rd step, scribing;
The above wafer of 150 μ m adopts common scribing process; The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer of one deck 2～50um on frame inner pin 1;
The 5th goes on foot, goes up core
During last core, lower floor's IC chip turns around, adopts the technology of Flip-Chip, utilizes scolder that each salient point of chip and framework pin are welded; Upper strata IC chip adopts bonding die glue and lower floor's die bonding together;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together bonding wire and frame inner pin on the IC chip nip through melting tin;
The 7th step, pressure welding;
Be connected pressure welding between upper strata chip and the frame inner pin with bonding wire;
The 8th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 9th step, tinization.
5. the method for packing of a kind of WLCSP multi-chip stacking packaging part according to claim 4 is characterized in that: described framework adopts the NiPdAu framework then need not do the tin processing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012103065738A CN102842560A (en) | 2012-08-21 | 2012-08-21 | Wafer level chip scale package (WLCSP) multiple chip stackable packaging piece and packaging method thereof |
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| CN2012103065738A CN102842560A (en) | 2012-08-21 | 2012-08-21 | Wafer level chip scale package (WLCSP) multiple chip stackable packaging piece and packaging method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107240555A (en) * | 2017-05-31 | 2017-10-10 | 江苏长电科技股份有限公司 | A kind of manufacture method of flip-chip and the chip-stacked encapsulating structure of ball bonding |
| CN108878300A (en) * | 2017-05-12 | 2018-11-23 | 意法半导体公司 | Packaging part during molding with back-protective layer to prevent mold flashing from failing |
| CN109037185A (en) * | 2018-07-24 | 2018-12-18 | 天水华天科技股份有限公司 | A kind of lead frame and its ultrathin small shape flip-chip packaged part |
| CN110649054A (en) * | 2019-09-27 | 2020-01-03 | 华天科技（昆山）电子有限公司 | Wafer-level packaging method and packaging structure for improving stress of solder mask layer of CIS chip |
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| JP2004119801A (en) * | 2002-09-27 | 2004-04-15 | Alps Electric Co Ltd | Method for forming solder bump |
| CN102263070A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | Wafer level chip scale packaging (WLCSP) piece based on substrate packaging |
| CN102263078A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | WLCSP (Wafer Level Chip Scale Package) packaging component |
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2012
- 2012-08-21 CN CN2012103065738A patent/CN102842560A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004119801A (en) * | 2002-09-27 | 2004-04-15 | Alps Electric Co Ltd | Method for forming solder bump |
| CN102263070A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | Wafer level chip scale packaging (WLCSP) piece based on substrate packaging |
| CN102263078A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | WLCSP (Wafer Level Chip Scale Package) packaging component |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878300A (en) * | 2017-05-12 | 2018-11-23 | 意法半导体公司 | Packaging part during molding with back-protective layer to prevent mold flashing from failing |
| CN107240555A (en) * | 2017-05-31 | 2017-10-10 | 江苏长电科技股份有限公司 | A kind of manufacture method of flip-chip and the chip-stacked encapsulating structure of ball bonding |
| CN107240555B (en) * | 2017-05-31 | 2020-04-07 | 江苏长电科技股份有限公司 | Manufacturing method of packaging structure for stacking flip chip and ball bonding chip |
| CN109037185A (en) * | 2018-07-24 | 2018-12-18 | 天水华天科技股份有限公司 | A kind of lead frame and its ultrathin small shape flip-chip packaged part |
| CN110649054A (en) * | 2019-09-27 | 2020-01-03 | 华天科技（昆山）电子有限公司 | Wafer-level packaging method and packaging structure for improving stress of solder mask layer of CIS chip |
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Application publication date: 20121226 |