CN107564822A - A kind of method for packing of integrated chip and the integrated chip of system in package - Google Patents
A kind of method for packing of integrated chip and the integrated chip of system in package Download PDFInfo
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- CN107564822A CN107564822A CN201710750191.7A CN201710750191A CN107564822A CN 107564822 A CN107564822 A CN 107564822A CN 201710750191 A CN201710750191 A CN 201710750191A CN 107564822 A CN107564822 A CN 107564822A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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Abstract
The invention discloses a kind of method for packing of integrated chip and the integrated chip of system in package, the method for packing includes：There is provided a plastic-sealed body, embedding inside plastic-sealed body to have a chip, the device side of chip is exposed outside plastic-sealed body；First dielectric film is set on the first surface of plastic-sealed body and the device side of chip, and the bond pad locations on chip form corresponding through hole；Metal film is set on the first dielectric film, and photoresistance glued membrane is set on metal film；Wet etching metal film, formed and rerouted；The second dielectric film is set based on rerouting, and etches the second dielectric film, appears part and reroutes to form weight cloth weld pad, formed and reroute layer.Rewiring is formed by using the mode of wet etching metal film, the equipment consumables cost using electroplating technology can be reduced, simultaneously, it can also save and electroplate liquid waste material is handled and caused cost, in addition, the step of also reducing deposited seed layer, operating process is relatively simple, so as to reduce further production cost.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to the method for packing of a kind of integrated chip and system-level
The integrated chip of encapsulation.
Background technology
Wafer scale fan-out package is the embedded type encapsulation in the processing and manufacturing of wafer one-level, and a kind of for input/defeated
The high main advanced package technologies of big, the integrated flexibility of the quantity of exit port (Input/Output, I/O).And it can be one
Realize that vertically and horizontally multi-chip is integrated and does not have to substrate in part encapsulation, device package can be accumulated and accomplish very little.This
Sample, fan-out package is currently the one preferred technique of encapsulation manufacture of future generation, such as multi-chip, thickness ultrathin encapsulate and three dimension system
Level encapsulation etc..
Wafer scale fan-out package the chip entirety plastic packaging of test passes and reconstructs wafer using wafer scale flip-clip.
Then I/O pin interconnections are fanned out to the plastic packaging region of chip circumference using rewiring layer.Again through planting the techniques such as ball backflow, cutting
Form independent packaging.Relative to fan-in technique, fan-out package supports bigger layout area again, is especially suitable for pin
Numerous application scenario.
In the prior art, Publication No. CN105070671A Chinese patent literature discloses a kind of chip packaging method,
This method comprises the following steps：S1 a, there is provided carrier, adhesive layer is formed in the carrier surface；S2, in the bonding layer surface
First medium layer is formed, and forms in the first medium layer that some that corresponding first is electrically drawn with semiconductor chip is logical
Hole；S3, the semiconductor chip face down is attached to the first medium layer surface；S4, in the first medium layer table
Face forms the dielectric layer for covering the chip；S5, adhesive layer and the first medium layer is separated, to remove the carrier and bonding
Layer；S6, redistribution trace layer is formed to the semiconductor chip based on the first medium layer and the first through hole.Above-mentioned
In method, step S6 forms conductive pole specifically, fill metallic conductor in first through hole by the technique such as depositing, electroplating；
Photoetching offset plate figure is made on first medium layer, and based on photoetching offset plate figure in first medium layer surface deposition or sputtering seed layer；
Metallic circuit (conductive pole and metallic circuit can also together with formed) is formed based on Seed Layer plated metallic conductor；Remove photoresist
Figure.But the technological process that redistribution trace layer is formed in the chip packaging method is complex, and by based on seed
The mode that layer plated metallic conductor forms metallic circuit forms redistribution trace layer, and formation cost is higher, in addition, using galvanizer
Skill can also produce electroplate liquid waste material, it is necessary to carry out Ecological Disposal to caused electroplate liquid waste material, thus, it will generation environment is protected
Cost.
Therefore, how to simplify the operating process of wafer scale fan-out package process, reduce production cost and production
During the processing cost of caused waste material turn into urgent problem to be solved.
The content of the invention
Therefore, the technical problem to be solved in the present invention is the operating process for solving wafer scale fan-out package process
It is complex, the problem of processing cost of caused waste material is higher in production cost and production process.
Therefore, according in a first aspect, the embodiments of the invention provide a kind of method for packing of integrated chip, its feature exists
In comprising the following steps：There is provided a plastic-sealed body, embedding inside plastic-sealed body to have a chip, the device side of chip is exposed outside plastic-sealed body；
First dielectric film is set on the first surface of plastic-sealed body and the device side of chip, and the bond pad locations on chip are formed correspondingly
Through hole；Metal film is set on the first dielectric film, and photoresistance glued membrane is set on metal film；Wet etching metal film, formed
Reroute；The second dielectric film is set based on rerouting, and etches the second dielectric film, appears part and reroutes to form weight cloth weld pad,
Formed and reroute layer.
Alternatively, metal film is aluminium film or the aluminium alloy film containing a small amount of copper.
Alternatively, there is provided a plastic-sealed body, embedding inside plastic-sealed body to have a chip, the device side of chip is exposed in plastic-sealed body bag
Include：One substrate is provided, and adhered layer is set on substrate；Chip is pasted on adhered layer, the device side direction of chip is pasted
Layer；Plastic packaging material is set based on adhered layer, chip is sealed, forms plastic-sealed body；Adhered layer and plastic-sealed body are separated, makes the device of chip
Face is exposed to outside plastic-sealed body.
Alternatively, chip is one or more bare chips.
Alternatively, it is one layer or multilayer to reroute layer.
Alternatively, the first dielectric film and the second dielectric film are photosensitive insulative film.
Alternatively, the method for packing of integrated chip also includes：Soldered ball, soldered ball and weight cloth weld pad phase are set on weight cloth weld pad
Coupling.
The embodiment of the present invention additionally provides a kind of integrated chip of system in package, it is characterised in that including：Plastic-sealed body；
Chip, chip it is embedding with plastic-sealed body in, the device side of chip is exposed to outside plastic-sealed body；First dielectric film, is arranged at plastic-sealed body
In the device side of first surface and chip, and the bond pad locations of chip are provided with corresponding through hole；Reroute, be arranged on through hole
In, and extend on the first dielectric film；Second dielectric film, it is arranged on the first dielectric film, and manifests part and reroute to be formed
Weight cloth weld pad；Soldered ball, it is arranged on weight cloth weld pad, and is coupled with weight cloth weld pad.
Alternatively, the material of rewiring is metallic aluminium or the aluminium alloy containing a small amount of copper.
Alternatively, chip is one or more bare chips.
Technical scheme provided in an embodiment of the present invention, has the following advantages that：
The 1st, metal film is set on the first dielectric film, and photoresistance glued membrane is set on metal film；Wet etching metal film, shape
Into rewiring；The second dielectric film is set based on rerouting, and etches second dielectric film, appears part and reroutes to form weight cloth
Weld pad, formed and reroute layer.Rewiring is formed by using the mode of wet etching metal film, instead of electroplating wiring technique, because
And the consumables cost of the equipment of electroplating technology can be reduced, electroplate liquid waste material is handled and produced at the same time it can also save
Environmental protection cost, in addition, the step of method for packing of the integrated chip reduces deposited seed layer, operating process is more simple
It is single, so as to reduce further production cost.
2nd, using aluminium film or the aluminium alloy film for containing a small amount of copper as metal film, subsequent wet etching sheet metal is improved
Feasibility, at the same time it can also further save production cost.
3rd, the first dielectric film in the method for packing of the integrated chip uses photosensitive insulative film, can directly pass through exposure
The modes such as light, development, through hole corresponding to the bond pad locations formed on chip, formation process is simple, also, the laser boring that compares
Etc. the mode for forming through hole, it is relatively low to form cost.
Brief description of the drawings
, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical scheme of the prior art
The required accompanying drawing used is briefly described in embodiment or description of the prior art, it should be apparent that, in describing below
Accompanying drawing is some embodiments of the present invention, for those of ordinary skill in the art, before creative work is not paid
Put, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart of the method for packing of integrated chip disclosed in the present embodiment；
Fig. 2 is the structural representation of plastic-sealed body disclosed in the present embodiment；
Fig. 3 is the disclosed schematic diagram for setting the first dielectric film of the present embodiment；
Fig. 4 is the disclosed schematic diagram for setting metal film and photoresistance glued membrane of the present embodiment；
Fig. 5, which is that the present embodiment is disclosed, forms the schematic diagram rerouted；
Fig. 6 is the planar structure schematic diagram of the integrated chip of system in package disclosed in the present embodiment；
Fig. 7 is the disclosed flow chart for forming plastic-sealed body of the present embodiment；
Fig. 8 is the disclosed schematic diagram that adhered layer is set on substrate of the present embodiment；
Fig. 9 is the disclosed schematic diagram for forming plastic-sealed body of the present embodiment
Description of reference numerals：
1- plastic-sealed bodies；2- chips；The dielectric films of 3- first；4- metal films；5- photoresistance glued membranes；6- is rerouted；7- second insulate
Film；8- substrates；9- adhered layers；10- soldered balls.
Embodiment
Technical scheme is clearly and completely described below in conjunction with accompanying drawing, it is clear that described implementation
Example is part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, ordinary skill
The every other embodiment that personnel are obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
In the description of the invention, it is necessary to which explanation, term " first ", " second " are only used for describing purpose, and can not
It is interpreted as indicating or implying relative importance.
Embodiment 1
The embodiment of the invention discloses a kind of method for packing of integrated chip, Fig. 1 is refer to, Fig. 1 discloses for the present embodiment
Integrated chip method for packing flow chart, comprise the following steps：
Step S10：One plastic-sealed body is provided.In the present embodiment, Fig. 2 is refer to, Fig. 2 is plastic-sealed body disclosed in the present embodiment
Structural representation, the inside of the plastic-sealed body 1 is embedding chip 2, and the device side of chip 2 is exposed outside plastic-sealed body 1, the device of chip 2
Part face, refers to, the plane where weld pad on chip 2.In the present embodiment, chip 2 is one or more bare chips, specifically
Ground, the quantity and function of the bare chip determines by specific application scenarios, can be according to reality when chip 2 is multiple bare chips
The needs of border scene, multiple bare chips are connected by rerouting layer, multiple bare chips is coupled.
Step S20：The first dielectric film is set on the first surface of plastic-sealed body and the device side of chip.In the present embodiment
In, Fig. 3 is refer to, Fig. 3, which is that the present embodiment is disclosed, is setting the schematic diagram of the first dielectric film, the bond pad locations on chip 2
Through hole corresponding to formation.In the present embodiment, the first dielectric film 3 is photosensitive insulative film, and specifically, the first dielectric film 3 can be with
For photo-sensistive polyimide film or polyparaphenylene's benzo twoport oxazole film etc., in a particular embodiment, by being insulated to first
Film 3 is exposed and developed, so as to, the bond pad locations on chip 2 form corresponding through hole, and formation process is relatively simple, and
And the laser boring that compares etc. forms the mode of through hole, the cost of the formation scheme in the present embodiment is relatively low.
Step S30：Metal film is set on the first dielectric film, and photoresistance glued membrane is set on metal film.It refer to Fig. 4,
Fig. 4 is the disclosed schematic diagram for setting metal film and photoresistance glued membrane of the present embodiment, in the present embodiment, metal film 4 be aluminium film or
Person contains the aluminium alloy film of a small amount of copper, it is preferable that the thickness of the metal film 4 is 3-10um, and metal is set on the first dielectric film 3
Film 4, refers to, metal film 4 is arranged at the upper surface of the first dielectric film 3, and metal film 4 is filled in leading on the first dielectric film 3
Metal column is formed in hole, so as to make metal film 4 be coupled with chip 2, in a particular embodiment, the side of vacuum sputtering can be used
Formula forms metal film 4.In the present embodiment, photoresistance glued membrane 5, photoresistance glued membrane can be formed by the way of spraying or rotation apply
5 are arranged on metal film 4, for protecting the metal film 4 that need not be etched, so as to be formed and reroute 6.Due to metallic aluminium or
The aluminium alloy that person contains a small amount of copper is easier to be etched, and thus, step S4 feasibility is improved, although in addition, aluminium is led
It is electrically poor, but the electric property of rewiring 6 can be improved by adjusting thickness and the width of rewiring 6, so as to energy
It is enough to realize that ensureing while production cost is saved using metallic aluminium or the formation of the aluminium alloy containing a small amount of copper rewiring 6
The electric property of integrated chip 2 is unaffected.
Step S40：Wet etching metal film, formed and rerouted.Fig. 5 is refer to, Fig. 5, which is that the present embodiment is disclosed, forms weight
The schematic diagram of wiring, in the present embodiment, etching agent is a kind of mixed acid used by carrying out wet etching, and the mixed acid includes
Phosphoric acid, nitric acid, acetic acid and water, it is preferable that using phosphoric acid：Nitric acid：Acetic acid：The volume ratio of water is 73%：3%：3%：21%
Mixed acid as etching agent.In the present embodiment, can also be by the way of wet-cleaning, to the He of photoresistance glued membrane 5 of residual
The metal film 4 that should be etched is further to be removed.
Step S50：Based on rerouting, the second dielectric film is set.Fig. 6 is refer to, Fig. 6 is system-level disclosed in the present embodiment
The planar structure schematic diagram of the integrated chip of encapsulation, in the present embodiment, the second dielectric film 7 is etched, appear part and reroute 6 shapes
Cheng Chongbu weld pads, formed and reroute layer, in a particular embodiment, the second dielectric film 7 is used to fill the gap rerouted between 6,
And extend to the upper surface of rewiring 6.In the present embodiment, the second dielectric film 7 is photosensitive insulative film, and specifically, second is exhausted
Velum 7 can be photo-sensistive polyimide film or polyparaphenylene's benzo twoport oxazole film etc., in a particular embodiment, Ke Yitong
The setting photoresistance glued membrane on the second dielectric film 7 is crossed, and to the mode that photoresistance glued membrane is exposed, develops and etched, appears part
Rewiring 6 forms weight cloth weld pads, and specifically, specific set location and quantity of weight cloth weld pad etc. can answering according to reality
With scene it needs to be determined that.
In the present embodiment, multilayer can be formed by repeat step S2-S5 and rerouted according to the needs of actual scene
Layer is, it is necessary to special instruction, and when forming other rewiring layers in addition to first layer reroutes layer, the first dielectric film 3 is
It is arranged at and reroutes on layer, and through hole is to be formed at the correspondence position that last layer reroutes weight cloth weld pad in layer, specific real
Apply in example, can also be used the second dielectric film 7 as the first dielectric film 3 formed in next rewiring layer, it is thus possible to
Omit step S20.
Due to forming rewiring 6 using the mode of wet etching metal film 4, plating wiring technique is instead of, thus, it is possible to
The consumables cost of the equipment using electroplating technology is reduced, electroplate liquid waste material is handled and caused at the same time it can also save
Environmental protection cost, in addition, the step of method for packing of the integrated chip reduces deposited seed layer, operating process is more simple
It is single, so as to reduce further production cost.
In an alternate embodiment of the invention, Fig. 7 is refer to, Fig. 7 forms the flow chart of plastic-sealed body, step disclosed in the present embodiment
10 include：
Step S11：One substrate is provided, and adhered layer is set on substrate.Fig. 8 is refer to, Fig. 8 is disclosed in the present embodiment
The schematic diagram of adhered layer is set on substrate, and in the present embodiment, the material of substrate 8 can be metal, alloy, ceramics or silicon
Piece, adhered layer 9 are made up of jointing material, and the adhered layer 9 can be bonded on substrate 8, at the same time it can also adhering chip 2, are being had
In body embodiment, adhered layer 9 can be adhesive tape, it is of course also possible to glue made of by way of spin coating or spraying adhesive glue
Film, it is preferable that adhered layer 9 is layers of two-sided, and the layers of two-sided is preferably that 250 DEG C two-sided is limited at the temperature for losing viscosity
Glue.
Step S12：Chip is pasted on adhered layer.Fig. 8 is refer to, in the present embodiment, the device side direction of chip 2
Adhered layer 9, chip 2 are one or more bare chips, and in a particular embodiment, chip 2 can be the same bare chip of function phase, when
So, or the bare chip of difference in functionality, specifically, the quantity and function of bare chip can be according to practical application scenes
It needs to be determined that in a particular embodiment, chip 2 can select the bare chip by thinning back side, pass through it is thus possible to reduce this
The thickness of integrated chip 2 made of the method for packing of integrated chip 2.
Step S13：Plastic packaging material is set based on adhered layer, chip is sealed, forms plastic-sealed body.Fig. 9 is refer to, Fig. 9 is this
The disclosed schematic diagram for forming plastic-sealed body of embodiment, in a particular embodiment, can be by the way that the substrate 8 for having pasted chip 2 be put
It is placed in the mode being molded in plastic package die and forms plastic-sealed body 1.
Step S14：Separate adhered layer and plastic-sealed body.In the present embodiment, adhered layer 9 and plastic-sealed body 1 are separated, makes chip 2
Device side be exposed to outside plastic-sealed body 1, in a particular embodiment, can be torn by pyrolysis, mechanical tear or pyrolysis with machinery
The mode for splitting combined use separates adhered layer 9 and plastic-sealed body 1.
In an alternate embodiment of the invention, Fig. 1 is refer to, the method for packing of the integrated chip also includes：
Step S60：Soldered ball is set on weight cloth weld pad, and soldered ball is coupled with weight cloth weld pad.In the present embodiment, refer to
Fig. 6, the material of soldered ball 10 can be Sn, SnAg or (SAC) SnAgCu.In a particular embodiment, can be first in the heavy cloth of top layer
Prefluxing on the heavy cloth weld pad of line layer, and design soldered ball 10 is needed according to actual scene with silk-screen printing technique, then pass through
Reflow soldering process, soldered ball 10 is securely attached on weight cloth weld pad.
Embodiment 2
The embodiment of the invention discloses a kind of integrated chip of system in package, Fig. 6 is refer to, including：Plastic-sealed body 1；Core
Piece 2, chip 2 it is embedding with plastic-sealed body 1 in, the device side of chip 2 is exposed to outside plastic-sealed body 1；First dielectric film 3, is arranged at plastic packaging
On the first surface of body 1 and the device side of chip 2, and the bond pad locations of chip 2 are provided with corresponding through hole；6 are rerouted, if
Put in through-holes, and extend on the first dielectric film 3；Second dielectric film 7, it is arranged on the first dielectric film 3, and manifests part
Reroute 6 and form weight cloth weld pad；Soldered ball 10, it is arranged on weight cloth weld pad, and is coupled with weight cloth weld pad.
In the present embodiment, chip 2 is one or more bare chips, and specifically, the quantity and function of the bare chip are by reality
The application scenarios on border determine, when chip 2 is multiple bare chips, can be connected according to the needs of actual scene by rerouting layer
Multiple bare chips are connect, multiple bare chips is coupled.
In the present embodiment, the first dielectric film 3 is photosensitive insulative film, and specifically, the first dielectric film 3 can be light sensitivity
Polyimide film or polyparaphenylene's benzo twoport oxazole etc..In a particular embodiment, by being exposed to the first dielectric film 3
And development, so as to, the bond pad locations on chip 2 form corresponding through hole, and formation process is relatively simple, also, compared to relatively sharp
Light punching etc. forms the mode of through hole, and the cost of the formation scheme in the present embodiment is relatively low.
In the present embodiment, the material for rerouting 6 is metallic aluminium or the aluminium alloy containing a small amount of copper, it is preferable that weight cloth
The thickness of line 6 is 3-10um, in a particular embodiment, can improve weight cloth by adjusting thickness and the width of rewiring 6
The electric property of line 6, the poor deficiency of the electric conductivity of aluminium is made up, thus, it is possible to use metallic aluminium or containing a small amount of copper
While aluminium alloy forms the saving production cost of rewiring 6, ensure that the electric property of the integrated chip 2 is unaffected.
In the present embodiment, by setting the second dielectric film 7 on the first dielectric film 3, and manifest part and reroute 6 shapes
Cheng Chongbu weld pads, so as to form rewiring layer, in a particular embodiment, rerouting layer can be according to the needs of practical application scene
One layer or multilayer are designed as, it is necessary to special instruction, when it be multilayer to reroute layer, in addition to first layer rewiring layer
Other reroute the first dielectric film 3 of layers, are arranged at and reroute on layer, and the position of cloth weld pad again in last layer reroutes layer
Install and be equipped with corresponding through hole, in a particular embodiment, can be direct if the second dielectric film 7 is photosensitive insulative film
Using the second dielectric film 7 as the first dielectric film 3 formed in next rewiring layer.
Technical scheme provided in an embodiment of the present invention, has the following advantages that：
The 1st, metal film is set on the first dielectric film, and photoresistance glued membrane is set on metal film；Wet etching metal film, shape
Into rewiring；The second dielectric film is set based on rerouting, and etches second dielectric film, appears part and reroutes to form weight cloth
Weld pad, formed and reroute layer.Rewiring is formed by using the mode of wet etching metal film, instead of electroplating wiring technique, because
And the consumables cost of the equipment of electroplating technology can be reduced, electroplate liquid waste material is handled and produced at the same time it can also save
Environmental protection cost, in addition, the step of method for packing of the integrated chip reduces deposited seed layer, operating process is more simple
It is single, so as to reduce further production cost.
2nd, using aluminium film or the aluminium alloy film for containing a small amount of copper as metal film, subsequent wet etching sheet metal is improved
Feasibility, at the same time it can also further save production cost.
3rd, the first dielectric film in the method for packing of the integrated chip uses photosensitive insulative film, can directly pass through exposure
The modes such as light, development, through hole corresponding to the bond pad locations formed on chip, formation process is simple, also, the laser boring that compares
Etc. the mode for forming through hole, it is relatively low to form cost.
Obviously, above-described embodiment is only intended to clearly illustrate example, and is not the restriction to embodiment.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of change or
Change.There is no necessity and possibility to exhaust all the enbodiments.And the obvious change thus extended out or
Among changing still in the protection domain of the invention.
Claims (10)
1. a kind of method for packing of integrated chip, it is characterised in that comprise the following steps：
One plastic-sealed body (1) is provided, the plastic-sealed body (1) it is internal it is embedding have a chip (2), the device side of the chip (2) it is exposed
The plastic-sealed body (1) is outside；
The first dielectric film (3) is set on the first surface of the plastic-sealed body (1) and the device side of the chip (2), and
Bond pad locations on the chip (2) form corresponding through hole；
Metal film (4) is set on first dielectric film (3), and photoresistance glued membrane (5) is set on the metal film (4)；
Metal film described in wet etching (4), formed and reroute (6)；
Second dielectric film (7) is set based on the rewiring (6), and etches second dielectric film (7), it is described heavy to appear part
Connect up (6) and form weight cloth weld pad, formed and reroute layer.
2. the method for packing of integrated chip according to claim 1, it is characterised in that the metal film (4) be aluminium film or
Person contains the aluminium alloy film of a small amount of copper.
3. the method for packing of integrated chip according to claim 1, it is characterised in that one plastic-sealed body of the offer (1), institute
State plastic-sealed body (1) it is internal it is embedding have chip (2), the device side of the chip (2) is exposed to be included outside in the plastic-sealed body (1)：
One substrate (8) is provided, and adhered layer (9) is set on the substrate (8)；
The chip (2) is pasted on the adhered layer (9), the device side of the chip (2) is towards the adhered layer
(9)；
Plastic packaging material is set based on the adhered layer (9), the chip (2) is sealed, forms the plastic-sealed body (1)；
The adhered layer (9) and the plastic-sealed body (1) are separated, the device side of the chip (2) is exposed to the plastic packaging
Body (9) is outside.
4. the method for packing of the integrated chip according to claim any one of 1-3, it is characterised in that the chip (2) is
One or more bare chips.
5. the method for packing of the integrated chip according to claim any one of 1-4, it is characterised in that it is described rewiring layer be
One layer or multilayer.
6. the method for packing of integrated chip according to claim 1, it is characterised in that first dielectric film (3) and
Two dielectric films (7) are photosensitive insulative film.
7. the method for packing of the integrated chip according to claim any one of 1-6, it is characterised in that also include：
Soldered ball (10) is set on the heavy cloth weld pad, and the soldered ball (10) is coupled with the heavy cloth weld pad.
A kind of 8. integrated chip of system in package, it is characterised in that including：
Plastic-sealed body (1)；
Chip (2), the chip (2) are embedded in the plastic-sealed body (1), and the device side of the chip (2) is exposed to the modeling
Seal body (1) outside；
First dielectric film (3), it is arranged on the first surface of the plastic-sealed body (1) and the device side of the chip (2), and
The bond pad locations of the chip (2) are provided with corresponding through hole；
Reroute (6), be arranged in the through hole, and extend on first dielectric film (3)；
Second dielectric film (7), it is arranged on first dielectric film (3), and manifests described reroute (6) in part and form weight cloth
Weld pad；
Soldered ball (10), it is arranged on the heavy cloth weld pad, and is coupled with the heavy cloth weld pad.
9. the integrated chip of system in package according to claim 8, it is characterised in that the material for rerouting (6)
Aluminium alloy for metallic aluminium or containing a small amount of copper.
10. the integrated chip of system in package according to claim 8, it is characterised in that the chip (2) be one or
Multiple bare chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710750191.7A CN107564822A (en) | 2017-08-28 | 2017-08-28 | A kind of method for packing of integrated chip and the integrated chip of system in package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710750191.7A CN107564822A (en) | 2017-08-28 | 2017-08-28 | A kind of method for packing of integrated chip and the integrated chip of system in package |
Publications (1)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109659278A (en) * | 2018-12-26 | 2019-04-19 | 合肥矽迈微电子科技有限公司 | Multichip stacking encapsulation method and Multichip stacking encapsulation body |
| TWI790503B (en) * | 2019-11-27 | 2023-01-21 | 台灣積體電路製造股份有限公司 | Integrated circuit package and method of forming same |
| WO2023077352A1 (en) * | 2021-11-04 | 2023-05-11 | 华为技术有限公司 | Package structure of optical communication module and preparation method |
| CN117976552A (en) * | 2024-04-02 | 2024-05-03 | 成都奕成集成电路有限公司 | Manufacturing method of chip packaging structure and chip packaging structure |
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| CN117976552A (en) * | 2024-04-02 | 2024-05-03 | 成都奕成集成电路有限公司 | Manufacturing method of chip packaging structure and chip packaging structure |
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Application publication date: 20180109 |