CN204946888U - Face-down bonding chip - Google Patents
Face-down bonding chip Download PDFInfo
- Publication number
- CN204946888U CN204946888U CN201520345046.7U CN201520345046U CN204946888U CN 204946888 U CN204946888 U CN 204946888U CN 201520345046 U CN201520345046 U CN 201520345046U CN 204946888 U CN204946888 U CN 204946888U
- Authority
- CN
- China
- Prior art keywords
- layer
- pad
- chip
- solder layer
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000003466 welding Methods 0.000 abstract description 18
- 230000000694 effects Effects 0.000 abstract description 10
- 238000005476 soldering Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- 230000000996 additive effect Effects 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010068 moulding (rubber) Methods 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The utility model discloses a kind of face-down bonding chip, comprise chip and substrate, described substrate is provided with pad, wherein, described pad is coated with solder layer, coatedly on described solder layer helps layer, described chip is by solder layer and help layer face-down bonding on substrate.Adopt the utility model, by coated solder layer and help layer successively on pad, solder layer and help layer to arrange respectively, solder layer to be fixed on pad and directly to contact with pad, layer is helped directly not contact with pad, under welding temperature, solder layer is fusible and be fully coated on the surface of pad, can not produce accuracy error, ensure accuracy, and help the hole produced in layer, do not affect the connection effect of face-down bonding chip, can ensure that welding effect, product yield are high.
Description
Technical field
The utility model relates to technical field of electronic components, particularly relates to a kind of face-down bonding chip.
Background technology
Chip face-down bonding be exactly ventricumbent silicon solder together with substrate interconnect, form reliable and stable machinery, electrical connection.Due to the chip bonding pad array arrangement of flip-chip, thus chip packing density is high; In addition, the interconnecting method that face-down bonding adopts chip and substrate directly to install, has the circuit characteristic of more superior high frequency, low delay, low crosstalk, is more suitable for the electronics applications of high frequency, high speed.So flip-chip bonding process word is since appearance, paid much attention in microelectronics Packaging always.
In prior art, usually solder and scaling powder are mixed to form soldering paste, and by solder paste application on the pad of substrate as the bonding agent of chip positioning, the interconnection of chip and substrate can be completed after welding.But existing technique needs to carry out a soldering paste process respectively to each pad, and required precision is high, and easily produces displacement between soldering paste and pad, causes production efficiency not high.Meanwhile, the effect of the face-down bonding chip adopting existing technique to make is unsatisfactory, and chip easily produces hole after being connected by soldering paste with the pad of pedestal, makes face-down bonding chip easily produce short circuit, affects the result of use of face-down bonding chip.
Summary of the invention
Technical problem to be solved in the utility model is, provides the face-down bonding chip that a kind of structure is simple, weldability good, yield is high.
In order to solve the problems of the technologies described above, the utility model provides a kind of face-down bonding chip, comprise chip and substrate, described substrate is provided with pad, wherein, described pad is coated with solder layer, coatedly on described solder layer helps layer, described chip is by solder layer and help layer face-down bonding on substrate.
As the improvement of such scheme, described pad is arranged in array.
As the improvement of such scheme, each pad is coated with solder layer, coatedly on each solder layer helps layer, corresponding to each solder layer, help layer separate.
As the improvement of such scheme, each pad is coated with solder layer, two often adjacent solder layers are coated by the same layer institute that helps.
As the improvement of such scheme, the thickness of described solder layer is 5 ~ 15 microns.
As the improvement of such scheme, described solder layer is tin layers.
As the improvement of such scheme, described pad is copper pad.
Enforcement the beneficial effects of the utility model are:
Substrate of the present utility model is provided with the pad corresponding with the pressure welding point of chip, by coated solder layer and help layer successively on pad, namely with solder layer and help layer to replace original soldering paste.Wherein, solder layer and help layer to arrange respectively, solder layer to be fixed on pad and directly to contact with pad, helps layer directly not contact with pad.Under welding temperature, solder layer is fusible and be fully coated on the surface of pad, can not produce accuracy error, ensure accuracy; Simultaneously, layer is helped to assist solder layer to melt with the connection realizing chip and substrate, correspondingly, directly do not contact with pad owing to helping layer, help the hole that the volatilization of solvent and portions additive in layer produces, do not affect the connection effect of face-down bonding chip, can ensure that welding effect, product yield are high.
In addition, in the utility model, every two adjacent pads can be divided into one group, each pad is coated with solder layer, two often adjacent solder layers are coated by the same layer institute that helps, the coated area helping layer is made to become large, by the mode of corresponding for original each pad one deck soldering paste, be converted to the mode that every two pads correspondence one helps layer, therefore, to the required precision step-down of bonder, make the aligning time shorten of the some rubber moulding block of bonder, spot welding effect is higher, save time, output effectively improves, more be conducive to the suitability for industrialized production of face-down bonding chip.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing face-down bonding chip;
Fig. 2 is the first example structure schematic diagram of the utility model face-down bonding chip;
Fig. 3 is the second example structure schematic diagram of the utility model face-down bonding chip.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearly, below in conjunction with accompanying drawing, the utility model is described in further detail.Only this statement, the present invention occurs in the text or is about to the up, down, left, right, before and after occurred, the orientation word such as inside and outside, only with accompanying drawing of the present invention for benchmark, it is not to concrete restriction of the present invention.
Show a kind of existing face-down bonding chip see Fig. 1, Fig. 1, comprise chip 1 and substrate 2, wherein, chip 1 is provided with pressure welding point 3, and substrate 2 is provided with pad 4, described pressure welding point 3 and pad 4 one_to_one corresponding.
Chip, then to be placed on substrate as the binding agent of chip positioning by solder paste application 5 on pad 4 by existing face-down bonding chip, and can complete interconnection after welding, underfill.But soldering paste 5 needs the connection melting to realize chip and substrate under welding temperature, but, along with the volatilization of solvent and portions additive in soldering paste 5, the junction of chip and pedestal can be made to produce hole, make face-down bonding chip easily produce short circuit, affect the result of use of face-down bonding chip.
See Fig. 2, Fig. 2 shows the first embodiment of the utility model face-down bonding chip, comprise chip 1 and substrate 2, wherein, chip 1 is provided with pressure welding point 3, and substrate 2 is provided with pad 4, and described pad 4 is coated with solder layer 6, coatedly on described solder layer 6 help layer 7, described chip 1 is by solder layer 6 and help layer 7 face-down bonding on substrate 2.Described pad 4 is arranged in array on substrate 2.
The utility model coated solder layer 6 and help layer 7 successively on the pad 4 of substrate 2, wherein, solder layer 6 and help layer 7 to arrange respectively, solder layer 6 defaults in the surface of pad 4, avoids, between solder layer 6 and pad 4, relative movement occurs.When carrying out face-down bonding, just on solder layer 6, coating helps layer 7.Correspondingly, solder layer 6 melts and is fully coated on the surface of pad 4 under welding temperature, simultaneously, the layer 7 that helps be coated on solder layer 6 melts the connection realizing chip 1 and substrate 2 with auxiliary solder layer 6 under welding temperature, but, because solder layer 6 directly contacts with pad 4, and help layer 7 directly not contact with pad 4, although help the volatilization of solvent and portions additive in layer 7, this does not affect the connection effect of face-down bonding chip, can ensure that welding effect, product yield are high.
Described solder layer 6 can be tin layers, silver layer, aluminium lamination, layers of copper or zinc layers, but not as restriction.
Further, the thickness of described solder layer 6 is 5 ~ 15 microns.It should be noted that, if the thickness of solder layer 6 is blocked up, pad 4 can be made to form floating effect, easily shut out the light; If the thickness of solder layer 6 is too thin, then easily form hole, make face-down bonding chip easily produce short circuit, affect the result of use of face-down bonding chip.The thickness of described solder layer 6 is preferably 10 microns, but not as restriction.
As shown in Figure 2, each pad 4 is coated with solder layer 6, coatedly on each solder layer 6 helps layer 7, corresponding to each solder layer 6, help layer 7 separate.
Described pad 4 is preferably copper pad, but not as restriction.
See Fig. 3, Fig. 3 shows the second embodiment of the utility model face-down bonding chip, with the chip first of face-down bonding shown in Fig. 2 embodiment difference be, in the chip of face-down bonding shown in Fig. 3, each pad 4 is coated with solder layer 6, two often adjacent solder layers 6 are coated by same layer 7 institute that helps.
It should be noted that, existing interconnection process needs each pad 4 solder paste application respectively, and soldering paste easily offsets in high temperature melting process, and required precision is high, causes production efficiency not high.In the second embodiment in the utility model, every two adjacent pads 4 are divided into one group, coated solder layer 6 in advance on each pad 4, avoids, between solder layer 6 and pad 4, relative movement occurs.When carrying out face-down bonding, arranging in units of group and helping layer, namely with helping layer 7 wrap up two adjacent pads 4 simultaneously, the coated area helping layer 7 is become greatly.Correspondingly, solder layer 6 melts and is fully coated on the surface of pad 4 under welding temperature, and the layer 7 that helps be coated on solder layer 6 assists solder layer 6 under welding temperature, melt to realize the connection of chip 1 and substrate 2.Simultaneously, due to the mode by the corresponding one deck soldering paste of an original pad 4, be converted to the mode that two pads 4 correspondences one help layer 7, therefore, to the required precision step-down of bonder, the aligning time shorten of the some rubber moulding block of bonder, make spot welding effect higher, save time, output effectively improves, and is more conducive to the suitability for industrialized production of face-down bonding chip.
The above is preferred implementation of the present utility model; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications are also considered as protection range of the present utility model.
Claims (4)
1. a face-down bonding chip, comprises chip and substrate, and described substrate is provided with pad, it is characterized in that, described pad is coated with solder layer, coatedly on described solder layer helps layer, and described chip is by solder layer and help layer face-down bonding on substrate;
Each pad is coated with solder layer, and two often adjacent solder layers are coated by the same layer institute that helps;
The thickness of described solder layer is 5 ~ 15 microns.
2. face-down bonding chip as claimed in claim 1, it is characterized in that, described pad is arranged in array.
3. face-down bonding chip as claimed in claim 1, it is characterized in that, described solder layer is tin layers.
4. face-down bonding chip as claimed in claim 1, it is characterized in that, described pad is copper pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520345046.7U CN204946888U (en) | 2015-05-26 | 2015-05-26 | Face-down bonding chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520345046.7U CN204946888U (en) | 2015-05-26 | 2015-05-26 | Face-down bonding chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204946888U true CN204946888U (en) | 2016-01-06 |
Family
ID=55014290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520345046.7U Active CN204946888U (en) | 2015-05-26 | 2015-05-26 | Face-down bonding chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204946888U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712899A (en) * | 2018-12-27 | 2019-05-03 | 通富微电子股份有限公司 | A kind of method for packaging semiconductor and semiconductor packing device |
| CN113113395A (en) * | 2021-03-25 | 2021-07-13 | Tcl华星光电技术有限公司 | Substrate and method for manufacturing light-emitting substrate |
| WO2023240576A1 (en) * | 2022-06-17 | 2023-12-21 | 厦门市芯颖显示科技有限公司 | Miniature electronic component, binding backplane, and binding assembly |
-
2015
- 2015-05-26 CN CN201520345046.7U patent/CN204946888U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109712899A (en) * | 2018-12-27 | 2019-05-03 | 通富微电子股份有限公司 | A kind of method for packaging semiconductor and semiconductor packing device |
| CN113113395A (en) * | 2021-03-25 | 2021-07-13 | Tcl华星光电技术有限公司 | Substrate and method for manufacturing light-emitting substrate |
| WO2023240576A1 (en) * | 2022-06-17 | 2023-12-21 | 厦门市芯颖显示科技有限公司 | Miniature electronic component, binding backplane, and binding assembly |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Flip-chip and welding method thereof Effective date of registration: 20170418 Granted publication date: 20160106 Pledgee: Guangdong Nanhai Rural Commercial Bank branch branch of Limited by Share Ltd. Pledgor: FOSHAN EVERCORE OPTOELECTRONIC TECHNOLOGY CO.,LTD. Registration number: 2017990000256 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20160106 Pledgee: Guangdong Nanhai Rural Commercial Bank branch branch of Limited by Share Ltd. Pledgor: FOSHAN EVERCORE OPTOELECTRONIC TECHNOLOGY CO.,LTD. Registration number: 2017990000256 |