CN203562420U - 一种半导体封装件 - Google Patents

一种半导体封装件 Download PDF

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CN203562420U
CN203562420U CN201320561273.4U CN201320561273U CN203562420U CN 203562420 U CN203562420 U CN 203562420U CN 201320561273 U CN201320561273 U CN 201320561273U CN 203562420 U CN203562420 U CN 203562420U
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lead frame
semiconductor package
chip
package part
utility
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黄源炜
徐振杰
曹周
敖利波
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Great Team Backend Foundry Dongguan Co Ltd
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Great Team Backend Foundry Dongguan Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型公开一种半导体封装件，所述半导体封装件包括导线架和芯片，所述导线架外部裸露部分镀有电镀层，所述导线架管脚侧面镀有电镀层。本实用新型通过在导线架的外部裸露部分镀有电镀层，特别是在导线架管脚侧面镀有电镀层的方式，本实用新型通过在导线架的外部裸露部分镀有电镀层，特别是在导线架管脚侧面镀有电镀层，为半导体封装件后续焊接到PCB板上时，提高两者的焊接牢固性提供了有力的保障。

Description

一种半导体封装件
技术领域
本实用新型属于半导体封装领域，具体涉及一种半导体封装件。 
背景技术
导线架作为集成电路的芯片载体，是一种借助于键合材料实现芯片内部电路引出端与外引线的电气连接，形成电气回路的关键结构件，它起到了和外部导线连接的桥梁作用，绝大部分的半导体集成块中都需要使用导线架，是电子信息产业中重要的基础材料。 
现有用导线架作为半导体芯片载体的半导体封装件，是将半导体芯片的非作用表面接置于导线架的芯片座，再通过多条焊线将半导体芯片的作用表面电性连接到导线架的管脚上，然后再借由封装胶体包覆半导体芯片、焊线以及导线架。现有半导体封装件往往在与PCB结合的时候由于结合力不足从而导致结合的不牢固。 
申请号为200510059833.6的中国发明专利说明书中公开了一种倒装芯片式封装结构及其制造方法，该封装结构包括导线架以及至少一个芯片；本发明的倒装芯片式封装结构及其制造方法主要是将芯片作用表面上的焊锡凸块经回焊制程接置并电性连接在导线架上前。很显然，本发明中只是在导线架的底部设有焊锡层，并不能很好的保证焊线的质量。 
实用新型内容
本实用新型目的是提供一种在半导体封装件后续焊接到PCB板上时，保证两者的焊接牢固性的半导体封装件。 
一种半导体封装件，包括导线架和芯片，所述导线架具有一芯片座，所述芯片通过结合材固定在所述芯片座上，所述芯片与导线架的管脚连有焊线，一封装胶体包覆芯片于导线架上，所述导线架外部裸露部分镀有电镀层。 
作为一种优选的方案，所述导线架管脚侧面镀有电镀层。 
作为一种更优选方案，所述电镀层为锡层。 
较佳地，所述结合材为胶水。 
本实用新型通过在导线架的外部裸露部分镀有电镀层，特别是在导线架管脚侧面镀有电镀层，增加导线架的电镀层和电镀层的面积，为半导体封装件后续焊接到PCB板上时，提高两者的焊接牢固性提供了有力的保障 
附图说明
为了更清楚地说明本实用新型实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本实用新型的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。 
图1是本实用新型半导体封装件结构示意图。 
具体实施方式
下面将结合本实用新型实施例中的附图，对本实用新型实施例中的技术方案进行清楚、完整地描述。基于本实用新型中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本实用新型保护的范围。 
实施例1 
参考图1，一种半导体封装件，包括导线架1和芯片2，所述导线架1具有一芯片座3，所述芯片2通过结合材8固定在所述芯片座3上，所述芯片2与导线架1的管脚4连有焊线5，一封装胶体6包覆芯片2于导线架1上，所述导线架1外部裸露部分镀有电镀层7，同时所述导线架管脚4侧面镀有镀锡层7。 
本实施例通过在导线架1的外部裸露部分镀有镀锡层7，特别是在导线架管脚4侧面镀有镀锡层7，增加导线架1的镀锡层和镀锡层的面积，使得半导体封装件后续焊接到PCB板上时，提高了两者的焊接牢固性。 
以上内容是结合具体的优选实施方式对本实用新型所作的进一步详细说明，不能认定本实用新型的具体实施只局限于这些说明。对于本实用新型所属 技术领域的普通技术人员来说，在不脱离本实用新型构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本实用新型的保护范围。 

Claims (4)

1.一种半导体封装件，包括导线架和芯片，所述导线架具有一芯片座，所述芯片通过结合材固定在所述芯片座上，所述芯片与导线架的管脚连有焊线，一封装胶体包覆芯片于导线架上，其特征是，所述导线架外部裸露部分镀有电镀层。
2.根据权利要求1所述一种半导体封装件，其特征是，所述导线架管脚侧面镀有电镀层。
3.根据权利要求1或2所述一种半导体封装件，其特征是，所述电镀层为锡层。
4.根据权利要求1所述一种半导体封装件，其特征是，所述结合材为胶水。
CN201320561273.4U 2013-09-11 2013-09-11 一种半导体封装件 Expired - Lifetime CN203562420U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104576407A (zh) * 2014-12-30 2015-04-29 杰群电子科技（东莞）有限公司 一种引线框架管脚端面镀锡的封装方法及封装结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104576407A (zh) * 2014-12-30 2015-04-29 杰群电子科技（东莞）有限公司 一种引线框架管脚端面镀锡的封装方法及封装结构
CN104576407B (zh) * 2014-12-30 2018-08-03 杰群电子科技（东莞）有限公司 一种引线框架管脚端面镀锡的封装方法及封装结构

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