CN203386762U - Mesa-type glassivation diode chip - Google Patents
Mesa-type glassivation diode chip Download PDFInfo
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- CN203386762U CN203386762U CN201320489014.5U CN201320489014U CN203386762U CN 203386762 U CN203386762 U CN 203386762U CN 201320489014 U CN201320489014 U CN 201320489014U CN 203386762 U CN203386762 U CN 203386762U
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- temperature oxidation
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- glassivation
- mesa
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Abstract
The utility model discloses a mesa-type glassivation diode chip in the field of electronic-element manufacturing. The chip includes a PN junction on a semiconductor substrate, and glassivation glass layers and a low-temperature oxidation interlayer, which are arranged on a side wall of a mesa and covers the outer part of the PN junction. The chip is characterized in that the glassivation layers include two layers, wherein the low-temperature oxidation interlayer is added between a first layer and a second layer; and a thickness of the low-temperature oxidation interlayer is 1+-0.5 mum so that the glassivation glass layers and the low-temperature oxidation interlayer around the PN junction are capable of improving high-temperature reliability performance of the chip effectively. The mesa-type glassivation diode chip has the advantages of being reasonable in process, great in product quality and high in product pressure resistance and high-temperature reliability and the like.
Description
Technical field
The utility model relates to a kind of semiconductor components and devices of manufacture field of electronic elements, is specifically a kind of mesa type glass passivated diode chip.
Background technology
At electronics production field diode, be a kind of electronic semi-conductor's components and parts commonly used, the glass passivating method of the mesa type glass passivated diode chip that the production technology of diode adopts usually at present is to adopt knife coating.Its main method is that glass metal is scraped in the chip groove, carries out sintering after oven dry, again glass metal is scraped in the chip groove, carries out sintering after oven dry and forms.The glass formed as stated above is that the PN junction place is thinner, and channel bottom is thicker, affects the withstand voltage properties of high pressure material, and its high temperature reliability can be general.
Summary of the invention
The purpose of the present utility model is to overcome the deficiencies in the prior art, provides a kind of high temperature reliability energy good and stable mesa type glass passivated diode chip.The present utility model is achieved through the following technical solutions:
A kind of mesa type glass passivated diode chip, comprise that the on-chip PN junction of a block semiconductor, table top sidewall are coated on glass passivation layer and the low-temperature oxidation interlayer of PN junction outside, it is characterized in that: described glass passivation layer is divided two-layer, wherein between one deck and two layers, increases the low-temperature oxidation interlayer; Technique scheme is done to further restriction, and described low-temperature oxidation compartment thickness is 1 ± 0.5um, and PN junction is glass passivation layer and low-temperature oxidation interlayer on every side, can effectively improve the high temperature reliability energy of chip.The utility model compared with prior art has following beneficial effect:
1. technique is reasonable, good product quality;
2. product resistance to pressure, high temperature reliability are high.
Accompanying drawing explanation glass passivation layer
Fig. 1 is the mesa type glass passivated diode chip structural representation.
In figure: PN junction 1, glass passivation layer 2 and low-temperature oxidation interlayer 3.
Embodiment
Below in conjunction with accompanying drawing, content of the present utility model is described further:
As figure is the mesa type glass passivated diode chip structural representation, comprise and adopt different doping processs, P type semiconductor and N type semiconductor are produced on the same semiconductor chip and at the PN junction 1 of its interface formation.And be positioned at glass passivation layer 2 and the low-temperature oxidation interlayer 3 that the table top sidewall is coated on the PN junction outside.In the present embodiment, the thickness of low-temperature oxidation LTO interlayer is 1 ± 0.5um; As shown in the figure, increase low-temperature oxidation LTO interlayer 3 in the middle of near the glass passivation layer 2 PN junction 1, adopt the mesa type glass passivated diode chip of this structure, can effectively improve the high temperature reliability energy of chip in industrial production.
Claims (2)
1. a mesa type glass passivated diode chip, comprise that the on-chip PN junction of a block semiconductor, table top sidewall are coated on glass passivation layer and the low-temperature oxidation interlayer of PN junction outside, it is characterized in that: described glass passivation layer is divided two-layer, wherein between one deck and two layers, increases the low-temperature oxidation interlayer.
2. mesa type glass passivated diode chip as claimed in claim 1, it is characterized in that: described low-temperature oxidation compartment thickness is 1 ± 0.5um.
Priority Applications (1)
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CN201320489014.5U CN203386762U (en) | 2013-08-12 | 2013-08-12 | Mesa-type glassivation diode chip |
Applications Claiming Priority (1)
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CN201320489014.5U CN203386762U (en) | 2013-08-12 | 2013-08-12 | Mesa-type glassivation diode chip |
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CN203386762U true CN203386762U (en) | 2014-01-08 |
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CN201320489014.5U Expired - Fee Related CN203386762U (en) | 2013-08-12 | 2013-08-12 | Mesa-type glassivation diode chip |
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CN (1) | CN203386762U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104064533A (en) * | 2014-07-03 | 2014-09-24 | 江苏东光微电子股份有限公司 | QFN packaging structure and method for double-face semiconductor device |
CN112289786A (en) * | 2020-10-22 | 2021-01-29 | 深圳市海弘建业科技有限公司 | Multilayer chip RFC4K ultrahigh voltage-withstanding GPP axial fast recovery rectifier diode |
-
2013
- 2013-08-12 CN CN201320489014.5U patent/CN203386762U/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104064533A (en) * | 2014-07-03 | 2014-09-24 | 江苏东光微电子股份有限公司 | QFN packaging structure and method for double-face semiconductor device |
CN112289786A (en) * | 2020-10-22 | 2021-01-29 | 深圳市海弘建业科技有限公司 | Multilayer chip RFC4K ultrahigh voltage-withstanding GPP axial fast recovery rectifier diode |
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Legal Events
Date | Code | Title | Description |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140108 Termination date: 20190812 |