CN204315628U - A kind of LED flip chip and LED flip chip group - Google Patents
A kind of LED flip chip and LED flip chip group Download PDFInfo
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- CN204315628U CN204315628U CN201420853537.8U CN201420853537U CN204315628U CN 204315628 U CN204315628 U CN 204315628U CN 201420853537 U CN201420853537 U CN 201420853537U CN 204315628 U CN204315628 U CN 204315628U
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Abstract
The utility model discloses a kind of LED flip chip and LED flip chip group, the electrode that LED flip chip comprises N layer, is located at the P layer on N layer and is connected with bottom N layer and bottom P layer respectively; Between N layer and P layer, be formed with the first insulating barrier, between N layer and P layer, be formed with step, be provided with the second insulating barrier covering P layer end face and N layer end face in one end relative with step.LED flip chip group is made up of the LED flip chip of more than two, is formed with the etching bath of through N layer and P layer, is filled with the second insulating barrier in etching bath between adjacent LED flip chip.Structure of the present utility model, even if there is the phenomenon that tin cream climbs in die bond process, also can not allow N layer be communicated with short circuit with P layer.
Description
Technical field
The utility model relates to LED flip chip.
Background technology
There is a kind of LED flip chip at present as shown in Figure 1, comprise N layer 1, P layer 2, N pole articulamentum 3, electrode 4, the 3rd insulating barrier 5, Sapphire Substrate 6.P layer 2 is located at the bottom surface of N layer 1, has the first insulating barrier between N layer 1 and P layer 2, and prevent N layer 1 and P layer 2 short circuit, P layer 1 is all protruded at the two ends of N layer 1, and the protrusion length of N layer 1 one end is greater than the protrusion length of N layer 1 other end; N pole articulamentum 3 is connected to the bottom surface of N layer; The bottom surface of P layer 2 is connected with electrode, is provided with electrode in the bottom surface of N pole articulamentum 3.At electrode 4 and be provided with the 3rd described insulating barrier the 5, three insulating barrier 5 preferably silicon dioxide insulating layer between N layer 1 and P layer 2; Described Sapphire Substrate 6 is located on N layer 1.
As shown in Figure 2, as needs die bond on substrate 9, first need the location point tin cream 10 for electrode on substrate 9, then above-mentioned LED flip chip is press fit on substrate 9, makes electrode corresponding with tin cream, when press-fiting LED flip chip, if tin cream consumption is very few, then die bond is insecure, unreliable, if tin cream consumption is excessive, as shown in Figure 3, tin cream end of climbing from the edge of LED flip chip can be caused to cause P pole and the conducting of N pole and the phenomenon of short circuit can be produced.
Summary of the invention
For solving the problems of the technologies described above, the utility model provides a kind of LED flip chip and LED flip chip group.
The technical scheme solved the problems of the technologies described above is: a kind of LED flip chip, the electrode comprising N layer, be located at the P layer on N layer and be connected with bottom N layer and bottom P layer respectively; Between N layer and P layer, be formed with the first insulating barrier, between N layer and P layer, be formed with step, be provided with the second insulating barrier covering P layer end face and N layer end face in one end relative with step.
A kind of LED flip chip group, is made up of the LED flip chip of more than two; The electrode that LED flip chip comprises N layer, is located at the P layer on N layer and is connected with bottom N layer and bottom P layer respectively; Between N layer and P layer, be formed with the first insulating barrier, between N layer and P layer, be formed with step, be provided with the second insulating barrier covering P layer end face and N layer end face in one end relative with step; Be formed with the etching bath of through N layer and P layer between adjacent LED flip chip, in etching bath, be filled with the second insulating barrier.
Further, P layer is positioned at the below of N layer, and in one end relative with step, P layer is concordant with the end face of N layer, and in one end identical with step, N layer protrudes P layer; The N layer end face of one end identical with step is coated with the second insulating barrier.
Further, N pole articulamentum is provided with between the electrode be connected with N layer and N layer; At electrode and be provided with the 3rd insulating barrier between N layer and P layer, N layer is provided with Sapphire Substrate; Second insulating barrier and the 3rd insulating barrier are connected as a single entity.
The beneficial effects of the utility model are: owing to being provided with the second insulating barrier, like this, even if there is the phenomenon that tin cream climbs in die bond process, N layer also can not be allowed to be communicated with short circuit with P layer.Because logical overetched technique defines etching bath, like this, the N layer of wherein one end can be made concordant with the end face of P layer, the second insulating barrier can be filled again in etching bath, then form LED flip chip through cutting, form the second insulating barrier in the end of LED flip chip, therefore, easily manufactured, cost is low.
Accompanying drawing explanation
Fig. 1 is the structural representation of LED flip chip in background technology.
Fig. 2 is the structural representation of LED flip chip die bond in background technology.
When Fig. 3 is LED flip chip die bond in background technology, tin cream occurs climbing the structural representation of phenomenon.
Fig. 4 is the schematic diagram of the utility model LED flip chip.
Fig. 5 is the schematic diagram of LED flip chip group.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is further elaborated.
Embodiment 1.
As shown in Figure 4, LED flip chip comprises N layer 1, P layer 2, N pole articulamentum 3, electrode 4, the 3rd insulating barrier 5, Sapphire Substrate 6.P layer 2 is located at the bottom surface of N layer 1, has the first insulating barrier between N layer 1 and P layer 2, and prevent N layer 1 and P layer 2 short circuit, one end of N layer 1 is all protruded P layer 1 and form step between N layer and P layer, and in one end relative with step, P layer 2 is concordant with the end face of N layer 1; N pole articulamentum 3 is connected to the bottom surface of N layer; The bottom surface of P layer 2 is connected with electrode, is provided with electrode in the bottom surface of N pole articulamentum 3.At electrode 4 and be provided with the 3rd described insulating barrier the 5, three insulating barrier 5 preferably silicon dioxide insulating layer between N layer 1 and P layer 2; Described Sapphire Substrate 6 is located on N layer 1.Be provided with the second insulating barrier 7, the second insulating barrier 7 preferably silicon dioxide insulating layer covering P layer 2 end face and N layer 1 end face in one end relative with step, the second insulating barrier 7 and the 3rd insulating barrier 5 are integrated.
The LED flip chip of present embodiment, in die bond process, even if the phenomenon that tin cream climbs appears in the tin cream 10 put on substrate 9, also can not allow N layer be communicated with short circuit with P layer.
In the present embodiment, as the improvement to above-mentioned LED flip chip, the N layer end face of one end identical with step also can cover the second insulating barrier.
Embodiment 2.
As shown in Figure 5, LED flip chip group is made up of the LED flip chip 100 of more than two.
Be formed with the etching bath 11 of through N layer and P layer between adjacent LED flip chip 100, in etching bath 11, be filled with the second insulating barrier.After etching bath 11 is cut, form LED flip chip as shown in Figure 4.
As shown in Figure 4, LED flip chip comprises N layer 1, P layer 2, N pole articulamentum 3, electrode 4, the 3rd insulating barrier 5, Sapphire Substrate 6.P layer 2 is located at the bottom surface of N layer 1, has the first insulating barrier between N layer 1 and P layer 2, and prevent N layer 1 and P layer 2 short circuit, one end of N layer 1 is all protruded P layer 1 and form step between N layer and P layer, and in one end relative with step, P layer 2 is concordant with the end face of N layer 1; N pole articulamentum 3 is connected to the bottom surface of N layer; The bottom surface of P layer 2 is connected with electrode, is provided with electrode in the bottom surface of N pole articulamentum 3.At electrode 4 and be provided with the 3rd described insulating barrier the 5, three insulating barrier 5 preferably silicon dioxide insulating layer between N layer 1 and P layer 2; Described Sapphire Substrate 6 is located on N layer 1.Be provided with the second insulating barrier 7, the second insulating barrier 7 preferably silicon dioxide insulating layer covering P layer 2 end face and N layer 1 end face in one end relative with step, the second insulating barrier 7 and the 3rd insulating barrier 5 are integrated.
The LED flip chip of present embodiment, in die bond process, even if the phenomenon that tin cream climbs appears in the tin cream 10 put on substrate 9, also can not allow N layer be communicated with short circuit with P layer.Because logical overetched technique defines etching bath, like this, the N layer of wherein one end can be made concordant with the end face of P layer, the second insulating barrier can be filled again in etching bath, then form LED flip chip through cutting, form the second insulating barrier in the end of LED flip chip, therefore, easily manufactured, cost is low.
Claims (9)
1. a LED flip chip, the electrode comprising N layer, be located at the P layer on N layer and be connected with bottom N layer and bottom P layer respectively; Between N layer and P layer, be formed with the first insulating barrier, be formed with step between N layer and P layer, it is characterized in that: be provided with the second insulating barrier covering P layer end face and N layer end face in one end relative with step.
2. LED flip chip according to claim 1, is characterized in that: P layer is positioned at the below of N layer, in one end relative with step, P layer is concordant with the end face of N layer, and in one end identical with step, N layer protrudes P layer.
3. LED flip chip according to claim 2, is characterized in that: on the N layer end face of one end identical with step, be coated with the second insulating barrier.
4. LED flip chip according to claim 2, is characterized in that: be provided with N pole articulamentum between the electrode be connected with N layer and N layer.
5. LED flip chip according to claim 1, is characterized in that: at electrode and be provided with the 3rd insulating barrier between N layer and P layer, and N layer is provided with Sapphire Substrate.
6. LED flip chip according to claim 5, is characterized in that: the second insulating barrier and the 3rd insulating barrier are connected as a single entity.
7. a LED flip chip group, is made up of the LED flip chip of more than two; The electrode that LED flip chip comprises N layer, is located at the P layer on N layer and is connected with bottom N layer and bottom P layer respectively; Between N layer and P layer, be formed with the first insulating barrier, between N layer and P layer, be formed with step, be provided with the second insulating barrier covering P layer end face and N layer end face in one end relative with step; It is characterized in that: the etching bath being formed with through N layer and P layer between adjacent LED flip chip, is filled with the second insulating barrier in etching bath.
8. LED flip chip group according to claim 7, is characterized in that: P layer is positioned at the below of N layer, and in one end relative with step, P layer is concordant with the end face of N layer, and in one end identical with step, N layer protrudes P layer; The N layer end face of one end identical with step is coated with the second insulating barrier.
9. LED flip chip group according to claim 8, is characterized in that: be provided with N pole articulamentum between the electrode be connected with N layer and N layer; At electrode and be provided with the 3rd insulating barrier between N layer and P layer, N layer is provided with Sapphire Substrate; Second insulating barrier and the 3rd insulating barrier are connected as a single entity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420853537.8U CN204315628U (en) | 2014-12-30 | 2014-12-30 | A kind of LED flip chip and LED flip chip group |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420853537.8U CN204315628U (en) | 2014-12-30 | 2014-12-30 | A kind of LED flip chip and LED flip chip group |
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| CN204315628U true CN204315628U (en) | 2015-05-06 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106025010A (en) * | 2016-07-19 | 2016-10-12 | 厦门乾照光电股份有限公司 | Flip LED chip based on conductive DBR structure and manufacturing method thereof |
| CN109616564A (en) * | 2018-10-26 | 2019-04-12 | 华灿光电(苏州）有限公司 | A kind of flip LED chips and preparation method thereof |
-
2014
- 2014-12-30 CN CN201420853537.8U patent/CN204315628U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106025010A (en) * | 2016-07-19 | 2016-10-12 | 厦门乾照光电股份有限公司 | Flip LED chip based on conductive DBR structure and manufacturing method thereof |
| CN109616564A (en) * | 2018-10-26 | 2019-04-12 | 华灿光电(苏州）有限公司 | A kind of flip LED chips and preparation method thereof |
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Address after: 510890 Huadu District, Guangdong, Guangzhou Flower Town, SAST Road, No. 1, No. 1 Patentee after: Hongli Newell group Limited by Share Ltd Address before: Huadu District, Guangdong city of Guangzhou Province, 510890 East Town Airport high-tech industrial base and SAST Jingu South Road intersection Patentee before: Guangzhou Hongli Tronic Co., Ltd. |