CN203340409U - A patterned ceramic layer printed circuit substrate for optical and electronic devices - Google Patents
A patterned ceramic layer printed circuit substrate for optical and electronic devices Download PDFInfo
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- CN203340409U CN203340409U CN2013203451954U CN201320345195U CN203340409U CN 203340409 U CN203340409 U CN 203340409U CN 2013203451954 U CN2013203451954 U CN 2013203451954U CN 201320345195 U CN201320345195 U CN 201320345195U CN 203340409 U CN203340409 U CN 203340409U
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- ceramic layer
- printed circuit
- circuit substrate
- optics
- electronic device
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Abstract
The utility model relates to a patterned ceramic layer printed circuit substrate for optical and electronic devices. The patterned ceramic layer printed circuit substrate comprises a metallic basic body on which ceramic layers are formed. Multiple isolating pedestals are formed by etching the ceramic layers. The patterned ceramic layer printed circuit substrate for optical and electronic devices has the metallic basic body with a larger size and is capable of containing multiple optical and/or electronic devices which have good electrical isolation and thermal insulation.
Description
Technical field
The utility model belongs to electronic technology field, and in particular, the utility model relates to a kind of ceramic layer of the patterning for optics and electronic device printed circuit substrate.
Background technology
For the device of optics and/or electronics, as integrated circuit or laser diode all need to utilize heat conducting material to be conducted heat.Need to adopt metallic matrix for this reason, as the copper matrix, and often need the electricity isolation between the device of described optics and/or electronics and metallic matrix.And some ceramic material has higher heat conduction efficiency and electricity is insulated.The ceramic material that for this reason between the device of be everlasting optics and/or electronics and metallic matrix, uses high heat conduction is as for providing electricity isolation and the conductive intermediate materials of maintaining heat still.For the efficient heat transfer from the device of optics and/or electronics to metallic matrix is provided, it is essential that good hot interface is provided between pottery and metallic matrix.
And, in increasing application, a plurality of optics and/or electronic device need to be coupled in the functional structure with electricity isolation and heat conduction.And, in order to hold a plurality of optics and/or electronic device, need to use larger sized basis material, for example need to use larger metallic matrix and ceramic wafer.If yet, when described a plurality of optics and/or electronic device being coupled on the ceramic component at single interface, between the optics of each coupling and/or electronic device, will cause difficult heat transfer, and may cause electrically conduction and be short-circuited.For this reason, need between a plurality of optics and/or electronic device, provide electricity isolation and heat isolation.
The utility model content
In order to solve above-mentioned technical problem of the prior art, the purpose of this utility model is to provide a kind of ceramic layer of the patterning for optics and electronic device printed circuit substrate.
To achieve these goals, the utility model has adopted following technical scheme:
The utility model relates to a kind of ceramic layer of the patterning for optics and electronic device printed circuit substrate, comprises metallic matrix, it is characterized in that being formed with ceramic layer on described metallic matrix; And the described ceramic layer of etching forms a plurality of isolation pedestals.
Wherein, the thickness of described ceramic layer is 10-500 μ m; Described ceramic layer is selected from least two kinds in aluminium oxide, beryllium oxide, aluminium nitride, silicon nitride, boron nitride, carborundum or boron carbide.
Wherein, described withstand voltage ceramic layer prepares by sputter, evaporation, arc deposited, ion plating, chemical vapour deposition (CVD) or powder sintering.
Wherein, there is transition zone between described metallic matrix and described ceramic layer.
Wherein, the thickness of described transition zone is 10-500 nm.
Wherein, described transition zone prepares by sputter, evaporation, arc deposited, ion plating or chemical vapour deposition technique.
Wherein, there is brazing layer between described metallic matrix and described ceramic layer.
Wherein, the solder that described brazing layer is used is the Cu solder alloy.
The technical solution of the utility model has following beneficial effect compared to existing technology:
(1) ceramic layer of the patterning for optics and electronic device printed circuit substrate described in the utility model, there is larger sized metal substrate, and can hold a plurality of optics and/or electronic device, and there is good electricity isolation and heat isolation between described a plurality of optics and/or electronic device.
(2) ceramic layer of the patterning for optics and electronic device printed circuit substrate described in the utility model, the thermal conductivity of described highly heat-conductive carbon/ceramic enamel coating is greater than 20 W/mK, but also has high proof voltage breakdown performance; Can realize radially effectively heat conduction and transfer, solve the heat dissipation problem of optics and/or electronic unit.
(3) ceramic layer of the patterning for optics and electronic device printed circuit substrate described in the utility model, can on described isolation pedestal, form the metallic circuit layer as required, described metallic circuit layer can be by depositing metal layers on the thermal conductive ceramic layer, and then dry ecthing forms; Also can after forming, the isolation pedestal form by deposition or coating.
The accompanying drawing explanation
The schematic diagram that Fig. 1 is the described ceramic layer of the patterning for optics and electronic device of embodiment 1 printed circuit substrate.
The schematic diagram that Fig. 2 is the described ceramic layer of the patterning for optics and electronic device of embodiment 2 printed circuit substrate.
The schematic diagram that Fig. 3 is the described ceramic layer of the patterning for optics and electronic device of embodiment 3 printed circuit substrate.
Embodiment
The utility model relates to a kind of ceramic layer of the patterning for optics and electronic device printed circuit substrate, comprises metallic matrix, it is characterized in that being formed with the ceramic layer of withstand voltage and high heat conduction on described metallic matrix; And the described ceramic layer of etching forms a plurality of isolation pedestals.The thickness of described ceramic layer is 10-500 μ m; Described ceramic layer is selected from least two kinds in aluminium oxide, beryllium oxide, aluminium nitride, silicon nitride, boron nitride, carborundum or boron carbide.Preferably, also there is transition zone or brazing layer between described metallic matrix and described ceramic layer.And the solder that described brazing layer is used is the Cu solder alloy.
embodiment 1
As shown in Figure 1, the described ceramic layer of the patterning for optics and electronic device of the present embodiment printed circuit substrate, comprise aluminum or aluminum alloy matrix 10, is formed with the ceramic layer 30 of withstand voltage and high heat conduction on described aluminum or aluminum alloy matrix 10; And by mask, described ceramic layer 30 is carried out to selective etch and form a plurality of isolation pedestals 50.The step of described compound withstand voltage ceramic layer adopts following technique, and its reaction system is AlCl
3-H
2o-NH
3-O
2-H
2, reaction temperature is 420-450 ℃, operating pressure is 1200Pa, wherein AlCl
3flow be 50 ml/min, H
2the flow of O is 10-20 ml/min, O
2flow be 15-20 ml/min, NH
3flow be 25-30 ml/min, H
2flow be 500 ml/min, film thickness is 200 μ m.The breakdown voltage resistant 5.0kV of being greater than of the structure obtained by this embodiment, the thermal conductivity of described ceramic coating is greater than 100 W/mK.The described structure of the present embodiment can be for electronic devices such as the optics such as LED etc. or wiring boards, and can be on single metal substrate a plurality of optics of intensive laying and/or electronic device, and needn't worry heat conduction and the conductivity between described a plurality of optics and/or electronic device.
embodiment 2
As shown in Figure 2, the described ceramic layer of the patterning for optics and electronic device of the present embodiment printed circuit substrate, comprise aluminum or aluminum alloy matrix 10, is formed with the ceramic layer 30 of withstand voltage and high heat conduction on described aluminum or aluminum alloy matrix 10; There is aluminium transition zone 20 between described aluminum or aluminum alloy matrix 10 and ceramic layer 30, and by mask, described ceramic layer 30 is carried out to selective etch and form a plurality of isolation pedestals 50.Wherein, described aluminium transition zone deposits and obtains by sputtering method.Described compound withstand voltage ceramic layer prepares by powder sintering, and the thickness of ceramic layer is 200 μ m.The breakdown voltage resistant 5.0kV of being greater than of the structure obtained by this embodiment, the thermal conductivity of described ceramic coating is greater than 100 W/mK.The described structure of the present embodiment can be for electronic devices such as the optics such as LED etc. or wiring boards, and can be on single metal substrate a plurality of optics of intensive laying and/or electronic device, and needn't worry heat conduction and the conductivity between described a plurality of optics and/or electronic device.
embodiment 3
As shown in Figure 3, the described ceramic layer of the patterning for optics and electronic device of the present embodiment printed circuit substrate, comprise copper or copper alloy matrix 10, is formed with the ceramic layer 30 of withstand voltage and high heat conduction on described copper or copper alloy matrix 10; There is brazing layer 40 between described copper or copper alloy matrix 10 and ceramic layer 30, and by mask, described ceramic layer 30 is carried out to selective etch and form a plurality of isolation pedestals 50.Described ceramic layer consists of beryllium oxide and aluminium oxide, and described ceramic layer is made by powder sintering, and sintering temperature is 1850-2000 ℃, and the thickness of described ceramic layer is 200 μ m.Described ceramic layer is attached on copper or copper alloy matrix 10 surfaces by the active soldering method.The breakdown voltage resistant 5.0kV of being greater than of the structure obtained by this embodiment, the thermal conductivity of described ceramic coating is greater than 20 W/mK.
For the ordinary skill in the art, be to be understood that and can not breaking away from the utility model scope of disclosure, can adopt to be equal to and replace or equivalent transformation form enforcement above-described embodiment.Protection range of the present utility model is not limited to the specific embodiment of embodiment part, as long as no the execution mode that breaks away from utility model essence, within all being interpreted as dropping on the protection range of the utility model requirement.
Claims (5)
1. the ceramic layer of the patterning for an optics and electronic device printed circuit substrate, comprise metallic matrix, it is characterized in that being formed with ceramic layer on described metallic matrix; And the described ceramic layer of etching forms a plurality of isolation pedestals.
2. the ceramic layer of the patterning for optics and electronic device printed circuit substrate according to claim 1, the thickness that it is characterized in that described ceramic layer is 10-500 μ m.
3. the ceramic layer of the patterning for optics and electronic device printed circuit substrate according to claim 1 and 2, is characterized in that having transition zone between described metallic matrix and described ceramic layer.
4. the ceramic layer of the patterning for optics and electronic device printed circuit substrate according to claim 3, the thickness that it is characterized in that described transition zone is 10-500nm.
5. the ceramic layer of the patterning for optics and electronic device printed circuit substrate according to claim 1 and 2, is characterized in that having brazing layer between described metallic matrix and described ceramic layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203451954U CN203340409U (en) | 2013-06-17 | 2013-06-17 | A patterned ceramic layer printed circuit substrate for optical and electronic devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203451954U CN203340409U (en) | 2013-06-17 | 2013-06-17 | A patterned ceramic layer printed circuit substrate for optical and electronic devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203340409U true CN203340409U (en) | 2013-12-11 |
Family
ID=49709059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013203451954U Expired - Fee Related CN203340409U (en) | 2013-06-17 | 2013-06-17 | A patterned ceramic layer printed circuit substrate for optical and electronic devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203340409U (en) |
-
2013
- 2013-06-17 CN CN2013203451954U patent/CN203340409U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SUZHOU JINGPIN ADVANCED MATERIALS CO., LTD. Free format text: FORMER NAME: SUZHOU JINGPIN PHOTOELECTRIC TECHNOLOGY CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: Wujiang District of Suzhou City, Jiangsu province 215200 Lili town FENHU Road No. 558 Patentee after: Suzhou Jing Pin new material limited company Address before: FenHu FenHu Avenue in Wujiang District of Suzhou City, Jiangsu province 215211 No. 558 No. two on the third floor of the building of scientific research innovation park (South) Patentee before: Suzhou Jingpin Optical-Electronical Technology Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131211 Termination date: 20160617 |