CN203325892U

CN203325892U - Wafer particle

Info

Publication number: CN203325892U
Application number: CN2012205876441U
Authority: CN
Inventors: 王海泉; 姜凤明
Original assignee: Individual
Current assignee: Individual
Priority date: 2012-11-09
Filing date: 2012-11-09
Publication date: 2013-12-04
Anticipated expiration: 2022-11-09

Abstract

The utility model relates to a wafer particle. The wafer particle comprises a multi-layer integrated circuit and PAD points connected with the multi-layer integrated circuit. The wafer particle is characterized in that: the PAD points are the rectangular or square PAD points of which diameters are equal to or greater than 60um and are equal to or smaller than 500um, a distance of every two center points between every two PAD points is equal to or greater than 100um and is equal to or smaller than 2mm, a face of the wafer particle having the PAD points is provided with an insulation covering layer which is used for protecting a wafer from being short-circuited or worn in a subsequent processing process. The wafer particle can employ surface mount technology (SMT) to carry out carrier tape packaging to complete production of intelligent cards, can greatly improve production efficiency and reduces cost.

Description

A kind of wafer particle

Technical field

The utility model relates to the smart card production field, is a kind of wafer particle specifically, and this wafer can be packaged into smart card by adopting traditional paster encapsulation technology (SMT).A kind of new wafer espespecially used in intelligent card chip particle (die) is encapsulated in to smart card circuitry plate process, this smart card circuitry plate generally is referred to as carrier band or slide glass in industry.

Background technology

Wafer refers to Si semiconductor integrated circuit making silicon wafer used, because it is shaped as circle, therefore be called wafer; Can manufacture various circuit component structures on silicon wafer, and become, the IC of specific electrical function product be arranged, can be used as intelligent card chip particle (die).

According to existing production technology, intelligent card chip particle (die) is before being packaged into the finished product smart card, capital is encapsulated into intelligent card chip particle (die) on carrier band or slide glass, and then will, with carrier band or the slide glass of intelligent card chip particle (die), by PUR or other adhesives, the back side of carrier band or slide glass be embedded on the card base of the smart card that washes the big or small groove of correspondence.The front of carrier band or slide glass is large stretch of filled gold face, carry out communication for smart card and outside, the back side of carrier band or slide glass is the vacant zone of the circuit, intelligent card chip particle (die) pasting area and the surrounding that are connected with intelligent card chip particle (die), and this vacant zone can be used for coating hot-melt adhesive or other adhesives and embeds, is fixed in the card base of smart card.

The process that intelligent card chip particle (die) is encapsulated on carrier band or slide glass generally is referred to as the carrier band encapsulation.This and the common chip package of electron trade are not concepts, and generally we mention chip package and refer to the encapsulation of chip plastic packaging.An important requirement of carrier band encapsulation is exactly packed chip will be in the wafer graininess.The apparent size figure of common this wafer is as Fig. 1, its PAD (102) point generally distributes on four limits of wafer, for this wafer is general, adopt following two kinds of techniques to do the carrier band encapsulation: a kind of is lead key closing process, and a kind of is Flip Chip Bond Technique (FCOS).Below do introduction with regard to two kinds of techniques respectively.

The carrier band of smart card is packaged with two kinds of methods at present.A kind of method is to adopt lead key closing process, at first by the wafer of intelligent card chip (wafer) attenuate, then to intelligent card chip wafer (wafer), scribing obtains some intelligent card chip wafer particles (die), next carry out die bond (die bond) or load, so-called die bond (die bond) is to use binding agent or scolder by the back side tight bond of intelligent card chip wafer particle (die) (die bond) on the carrier band back side, then use lead key closing process, all generally to use gold thread binding (wire bond), finally use hot curing or ultraviolet ray to irradiate curing (UV) intelligent card chip wafer particle (die) and wiring are done to the sealing protection.Its flow process is as follows:

Intelligent card chip wafer (Wafer) attenuate → scribing → die bond (die bond) → Bonding (wire bond) → encapsulation (ultraviolet (UV) irradiates that glue makes that it solidifies, thermosetting technique all can) → test;

The difference of thermosetting and UV: as its name suggests, thermosetting is to realize the protection adhesive curing by heating, and UV realizes the protection adhesive curing by ultraviolet irradiation.

This method has occupied the main flow in market at present, and along with current gold cost and protection are risen with UV glue (UV glue) cost, packaging cost also climbs up and up.

Another kind method is referred to as FCOS (a kind of intelligent card chip method for packing that company of Infineon applies for a patent, Flip Chip on Substrate, FCOB), the method is by flip chip technology (fct) (face-down bonding technique), intelligent card chip particle (die) to be adhered to the back side of carrier band by conducting resinl or thermocompression bonding or hot sonic soldering.

Flip chip technology (fct) is not a kind of new technology, and it refers to the technological process that the semiconductor chip particle directly is connected with carrier band.At first this flow process will plant gold goal or other conductive salient points to the useful pad (PAD) of every the intelligent card chip particle (die) on intelligent card chip wafer (wafer), and the pad (PAD) that then intelligent card chip particle (die) upside-down mounting is made to it is towards carrier band.Pad on the carrier band circuit (PAD) is corresponding one by one with pad (PAD) position of the intelligent card chip particle (die) of long good salient point, and the pad (PAD) of above-mentioned (being between intelligent card chip particle die and carrier band) between the two can mechanically be bonded together by a kind of anisotropic conductivity viscose glue.

Flip chip technology (fct) can increase the density of device on carrier band, and with respect to existing Wire Bonding Technology (by the gold thread electric connection mode), and it is a kind ofly can save gold thread binding and protection glue, more direct, stable electric connection mode.Its main process is as follows:

Intelligent card chip wafer (Wafer) attenuate → scribing → salient point and UBM (a kind of packaging technology, under bump metal, projection bottom metal layer) processing → flip chip bonding (hot pressing or hot sonic soldering, but adding additives coordinates) → test;

After having experienced longer development, company of Infineon and German smart card manufacturer Giesecke& Devrient (G& D) successfully cooperation has been released the FCOS packaging technology of innovating and first flip chip technology (fct) has been applied to Intelligent card package.The FCOS technology encapsulates the intelligent card chip particle (die) in smart card module (with the circuit board of intelligent card chip) in the upside-down mounting mode.The function lining face of intelligent card chip particle (die) directly is connected with circuit board by flip chip bonding, no longer needs traditional spun gold and protection glue (UV glue) encapsulation, has saved the packaging cost of these two links.Owing in encapsulation, having saved metal wire, this new interconnection technique has been saved the module space in addition, and it can be in the situation that the larger intelligent card chip particle (die) of the constant arrangement of module size makes in smart card to add more function; Also can make the module size of smart card less.In addition, compare traditional gold thread binding technology, adopt the smart card of FCOS to have stronger mechanical stability and optical visual effect, less and thinner module size, stronger anti-corrosive properties and toughness, it has adopted non-halogen material, meets environment protection requirement.

The shortcoming of FCOS is that the equipment investment of Flip Chip Bond Technique is too high, and the coated metal of carrier band is had to specific (special) requirements, guarantee carrier band back side circuit coated metal must with wafer convex point on solder material welding, if gold-plated on carrier band, its thickness must be limited in 1-2um (micron), to limit the formation of fragile golden tin compound, so its whole production cost is very high.

The utility model content

The purpose of this utility model is to design a kind of new wafer particle, to overcome, adopts the wafer manufacturing smart card technology difficulty of prior art large, and equipment investment is high, the shortcoming that production cost is high.

Technical solutions of the utility model are as follows:

A kind of wafer particle, comprise multilevel integration and connected PAD point, it is characterized in that: the PAD point on said wafer particle is not less than 60um for diameter, be not more than 500um and between any two the distance of central point be not less than 100um, be not more than the circular PAD point of 2mm, or be not less than 60um for catercorner length, be not more than 500um and between any two the distance of central point be not less than 100um, be not more than rectangle or the square PAD point of 2mm, on the face that said wafer particle is ordered with PAD, except the PAD point, be provided with for the protection of wafer in the post-production process not by the insulating cover of short circuit or wearing and tearing.

Further, said PAD point is provided with copper alloy or aluminium alloy or the gilt watch surface layer that can be connected with tin or ashbury metal.

Further, on said wafer, any PAD point side is provided with the solder joint origin identification point that is conducive to follow-up SMT production.

The key difference of wafer particle described in the utility model and general wafer particle is that existing wafer particle PAD point is distributed in to upper and lower both sides, PAD point area and all less design of centre-to-centre spacing to be transformed, design area that PAD orders and PAD point all larger circle or the wafer particle PAD point of rectangle or foursquare novel layouts of the distance between central point in twos, be very easy to follow-up SMT production.

Adopt known wafer production technology just can complete production of the present utility model.Wafer particle of the present utility model (referring to Fig. 2, Fig. 3), the technique while being encapsulated as smart card can directly adopt carrier band or slide glass, carry out the carrier band encapsulation by paster technique (SMT), complete the production of smart card, therefore can greatly enhance productivity, reduce costs.

The accompanying drawing explanation

The utility model has following accompanying drawing (take ISSI IS23SC55160 wafer be example):

Fig. 1 has wafer schematic appearance (the smart card production technology that is suitable for existing costliness) now

Fig. 2 wafer schematic diagram of the present utility model

Fig. 3 the utility model wafer insulating barrier generalized section

Detailed description of main elements

101 is existing general wafer particle schematic diagram

102 is the solder joint on existing general wafer particle

301 is the utility model wafer particle schematic diagram

302 solder joints that are the utility model wafer particle

303 insulating barriers that are the utility model wafer particle

304 is chip welding spot origin identification point

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further detail.

The IS23SC55160 wafer 101 that Fig. 1 is traditional ISSI, its PAD point is distributed in upper and lower both sides, PAD is ordered is shaped as square PAD point 102, minimum spacing between the diagonal distance that this square PAD is ordered, PAD point is all less, this traditional wafer can only adopt lead key closing process or FCOS technique to be packaged into smart card, technique, equipment complexity, cost is high.

Fig. 2 is wafer 301 schematic diagrames of the utility model design, and its PAD point is circular PAD point 302, can be also rectangle or square PAD point.Circular PAD point on said wafer particle is not less than 60um, is not more than 500um for diameter, wherein, and 60,70,90,120,150,200,250,300,350,400,450,500um is the size that can select; Between the PAD point, the distance of central point is not less than 100um, is not more than 2mm in twos, wherein, 100,120,150,200,250,300,350,400,450,500,700,900um, and 1,1.2,1.5,1.8,2mm is the size that can select; Said rectangle or square PAD point catercorner length are not less than 60um, are not more than 500um, wherein, and 60,70,90,120,150,200,250,300,350,400,450,500um is the size that can select; Between the PAD point, the distance of central point is not less than 100um, is not more than 2mm in twos, wherein, 100,120,150,200,250,300,350,400,450,500,700,900um, and 1,1.2,1.5,1.8,2mm is the size that can select; For protect wafer in the post-production process not by short circuit or wearing and tearing, on the face that said wafer particle is ordered with PAD, the part except PAD point 302, be provided with insulating cover 303.In order to guarantee that subsequent handling carries out smoothly, said PAD point 302 is provided with copper alloy or aluminium alloy or the gilt watch surface layer that can be connected with tin or ashbury metal.Further, on said wafer, any PAD point side is provided with the solder joint origin identification point 304 that is conducive to follow-up SMT production; Also can adjust relative position and distance that a certain PAD point and other PAD are ordered, be beneficial to location in follow-up SMT production.

Adopt known wafer production technology just can complete the utility model.Technique when wafer particle of the present utility model is encapsulated as smart card can directly adopt carrier band or slide glass, by paster technique (SMT), carries out the carrier band encapsulation, completes the production of smart card, therefore can greatly enhance productivity, and reduces costs.

Fig. 3 is the utility model wafer insulating barrier generalized section, and on the front of wafer, the zone except the PAD point all covers insulating barrier.The protective layer that this insulating barrier can also be used as the crystal grain subsequent production, the remainder of avoiding wafer is outside exposed and potential risk occurs, for example, for the protection of wafer in the post-production process not by short circuit or wearing and tearing.

Claims

1. a wafer particle, comprise multilevel integration and connected PAD point, it is characterized in that: the PAD point on said wafer particle is not less than 60um for diameter, be not more than 500um and between any two the distance of central point be not less than 100um, be not more than the circular PAD point of 2mm, or be not less than 60um for catercorner length, be not more than 500um and between any two the distance of central point be not less than 100um, be not more than rectangle or the square PAD point of 2mm, on the face that said wafer particle is ordered with PAD, except the PAD point, be provided with for the protection of wafer in the post-production process not by the insulating cover of short circuit or wearing and tearing.

2. wafer particle as claimed in claim 1, is characterized in that said PAD point is provided with copper alloy or aluminium alloy or the gilt watch surface layer that can be connected with tin or ashbury metal.

3. wafer particle as claimed in claim 1 or 2, is characterized in that on said wafer, any PAD point side is provided with the solder joint origin identification point that is conducive to follow-up SMT production.