CN108447831B - Double-sided circuit wafer design and packaging method - Google Patents
Double-sided circuit wafer design and packaging method Download PDFInfo
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- CN108447831B CN108447831B CN201810240409.9A CN201810240409A CN108447831B CN 108447831 B CN108447831 B CN 108447831B CN 201810240409 A CN201810240409 A CN 201810240409A CN 108447831 B CN108447831 B CN 108447831B
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- 238000000034 method Methods 0.000 title claims abstract description 38
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- 230000001070 adhesive effect Effects 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 238000002161 passivation Methods 0.000 claims description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 12
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- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 6
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
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- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/742—Apparatus for manufacturing bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a double-sided circuit wafer design and packaging method. The method comprises the following steps: designing and manufacturing a wafer according to the double-sided circuit; and mounting the conducting element on the side surface, and packaging the wafer and the carrier plate. The double-sided circuit wafer design and packaging method is applied to the semiconductor chip process, and can reduce half of the design area, thereby greatly reducing the raw material cost; the circuit interference in the single-sided design can be effectively isolated; the two process flows of packaging patch and bonding wire can be simplified into one side-mounting flow, and packaging patch glue and bonding wire materials are omitted, so that the processing cost is reduced again; the side-mounted weldability is higher than that of the traditional welding wire, so that the stability of the performance is effectively maintained.
Description
Technical Field
The invention relates to wafer design, manufacture and packaging processing in the field of semiconductors, in particular to a double-sided circuit wafer design and packaging method.
Background
Semiconductor (semiconductor) refers to a material having conductivity between that of a conductor and an insulator at normal temperature. Semiconductors have wide applications in radios, televisions, and thermometry. Such as diodes, are devices fabricated using semiconductors. A semiconductor refers to a material whose conductivity can be controlled, ranging from an insulator to a conductor. The importance of semiconductors is enormous, both from a technological and an economic point of view. Most electronic products today, such as computers, mobile phones or digital recorders, have very close association with semiconductors. Common semiconductor materials are silicon, germanium, gallium arsenide, etc., and silicon is one of the most influential in commercial applications among various semiconductor materials.
The wafer is a carrier used for producing integrated circuits, and is a multi-finger monocrystalline silicon wafer, and also a compound wafer of gallium arsenide, silicon carbide, gallium nitride, indium phosphide and the like. In semiconductor manufacturing processes, the wafer is typically manufactured in a single-sided design. However, as the requirements for various functions are more and more high, the requirements for the integration density of the transistor are more and more high, and the integration density of the transistor is more and more challenging.
Semiconductor wafer design and packaging are largely dependent on wafer processing and packaging capabilities, with wafer single-sided designs typically being wafer-based single-sided growth circuits, and packaging processing being dependent on the design structure of the wafer.
Various methods are used to increase the integration density of transistors, and the improvement of the manufacturing and packaging processes of the wafer is one direction for solving the problem.
The invention is to integrate the wafer manufacturing process and the packaging processing capability, and select the wafer through hole process and the side packaging process to realize the change of the wafer single-sided circuit design into the double-sided design processing. The wafer design stage changes the traditional single-sided circuit and the bonding pads on the periphery into double-sided circuit wafer design, and the double-sided bonding pads are positioned on the same side edge of the wafer, and the internal circuit is realized through a through hole process. Thereby realizing the high-integration and low-density design and manufacture of the wafer function.
Disclosure of Invention
In order to improve the process of designing and manufacturing a semiconductor wafer, reduce the volume, reduce the cost, isolate the interference and other purposes, the invention aims to provide a double-sided circuit wafer designing and packaging method, which is applied to the related fields of various semiconductor functional devices according to various substrate materials such as wafer compounds or monocrystalline silicon and the like and the processing capacity, and extends the circuit design area under the condition that the wafer integration process capacity is unchanged, thereby saving the consumption cost of semiconductor materials.
The invention provides a double-sided circuit wafer design and packaging method, which comprises the following steps:
Step S1, designing and manufacturing a wafer according to a double-sided circuit;
And S2, mounting a conducting element on the side surface, packaging the wafer and the carrier plate.
Further, in step S1, the surface pads of the double-sided circuit are designed on the same side and are arranged near the edge of one side, the pad pitch is greater than or equal to 60um, and the pad length is greater than or equal to 50um.
Further, in step S1, the thickness of the wafer is 200um to 300um; the width of the wafer is 300-500 um; the length of the wafer is 750 um-1000 um.
Further, in step S1, the two-sided circuits are connected in an inline manner through a through hole; when the double-sided circuit is manufactured, a double-sided synchronous processing technology is selected or a step-by-step single-sided processing technology is selected according to the difference of functional requirements.
Further, the manufacturing method of the double-sided circuit wafer comprises the following steps:
s11, a wafer with the thickness of 750um or 675um is selected as the monocrystalline silicon or compound substrate;
s12, grinding the thickness of the wafer to the packaging side mounting standard;
s13, dry etching the double-sided alignment holes by using chlorine-containing or fluorine-containing gas;
s14, processing an inner layer circuit by using the processes of implantation doping, pattern photoetching plate making, epitaxial growth and metallization layer precipitation interconnection;
S15, manufacturing double-sided surface metal and a passivation layer, electroplating a surface metal layer, and sputtering a titanium layer before electroplating;
S16, through holes, wherein the monocrystalline silicon substrate is dry-etched by fluorine-containing gas, and the compound substrate is dry-etched by chlorine-containing gas;
S17, sputtering a layer of titanium-containing metal base on the passivation layer on the surface of the wafer after the through hole, coating a photosensitive film, exposing, developing and selectively etching a top-layer circuit groove to expose the titanium-containing metal base, electroplating surface metal gold or aluminum element, and etching a residual photosensitive film and an excessive titanium layer;
s18, covering a passivation layer on the surface layer of the wafer, and exposing the metal bonding pad through the passivation layer;
s19, cutting the crystal grains.
Further, in step S2, the method for mounting the conductive element on the side surface and packaging the die and the carrier includes the following steps:
s21, manufacturing a carrier plate of the packaging side-mounted package according to the windowing position and the size of a bonding pad of a wafer, wherein the bonding pad design of the carrier plate is required to be consistent with the bonding pad size and the spacing of the wafer;
s22, heating, baking, solidifying and welding the wafer and the bonding pad of the carrier plate by using a conductive adhesive oven, dispensing conductive adhesive on the bonding pad at the joint of the carrier plate and the wafer, rotating the wafer by 90 degrees through packaging side mounting equipment, mounting the wafer on the windowed surface of the bonding pad of the carrier plate after dispensing, adsorbing the conductive adhesive by capillary effect, quickly conducting the bonding pad of the carrier plate and the bonding pad of the wafer, and transmitting the conductive adhesive to a high-temperature oven for baking to solidify the conductive adhesive;
s23, after being conducted with the carrier plate and solidified, the packaging is completed, and a terminal element product is obtained.
Further, in step S22, solder reflow soldering may be further selected, a solder paste printing screen is manufactured according to the design of the wafer bonding pad and the carrier bonding pad, the window opening size of the screen is kept consistent with the window opening size of the carrier bonding pad, the solder paste is printed on the carrier metal bonding pad through the steel mesh, the wafer is rotated by 90 degrees through the packaging side mounting equipment, the solder paste is liquefied through the temperature rising area and the heat preservation area of the reflow oven, the carrier bonding pad is conducted with the bonding pad of the wafer by utilizing the capillary effect, and after the side mounting is completed, the solder paste is conveyed to the reflow oven for reflow and resolidification.
The invention also provides a double-sided circuit wafer which is characterized by comprising a carrier plate and a wafer, wherein the wafer comprises a substrate, a first surface circuit, a second surface circuit, a side surface, a top surface and a conducting element, and the double-sided circuit wafer comprises the following components:
The carrier plate is encapsulated with the substrate and is used for bearing the wafer;
The substrate is encapsulated on the carrier plate and is the bottom surface of the wafer;
The first surface circuit is connected with the substrate and is used for designing and manufacturing a wafer circuit;
The second surface circuit is connected with the substrate and is used for designing and manufacturing a wafer circuit, and the second surface circuit is opposite to the first surface circuit and realizes the interconnection conduction through a through hole;
the side surface is connected with the substrate, the first surface circuit, the second surface circuit and the top surface and is used for installing a conducting element;
the top surface is connected with the first surface circuit, the second surface circuit and the side surface and is the top surface of the wafer;
The conducting element is arranged on the side face and used for forming a wafer circuit.
Further, one end of the metal terminal of the conducting element is welded on the bonding pad on the first surface circuit or the second surface circuit, the other end of the metal terminal is welded on the bonding pad of the carrier plate, the bonding pad distance is more than or equal to 60um, and the bonding pad length is more than or equal to 50um.
Further, the thickness of the wafer is 200-300 um; the width of the wafer is 300-500 um; the length of the wafer is 750 um-1000 um.
The invention has the following beneficial effects:
By integrating the wafer manufacturing process and the packaging processing capability, the effective area of the wafer manufacturing process can be reduced by half, so that the raw material cost is greatly reduced; the circuit interference in the single-sided design can be effectively isolated; the two process flows of packaging patch and bonding wire can be simplified into one side-mounting flow, and packaging patch glue and bonding wire materials are omitted, so that the processing cost is reduced again; the side-mounted weldability is higher than that of the traditional welding wire, so that the stability of the performance is effectively maintained.
Drawings
FIG. 1 is a schematic diagram of the design and package integration of the present invention.
Fig. 2 is a schematic diagram of a pad design of the present invention.
FIG. 3 is a schematic diagram of a wafer design process according to the present invention.
FIG. 4 is a schematic diagram of a die package process according to the present invention.
Detailed Description
The following detailed description of specific embodiments of the invention is provided in connection with the accompanying drawings and examples in order to provide a better understanding of the aspects of the invention and advantages thereof. However, the following description and examples are for illustrative purposes only and are not intended to limit the invention to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications and alternatives falling within the spirit and scope of the invention. The drawings of the present invention are merely schematic illustrations, and are not intended to be drawn to actual dimensions.
A double-sided circuit wafer is shown in FIG. 3, and FIG. 3 is a schematic diagram of the wafer design process of the present invention. The chip comprises a carrier 1 and a chip 2, wherein the chip 2 comprises a substrate 21, a first surface circuit 22, a second surface circuit 23, a first side 24, a second side 25, a top 26 and a conducting element (not shown), and the chip comprises: the carrier 1 is encapsulated with the substrate 21 and is used for carrying the wafer 2; the substrate 21 is encapsulated on the carrier 1 and is the bottom surface of the wafer 2; the first surface circuit 22 is connected with the substrate 21 and is used for designing and manufacturing a wafer circuit; the second surface circuit 23 is connected to the substrate 21 for designing and manufacturing a wafer circuit, the second surface circuit 23 is opposite to the first surface circuit 22, and the interconnection conduction is realized through the through hole 27; the first side 24 is connected 26 to the substrate 21, the first surface circuit 22, the second surface circuit 23, and the top surface for mounting conductive elements; the second side 25 is connected to the substrate 21, the first surface circuit 22, the second surface circuit 23, and the top surface 26 for mounting conductive elements; the top surface 26 is connected to the first surface circuit 22, the second surface circuit 23, the first side surface 24, and the second side surface 25, and is the top surface 26 of the wafer 2; the conducting element is mounted on the first side 24 and the second side 25, and is used for forming a wafer circuit.
A double-sided circuit wafer design and packaging method is shown in FIG. 1, FIG. 1 is a schematic diagram of the design and packaging integration of the present invention. The main technology involved from design to die mounting to packaging is embodied in its entirety. The specific embodiment comprises the following steps.
Step S1, designing and manufacturing the wafer according to the double-sided circuit.
In the prior art, the wafer is designed into a single-sided circuit, the bonding pads are positioned on the periphery, the wafer is designed according to a double-sided circuit, the double-sided bonding pads are positioned on the same side edge of the wafer, and the internal circuit is realized through a through hole process. Thereby realizing the high-integration and low-density design and manufacture of the wafer function.
As shown in fig. 2, fig. 2 is a schematic diagram of a pad design of the present invention, the surface pads 28 of the first surface circuit 22 and the second surface circuit 23 of the die are designed on the same side and are arranged near one side edge, the distance between the pads 281 and 282 is not less than 60um (micrometers), and the length of the pad 28 is not less than 50um, for example, the pad 281 and the pad 282 are shown, so that the problem of short circuit of the subsequent Cheng Fengzhuang side package can be effectively avoided by the design of a green oil window of the substrate and the coating of non-conductive adhesive.
The thickness of the wafer 2 is more than or equal to 200um and is limited to the best size of the side-mounted suction nozzle in the current packaging, the thickness of the wafer 2 is less than or equal to 300um and is limited to the best size of the through-hole process, the width of the wafer 2 is more than or equal to 300um and is limited to the anti-die-flow impact stability of the side-mounted wafer in consideration of the effective area utilization rate of the wafer, the width of the wafer 2 is less than or equal to 500um and is more suitable for large-area wafer products due to the fact that the bottleneck of the through-hole process of the wafer is or is widened along with the improvement of the technology and the packaging process is further enhanced.
Therefore, the thickness and width of the wafer 2 are as follows: the width of the wafer 2 is 300 um-500 um, the thickness of the wafer 2 is 200 um-300 um, and the length of the wafer 2 is 750 um-1000 um.
When the double-sided circuit is processed, a double-sided synchronous processing technology is preferably selected to improve the manufacturing efficiency, but a step-by-step single-sided processing technology can also be selected according to the actual function requirement difference.
The manufacturing method of the double-sided circuit wafer comprises the following steps.
S11, a wafer with the thickness of 750um or 675um is selected as the monocrystalline silicon or compound substrate, and the wafer size is divided into 6 inches, 8 inches and 12 inches.
S12, grinding the thickness of the wafer to the packaging side mounting standard; 200um to 300um. The vacuum opening of the packaging side-mounted suction nozzle is smaller than 200um, so that the manufacturing is difficult, and the general suction nozzle has the problem of air leakage and cannot suck or firmly suck grains. When the die is higher than 300um, the die is overweight, the vacuum suction of the package is insufficient, the problem that the die cannot be sucked or falls before the chip is stuck is caused, and the design of the package integration space is not facilitated due to the too thick die; the crystal grain is cut by laser based on part of the substrate material, the thickness of the crystal wafer is not easy to be too thick, for example, the gallium arsenide crystal wafer can be finished only by three lasers on the double-sided cutting channels when the thickness is 300 um; the higher the laser temperature, the longer the stay time at the same position, the deeper the cutting, the higher the heat, and the easy burning of the wafer.
S13, the circuit processing can select partial process double-sided circuits to be synchronously manufactured according to the process difference, and at the moment, the double-sided alignment holes are required to be dry-etched by using chlorine-containing or fluorine-containing gas before circuit manufacturing, so that the alignment of the manufacturing positions of the double-sided circuits is facilitated.
S14, processing an inner layer circuit by using an in-industry mature process such as transistor structure modes of PN junction, heterojunction, MOS field effect and the like, and processes of common oxide film preparation, diffusion or ion implantation doping, graphic photoetching plate making, epitaxial growth, metallization layer precipitation interconnection and the like according to the functions and design requirements of the double-sided wafer.
S15, manufacturing double-sided surface metal and a passivation layer, and electroplating a surface metal layer such as gold and aluminum metal after the internal circuit layer, the dielectric layer and the passivation layer are finished; a titanium layer is required to be sputtered before electroplating, so that the combination of metal and a passivation layer is facilitated.
S16, if the double-sided circuit is required to be connected in an internal mode, the aperture of a through hole and the size of a hole disc are required to be reserved in the initial design of the wafer circuit; the via process is typically performed after the completion of the inner layer circuitry, and monocrystalline silicon substrates are typically dry etched with fluorine-containing gases and compound substrates are typically dry etched with chlorine-containing gases.
And S17, sputtering a layer of titanium-containing metal base on the passivation layer on the surface of the wafer after the through hole, coating a photosensitive film, exposing, developing and selectively etching a top-layer circuit groove to expose the titanium-containing metal base, electroplating surface metal gold or aluminum element, and etching the residual photosensitive film and the redundant titanium layer.
S18, covering a passivation layer on the surface layer of the wafer, and exposing the metal bonding pad through the passivation layer; can effectively protect the thin circuit of the wafer from damage and prevent the circuit from oxidation, and the mask is composed of organic components and has the property of being oil-proof.
S19, cutting the crystal grains, wherein a cutting knife is generally selected for cutting the monocrystalline silicon substrate crystal cells, the width of cutting channels among the crystal grains is generally reserved to 80um, and partial crystal cells containing a low dielectric layer can be cooperatively cut by adopting a laser mode and a cutting knife mode; the compound substrate wafer is usually cut by laser, the width of the cutting channel is usually between 40um and 60um, and the thicker the substrate, the more laser cutting times are.
Step S2, side mounting a conducting element, packaging a wafer and a carrier plate, comprising the following steps.
S21, manufacturing a packaging-side-mounted carrier plate 1, such as a printed circuit board, a frame and the like, according to the windowing position and the size of the bonding pads 28 of the wafer 2, wherein the bonding pads 11 of the carrier plate are required to be designed to be consistent with the size and the spacing of the bonding pads 28 of the wafer 2.
As shown in fig. 4, fig. 4 is a schematic view of a die package process according to the present invention. The metal terminals of the conductive elements are soldered at one end to the pads 28 on the first surface circuit 22 or the second surface circuit 23 and at the other end to the pads 11 of the carrier plate 1.
S22, the bonding pad 28 of the wafer 2 and the bonding pad 11 of the carrier plate 1 can be heated, baked, cured and welded by a conductive adhesive oven, the bonding pad point conductive adhesive at the joint of the carrier plate 1 and the wafer 2 is rotated by 90 degrees through packaging side mounting equipment and is arranged on the windowed surface of the dotted bonding pad 11 of the carrier plate, the wafer patch position needs to enable one side of the bonding pad 28 of the wafer to be attached to the corresponding position of the dotted conductive adhesive, the conductive adhesive is adsorbed by capillary effect, the bonding pad of the carrier plate and the bonding pad of the wafer are quickly conducted, and the bonding pad is transmitted to a high-temperature oven to be baked and cured.
S23, after being conducted with the carrier plate 1 and solidified, the packaging is completed, and a terminal element product is obtained.
In step S22, solder paste is optionally reflowed, a solder paste printing screen is designed and manufactured according to the wafer pad 28 and the carrier pad 11, the window size of the screen is consistent with the window size of the carrier pad 11, the solder paste 3 is printed on the carrier pad 11 through a steel mesh, the wafer is rotated by 90 degrees through packaging side-mounting equipment, the solder paste 3 is liquefied through a reflow oven heating area and a heat preservation area, the carrier pad 11 is conducted with the pad 28 of the wafer by utilizing capillary effect, after side-mounting is completed, the solder paste is transmitted to the reflow oven for reflow and resolidification, and the reflow soldering process connects the wafer pad 28 with the carrier pad 11, so that the wafer 2 and the carrier 1 are conducted mutually and the wafer is fixed. In step S22, the chip mounting is performed such that the die pad 28 is attached to the corresponding position by printing solder paste or conductive paste.
It should be noted that the above embodiments described above with reference to the drawings are only for illustrating the present invention and not for limiting the scope of the present invention, and it should be understood by those skilled in the art that modifications or equivalent substitutions to the present invention are intended to be included in the scope of the present invention without departing from the spirit and scope of the present invention. Furthermore, unless the context indicates otherwise, words occurring in the singular form include the plural form and vice versa. In addition, unless specifically stated, all or a portion of any embodiment may be used in combination with all or a portion of any other embodiment.
Claims (9)
1. A double-sided circuit wafer design and packaging method comprises the following steps:
Step S1, designing and manufacturing a wafer according to a double-sided circuit, wherein the step comprises the following steps:
s11, a wafer with the thickness of 750um or 675um is selected as the monocrystalline silicon or compound substrate;
s12, grinding the thickness of the wafer to the packaging side mounting standard;
s13, dry etching the double-sided alignment holes by using chlorine-containing or fluorine-containing gas;
s14, processing an inner layer circuit by using the processes of implantation doping, pattern photoetching plate making, epitaxial growth and metallization layer precipitation interconnection;
S15, manufacturing double-sided surface metal and a passivation layer, electroplating a surface metal layer, and sputtering a titanium layer before electroplating;
S16, through holes, wherein the monocrystalline silicon substrate is dry-etched by fluorine-containing gas, and the compound substrate is dry-etched by chlorine-containing gas;
S17, sputtering a layer of titanium-containing metal base on the passivation layer on the surface of the wafer after the through hole, coating a photosensitive film, exposing, developing and selectively etching a top-layer circuit groove to expose the titanium-containing metal base, electroplating surface metal gold or aluminum element, and etching a residual photosensitive film and an excessive titanium layer;
s18, covering a passivation layer on the surface layer of the wafer, and exposing the metal bonding pad through the passivation layer;
S19, cutting grains;
And S2, mounting a conducting element on the side surface, packaging the wafer and the carrier plate.
2. The method for designing and packaging a double-sided circuit die according to claim 1, wherein in step S1, the surface pads of the double-sided circuit are designed on the same side and are arranged near one side edge, the pad pitch is equal to or greater than 60um, and the pad length is equal to or greater than 50um.
3. The method for designing and packaging a double-sided circuit wafer according to claim 1, wherein in the step S1, the thickness of the wafer is 200um to 300um; the width of the wafer is 300-500 um; the length of the wafer is 750 um-1000 um.
4. The method for designing and packaging double-sided circuit die as claimed in claim 1, wherein in step S1, the double-sided circuits are connected in series through vias; when the double-sided circuit is manufactured, a double-sided synchronous processing technology is selected or a step-by-step single-sided processing technology is selected according to the difference of functional requirements.
5. The method of designing and packaging a double-sided circuit die as claimed in claim 1, wherein in step S2, the method of mounting the conductive element on the side and packaging the die and the carrier comprises the steps of:
s21, manufacturing a carrier plate of the packaging side-mounted package according to the windowing position and the size of a bonding pad of a wafer, wherein the bonding pad design of the carrier plate is required to be consistent with the bonding pad size and the spacing of the wafer;
s22, heating, baking, solidifying and welding the wafer and the bonding pad of the carrier plate by using a conductive adhesive oven, dispensing conductive adhesive on the bonding pad at the joint of the carrier plate and the wafer, rotating the wafer by 90 degrees through packaging side mounting equipment, mounting the wafer on the windowed surface of the bonding pad of the carrier plate after dispensing, adsorbing the conductive adhesive by capillary effect, quickly conducting the bonding pad of the carrier plate and the bonding pad of the wafer, and transmitting the conductive adhesive to a high-temperature oven for baking to solidify the conductive adhesive;
s23, after being conducted with the carrier plate and solidified, the packaging is completed, and a terminal element product is obtained.
6. The method for designing and packaging double-sided circuit wafer according to claim 5, wherein in step S22, solder reflow soldering is also selected, a solder paste printing screen is manufactured according to the wafer pad and the carrier pad design, the screen window size is kept consistent with the carrier pad window size, the solder paste is printed on the carrier metal pad through a steel screen, the wafer is rotated by 90 degrees through packaging side mounting equipment, the solder paste is liquefied through a reflow oven heating area and a heat preservation area, the carrier pad is conducted with the pad of the wafer by utilizing capillary effect, and after side mounting is completed, the wafer is conveyed to a reflow oven for reflow and resolidification.
7. The utility model provides a two-sided circuit wafer which characterized in that includes carrier plate, wafer, the wafer includes base, first surface circuit, second surface circuit, side, top surface, conduction component, wherein:
The carrier plate is encapsulated with the substrate and is used for bearing the wafer;
The substrate is encapsulated on the carrier plate and is the bottom surface of the wafer;
The first surface circuit is connected with the substrate and is used for designing and manufacturing a wafer circuit;
The second surface circuit is connected with the substrate and is used for designing and manufacturing a wafer circuit, and the second surface circuit is opposite to the first surface circuit and realizes the interconnection conduction through a through hole;
the bonding pads of the first surface circuit and the second surface circuit are designed on the same side and are arranged close to the edge of one side, the bonding pad distance is more than or equal to 60um, and the bonding pad length is more than or equal to 50um;
The side surface is connected with the substrate, the first surface circuit, the second surface circuit and the top surface and is used for installing the conducting element;
the top surface is connected with the first surface circuit, the second surface circuit and the side surface and is the top surface of the wafer;
The conducting element is arranged on the side face and used for forming a wafer circuit.
8. The double-sided circuit die of claim 7, wherein the metal terminals of the pass-through element are soldered at one end to pads on the first surface circuit or the second surface circuit and at the other end to carrier pads.
9. The double-sided circuit die of claim 7, wherein the die has a thickness of 200um to 300um; the width of the wafer is 300-500 um; the length of the wafer is 750 um-1000 um.
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| CN201810240409.9A CN108447831B (en) | 2018-03-22 | 2018-03-22 | Double-sided circuit wafer design and packaging method |
| PCT/CN2018/104463 WO2019179060A1 (en) | 2018-03-22 | 2018-09-07 | Method for designing and packaging two surface circuit die |
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| CN201810240409.9A CN108447831B (en) | 2018-03-22 | 2018-03-22 | Double-sided circuit wafer design and packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108447831B (en) * | 2018-03-22 | 2024-05-07 | 上海飞骧电子科技有限公司 | Double-sided circuit wafer design and packaging method |
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| JP2002198463A (en) * | 2000-12-26 | 2002-07-12 | Canon Inc | Chip size package and its manufacturing method |
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| CN108447831A (en) | 2018-08-24 |
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