CN203218253U - MSOP10 integrated circuit packaging lead frame structure - Google Patents

MSOP10 integrated circuit packaging lead frame structure Download PDF

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Publication number
CN203218253U
CN203218253U CN 201320117487 CN201320117487U CN203218253U CN 203218253 U CN203218253 U CN 203218253U CN 201320117487 CN201320117487 CN 201320117487 CN 201320117487 U CN201320117487 U CN 201320117487U CN 203218253 U CN203218253 U CN 203218253U
Authority
CN
China
Prior art keywords
lead frame
msop10
integrated circuit
frame structure
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN 201320117487
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Chinese (zh)
Inventor
刘兴波
梁大钟
施保球
饶锡林
石艳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHINA CHIPPACKING TECHNOLOGY Co Ltd
Original Assignee
CHINA CHIPPACKING TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHINA CHIPPACKING TECHNOLOGY Co Ltd filed Critical CHINA CHIPPACKING TECHNOLOGY Co Ltd
Priority to CN 201320117487 priority Critical patent/CN203218253U/en
Application granted granted Critical
Publication of CN203218253U publication Critical patent/CN203218253U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model aims at providing an MSOP10 integrated circuit packaging lead frame structure being higher in packaging efficiency and saving more cost. The lead frame structure comprises a substrate and multiple lead frame units, wherein the lead frame units are uniformly arranged on the substrate in rows, and each row includes ten lead frame units. According to the utility model, working efficiency is greatly improved, labor cost is greatly reduced, consumption of power and resin can be effectively reduced, technical effect is obvious, and the MSOP10 integrated circuit packaging lead frame structure is suitable for packaging of integrated circuits.

Description

A kind of lead frame structure of MSOP10 integrated circuit encapsulation
Technical field
The utility model relates to the lead frame structure of integrated circuit encapsulation, is specifically related to a kind of MSOP10 integrated circuit package leadframe shelf structure.
Background technology
Must use lead frame structure during the integrated circuit encapsulation, existing MSOP10 package lead mount structure, since be subjected to before skill state limit, one row can only arrange five lead frames at most, can adorn 140 circuit on a slice MSOP10 package lead mount structure, every mould can seal eight MSOP10 package lead mount structures at most, and every like this mould can go out 1120 in circuit at most, thereby efficient has much room for improvement.Because chip encapsulation has been tending towards meagre profitization, therefore how improves packaging efficiency, save cost and become inevitable problem.Therefore, existing MSOP10 package lead mount structure can not satisfy the demands, and needs to improve.
Summary of the invention
It is that the lead frame that overcomes the integrated circuit encapsulation of existing skill in stating exists the low skill of production efficiency and states defective that skill of the present utility model is stated purpose, provide a kind of packaging efficiency higher, more save the lead frame structure of the MSOP10 integrated circuit encapsulation of cost.
For realizing that above skill states purpose, skill of the present utility model is stated scheme and is
A kind of lead frame structure of MSOP10 integrated circuit encapsulation comprises substrate and some lead frames unit, and per ten of described lead frame unit are a row, are divided into some rows and evenly are located on the described substrate.
Further, per two rows in described lead frame unit are one group, are divided into some groups and are arranged on the described substrate.
Further, described lead frame unit has 20 groups, and proper alignment is on described substrate.
Useful skill of the present utility model is stated effect and is: because every row is provided with ten lead frame unit, compare the MSOP10 package lead mount structure of existing five row's structures, production efficiency improves greatly, thereby greatly reduces cost of labor; With advancing also can effectively reduce the consumption of power consumption and resin, thus skill to state effect obvious.
Description of drawings
Fig. 1 is the structural representation of an embodiment of the utility model.
Embodiment
In conjunction with Fig. 1, the lead frame structure of a kind of MSOP10 integrated circuit encapsulation of the utility model comprises substrate 1 and some lead frames unit 2, and 2 per ten of described lead frame unit are a row, are divided into some rows and evenly are located on the described substrate 1.In force, lead frame unit 2 per two rows are one group, are divided into some groups and are arranged on the described substrate 1.Better, described lead frame unit has 20 groups, and proper alignment is on described substrate, and in force, each lead frame unit namely is packaged into an independently integrated circuit.The A place is the partial schematic diagram of lead frame among the figure.
MSOP10 package leadframe structure Design, the main arrangement problems that will solve exactly between a few row's circuit should reduce circuit paging effective area as far as possible, thereby saves copper material, the reliability when considering the whole piece circuit package again.MSOP10 package lead mount structure comprises the substrate 1 of a rectangle as shown in Figure 1, and is arranged in the some lead frames unit 2 on the substrate 1.And clearly visible by Fig. 1,2 per ten of lead frame unit are a row.Per two row lead frame unit 2 are one group.
On a MSOP10 package lead mount structure, be placed with 20 batch totals, 40 row lead frame unit 2 in whole base plate 1, the every structural lead frame of MSOP10 package leadframe unit 2 amounts to 400 like this, can adorn 400 circuit.And every mould can go out 8 MSOP10 package lead mount structures, can go out the circuit number and reach 3200, compare the MSOP10 package lead mount structure of existing 5 row's structures, production efficiency improves 186%, thereby greatly reduce cost of labor, with advancing also can effectively reduce the consumption of power consumption and resin, thus skill to state effect obvious.
The production efficiency that improved of the present utility model, and reduced cost of labor; With advancing also can effectively reduce the consumption of power consumption and resin, be one of this area not only practical but also novel skill state improvement.

Claims (3)

1. the lead frame structure of a MSOP10 integrated circuit encapsulation comprises substrate and some lead frames unit, and it is characterized in that: per ten of described lead frame unit are a row, are divided into some rows and evenly are located on the described substrate.
2. the lead frame structure of a kind of MSOP10 integrated circuit encapsulation according to claim 1, it is characterized in that: per two rows in described lead frame unit are one group, are divided into some groups and are arranged on the described substrate.
3. the lead frame structure of a kind of MSOP10 integrated circuit encapsulation according to claim 2, it is characterized in that: described lead frame unit has 20 groups, and proper alignment is on described substrate.
CN 201320117487 2013-03-15 2013-03-15 MSOP10 integrated circuit packaging lead frame structure Expired - Lifetime CN203218253U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201320117487 CN203218253U (en) 2013-03-15 2013-03-15 MSOP10 integrated circuit packaging lead frame structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201320117487 CN203218253U (en) 2013-03-15 2013-03-15 MSOP10 integrated circuit packaging lead frame structure

Publications (1)

Publication Number Publication Date
CN203218253U true CN203218253U (en) 2013-09-25

Family

ID=49207766

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201320117487 Expired - Lifetime CN203218253U (en) 2013-03-15 2013-03-15 MSOP10 integrated circuit packaging lead frame structure

Country Status (1)

Country Link
CN (1) CN203218253U (en)

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20130925

CX01 Expiry of patent term