CN203553142U - Matrix array minidip lead frame - Google Patents
Matrix array minidip lead frame Download PDFInfo
- Publication number
- CN203553142U CN203553142U CN201320599416.0U CN201320599416U CN203553142U CN 203553142 U CN203553142 U CN 203553142U CN 201320599416 U CN201320599416 U CN 201320599416U CN 203553142 U CN203553142 U CN 203553142U
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- Prior art keywords
- lead frame
- minidip
- unit
- lead
- frame
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Abstract
The utility model discloses a semiconductor packaging lead frame of the microelectronic production field, to be specific, discloses a matrix array MINIDIP lead frame constituted by a lead frame, a plurality of unit lead frames disposed in the lead frame. The matrix array MINIDIP lead frame is characterized in that the unit lead frames are disposed on the frame in a matrix-type arrangement; the lead frame is constituted by an upper piece lead frame and a lower piece lead frame; outer lead pins of the unit lead frames of the upper piece lead frame and the lower piece lead frame are in a staggered arrangement, and are connected with the side frames of the frame by grids. The matrix array MINIDIP lead frame has advantages of simple structure, reliable technology, and abilities of reducing number of copper frames and reducing costs.
Description
Technical field
The utility model relates to the lead frame of a kind of semiconductor packages of microelectronics production field, specifically for a kind of rectangular array MINIDIP lead frame.
Background technology
The series of DIP encapsulation is early development lead frame pattern out, at that time because being subject to the impact of lead frame rolled copper foil manufacturing technology, diel and stamping technology, encapsulation aspect is subject to plastic package die, electroplates the restriction of selecting coating technology, cutting the conditions such as the accuracy of identification of muscle shaping dies technology, upper core/pressure welding device and operation window scope, lead frame generally designs the width in loam mono-30mm, be double or single design, every 10-20 unit are not etc.List/double DIP series of products belong to people intensive encapsulating products at present, have that production efficiency is low, stock utilization is low, course of processing error rate is high, use equipment is many, cause the problems such as floor space is large, energy resource consumption is large, the manual processing mold security risk of DIP is large, it is five chips that MINIDIP bridge is used framework while producing, and the overlapping series connection of chip again parallel connection is combined into rectifier bridge; After body encapsulation, thickness reaches 2.5mm; Required copper framework cost is higher.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, and a kind of rectangular array MINIDIP lead frame that adopts is provided, and chip plane arrangement mode is produced, and can effectively reduce the thickness after encapsulation, and reduce the cost of copper framework.
The utility model is achieved through the following technical solutions:
A kind of rectangular array MINIDIP lead frame, by lead frame and several unit lead frames of being located in lead frame, formed, it is characterized in that: described unit lead frame is matrix form and arranges on described framework, lead frame is comprised of upper slice lead frame and lower lead frame, unit lead frame in fluctuating plate lead frame is outer lead pin and is staggered, and is connected with described framework border by grizzly bar; Described lead wire unit framework is that two carrier structures are that each unit lead frame has two carriers, and the pin of unit lead frame is connected with carrier; Unit lead frame in described lead frame consists of 18 row 10 row; The carrier of the unit lead frame on upper slice lead frame is placed first, second IC chip, and the carrier of the unit lead frame on lower lead frame is placed the 3rd, the 4th IC chip.
The utility model compared with prior art has following beneficial effect:
1. frame structure is simple, process;
2. reduced copper framework, reduced costs.
Accompanying drawing explanation
Fig. 1 is rectangular array MINIDIP lead frame structure figure;
Fig. 2 is unit lead frame connection layout;
Fig. 3 is rectifier bridge electrical schematic diagram.
In figure: lead frame 1, unit lead frame 2, chip carrier 3 and lead-in wire 4.
Embodiment
Below in conjunction with accompanying drawing, content of the present utility model is further described:
Be illustrated in figure 1 rectangular array MINIDIP lead frame structure figure, upper and lower two lead frames, consist of, it is five chips that old MINIDIP bridge is used framework while producing, and the overlapping series connection of chip again parallel connection is combined into rectifier bridge; After body encapsulation, thickness reaches 2.5mm; Required copper framework cost is higher; The new mode of production adopts rectangular array, chip plane arrangement mode to produce, and thickness can be reduced to 1.4mm.
Lead frame of the present utility model consists of several unit lead frames that are located in lead frame, described unit lead frame is matrix form and arranges on described framework, lead frame is comprised of upper slice lead frame and lower lead frame, unit lead frame in fluctuating plate lead frame is outer lead pin and is staggered, and is connected with described framework border by grizzly bar; Described lead wire unit framework is that two carrier structures are that each unit lead frame has two carriers, and the pin of unit lead frame is connected with carrier; Unit lead frame in described lead frame consists of 18 row 10 row; The carrier of the unit lead frame on upper slice lead frame is placed first, second IC chip, and the carrier of the unit lead frame on lower lead frame is placed the 3rd, the 4th IC chip.
Claims (4)
1. a rectangular array MINIDIP lead frame, by lead frame and several unit lead frames of being located in lead frame, formed, it is characterized in that: described unit lead frame is matrix form and arranges on described framework, lead frame is comprised of upper slice lead frame and lower lead frame, unit lead frame in fluctuating plate lead frame is outer lead pin and is staggered, and is connected with described framework border by grizzly bar.
2. rectangular array MINIDIP lead frame according to claim 1, is characterized in that: described unit lead frame is that two carrier structures are that each unit lead frame has two carriers, and the pin of unit lead frame is connected with carrier.
3. rectangular array MINIDIP lead frame according to claim 1, is characterized in that: the unit lead frame in lead frame consists of 18 row 10 row.
4. rectangular array MINIDIP lead frame according to claim 1, it is characterized in that: the carrier of the unit lead frame on upper slice lead frame is placed first, second IC chip, the carrier of the unit lead frame on lower lead frame is placed the 3rd, the 4th IC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320599416.0U CN203553142U (en) | 2013-09-27 | 2013-09-27 | Matrix array minidip lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320599416.0U CN203553142U (en) | 2013-09-27 | 2013-09-27 | Matrix array minidip lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203553142U true CN203553142U (en) | 2014-04-16 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320599416.0U Expired - Fee Related CN203553142U (en) | 2013-09-27 | 2013-09-27 | Matrix array minidip lead frame |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203553142U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103474412A (en) * | 2013-09-27 | 2013-12-25 | 如皋市易达电子有限责任公司 | Rectangular array MINIDIP lead frame |
| CN105185765A (en) * | 2015-09-28 | 2015-12-23 | 宁波港波电子有限公司 | Array high-density lead frame and method |
-
2013
- 2013-09-27 CN CN201320599416.0U patent/CN203553142U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103474412A (en) * | 2013-09-27 | 2013-12-25 | 如皋市易达电子有限责任公司 | Rectangular array MINIDIP lead frame |
| CN105185765A (en) * | 2015-09-28 | 2015-12-23 | 宁波港波电子有限公司 | Array high-density lead frame and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140416 Termination date: 20150927 |
|
| EXPY | Termination of patent right or utility model |