CN204315555U - A kind of chip high efficiency encapsulating structure - Google Patents
A kind of chip high efficiency encapsulating structure Download PDFInfo
- Publication number
- CN204315555U CN204315555U CN201420781137.0U CN201420781137U CN204315555U CN 204315555 U CN204315555 U CN 204315555U CN 201420781137 U CN201420781137 U CN 201420781137U CN 204315555 U CN204315555 U CN 204315555U
- Authority
- CN
- China
- Prior art keywords
- chip
- encapsulation
- type
- support body
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The utility model relates to integrated antenna package technical field, particularly relates to a kind of chip high efficiency encapsulating structure, and it comprises support body housing, four " Y " type Ka Gai and four chips; The punch forming of described support body housing has four encapsulation regions, each encapsulation region includes the lead foot that chip carrier is arranged at chip carrier surrounding, each chip carrier is all placed with chip, each chip carrier periphery all offers interface, with corresponding interface grafting after four " Y " type Ka Gai cover chip respectively in an encapsulation region; Wire is connected with between each chip and corresponding lead foot; Described support body housing cuts elongated hole in the surrounding punch forming of each encapsulation region, has described in one and cuts elongated hole, can reduce costs, enhance productivity, ensure package quality between adjacent and neighbouring two encapsulation regions, left and right.
Description
Technical field
The utility model relates to integrated antenna package technical field, particularly relates to a kind of chip high efficiency encapsulating structure.
Background technology
Along with the development of integrated circuit technique, the encapsulation of integrated circuit requires more and more stricter.Common packaging technology is, is fixed on lead frame by IC chip, then recycles the coated protection IC chip of colloid encapsulation, so can complete the basic framework of semiconductor packaging structure.
Existing integrated circuit package structure, chip elargol is adhered on chip carrier, and need solidify elargol by baking procedure, and chip is fixed on chip carrier.Use elargol to cause cost higher, and production efficiency is lower, and when occurring to encapsulate the problems such as bad or failure of chip, the chip be fixed on chip carrier directly can only be scrapped, thus affect the package quality of chip and the process rate of final finished.And each lead frame can only encapsulate a chip, production efficiency is lower.
Summary of the invention
The purpose of this utility model is to provide a kind of chip high efficiency encapsulating structure for the deficiencies in the prior art, can encapsulate multiple chip simultaneously, reduce costs, enhance productivity, and ensures package quality.
For achieving the above object, the utility model adopts following technical scheme.
A kind of chip high efficiency encapsulating structure, it comprises support body housing, four " Y " type Ka Gai and four chips; The punch forming of described support body housing has four encapsulation regions, each encapsulation region includes the lead foot that chip carrier is arranged at chip carrier surrounding, each chip carrier is all placed with chip, each chip carrier periphery all offers interface, with corresponding interface grafting after four " Y " type Ka Gai cover chip respectively in an encapsulation region, the middle part of " Y " type Ka Gai offers manhole; Wire is connected with between each chip and corresponding lead foot; Described support body housing cuts elongated hole in the surrounding punch forming of each encapsulation region, has described in one and cut elongated hole between adjacent and neighbouring two encapsulation regions, left and right.
Described " Y " type Ka Gai comprises " Y " type clamping sheet, and three ends of " Y " type clamping sheet are provided with edge, edge and interface grafting.
The upper end of described each encapsulation region is provided with packing colloid.
The utility model beneficial effect is: a kind of chip high efficiency encapsulating structure described in the utility model, can reduce costs, enhance productivity, and ensures package quality.
Accompanying drawing explanation
Fig. 1 is vertical view of the present utility model.
Fig. 2 is the cutaway view of an encapsulation region of the present utility model.
Fig. 3 is the structural representation of " Y " of the present utility model type Ka Gai.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further described.
As shown in Figure 1 to Figure 3, a kind of chip high efficiency encapsulating structure described in the utility model, it comprises support body housing 1, four " Y " type card lids 3 and four chips 2; The punch forming of described support body housing 1 has four encapsulation regions, each encapsulation region includes the lead foot 11 that chip carrier 10 is arranged at chip carrier 10 surrounding, each chip carrier 10 is all placed with chip 2, each chip carrier 10 periphery all offers interface, four " Y " type card lids 3 cover in an encapsulation region respectively after chip 2 with corresponding interface grafting, the middle part of " Y " type card lid 3 offers manhole 32, contribute to flowing in manhole 32 when packing colloid 5 encapsulates, better fixing " Y " type card lid 3; Wire 4 is connected with between chip 2 and lead foot 11; ; Wire 4 is connected with between each chip 2 and corresponding lead foot 11; Described support body housing 1 cuts elongated hole 12 in the surrounding punch forming of each encapsulation region, has described in one and cut elongated hole 12 between adjacent and neighbouring two encapsulation regions, left and right.
Further, described " Y " type card lid 3 comprises " Y " type clamping sheet 30, and three ends of " Y " type clamping sheet 30 are provided with edge 31, and edge 31 and interface grafting, should can be fixedly installed in chip 2 on chip carrier 10 by " Y " type card lid 3, and install simple and fast.Further, the upper and lower side of described each encapsulation region is provided with packing colloid 5, for coated and protect IC 2.
During encapsulation; four chips 2 are positioned over respectively on a chip carrier 10; use " Y " type clamping sheet 30 fixed chip 2 more respectively; then recycle packaging plastic and encapsulate the upper and lower side of each encapsulation region, coated and protect IC 2, then use cutter to cut along the elongated hole 12 that cuts of support body housing 1; so can complete the basic framework of four chip 2 encapsulating structures; can reduce costs, enhance productivity, ensure package quality.
The above is only better embodiment of the present utility model, therefore all equivalences done according to structure, feature and the principle described in the utility model patent claim change or modify, and are included in the utility model patent claim.
Claims (3)
1. a chip high efficiency encapsulating structure, is characterized in that: it comprises support body housing (1), four " Y " type Ka Gai (3) and four chips (2); The punch forming of described support body housing (1) has four encapsulation regions, each encapsulation region includes the lead foot (11) that chip carrier (10) is arranged at chip carrier (10) surrounding, each chip carrier (10) is all placed with chip (2), each chip carrier (10) periphery all offers interface, four " Y " type Ka Gai (3) cover in an encapsulation region respectively chip (2) afterwards with corresponding interface grafting, the middle part of " Y " type Ka Gai (3) offers manhole (32); Wire (4) is connected with between each chip (2) with corresponding lead foot (11); Described support body housing (1) cuts elongated hole (12) in the surrounding punch forming of each encapsulation region, has described in one and cut elongated hole (12) between adjacent and neighbouring two encapsulation regions, left and right.
2. a kind of chip high efficiency encapsulating structure according to claim 1, it is characterized in that: described " Y " type Ka Gai (3) comprise " Y " type clamping sheet (30), three ends of " Y " type clamping sheet (30) are provided with edge (31), edge (31) and interface grafting.
3. a kind of chip high efficiency encapsulating structure according to claim 1, is characterized in that: the upper end of described each encapsulation region is provided with packing colloid (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420781137.0U CN204315555U (en) | 2014-12-12 | 2014-12-12 | A kind of chip high efficiency encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420781137.0U CN204315555U (en) | 2014-12-12 | 2014-12-12 | A kind of chip high efficiency encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204315555U true CN204315555U (en) | 2015-05-06 |
Family
ID=53137856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420781137.0U Expired - Fee Related CN204315555U (en) | 2014-12-12 | 2014-12-12 | A kind of chip high efficiency encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204315555U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108695268A (en) * | 2017-04-04 | 2018-10-23 | 爱思开海力士有限公司 | Wafer-level packaging, semiconductor device cell and its manufacturing method |
| CN108847442A (en) * | 2018-06-30 | 2018-11-20 | 山东昊润自动化技术有限公司 | A kind of pressure chip packaging method |
-
2014
- 2014-12-12 CN CN201420781137.0U patent/CN204315555U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108695268A (en) * | 2017-04-04 | 2018-10-23 | 爱思开海力士有限公司 | Wafer-level packaging, semiconductor device cell and its manufacturing method |
| CN108695268B (en) * | 2017-04-04 | 2022-02-15 | 爱思开海力士有限公司 | Wafer level package, semiconductor device unit and manufacturing method thereof |
| CN108847442A (en) * | 2018-06-30 | 2018-11-20 | 山东昊润自动化技术有限公司 | A kind of pressure chip packaging method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2011090574A3 (en) | Semiconductor package and method | |
| JP2013168652A5 (en) | ||
| CN204315555U (en) | A kind of chip high efficiency encapsulating structure | |
| CN105895611A (en) | Quad flat no-lead package with wettability side surface | |
| CN204315562U (en) | A kind of multichip packaging structure | |
| CN204315554U (en) | The integrated circuit package structure of tool lead frame | |
| CN204315563U (en) | A kind of semiconductor-sealing-purpose conducting wire frame structure | |
| CN202275714U (en) | Ceramic capacitor | |
| CN204315549U (en) | A kind of anti-oxidation integrated circuit package structure | |
| CN204315556U (en) | A kind of gold-plated anti-oxidation chip-packaging structure | |
| CN204315557U (en) | A kind of high efficiency and heat radiation integrated circuit package structure | |
| CN202084532U (en) | TO92 model encapsulation box and supporting moulds | |
| CN204315548U (en) | A kind of radiating semiconductor packer | |
| CN203254606U (en) | DIP (dual-in-line package) lead frame plastic package mold | |
| CN205845929U (en) | A kind of break-resistance framework for packaging | |
| CN203826369U (en) | Semiconductor lead frame | |
| CN101211886A (en) | Outer pin-free wire holder packaging structure | |
| MY156107A (en) | Large panel leadframe | |
| CN203221121U (en) | Stamping compound die of belt type conveyor | |
| CN204271072U (en) | Lead-frame packages structure | |
| CN104538378A (en) | Wafer level package structure and technological method thereof | |
| CN202084534U (en) | TO92S type packaging box and assorted mould | |
| CN104485287B (en) | Preparation method of novel QFN (Quad Flat No Lead) frame comprising overflow groove | |
| CN202084533U (en) | T0126 packaging box and matched mould | |
| CN203339154U (en) | Lead frame structure with alternative pins |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150506 Termination date: 20211212 |