CN204315563U - A kind of semiconductor-sealing-purpose conducting wire frame structure - Google Patents
A kind of semiconductor-sealing-purpose conducting wire frame structure Download PDFInfo
- Publication number
- CN204315563U CN204315563U CN201420781160.XU CN201420781160U CN204315563U CN 204315563 U CN204315563 U CN 204315563U CN 201420781160 U CN201420781160 U CN 201420781160U CN 204315563 U CN204315563 U CN 204315563U
- Authority
- CN
- China
- Prior art keywords
- chip
- wire frame
- type
- frame body
- gai
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The utility model relates to integrated antenna package technical field, particularly relate to a kind of semiconductor-sealing-purpose conducting wire frame structure, it comprises wire frame body, " Y " type Ka Gai and chip, described wire frame body comprises chip carrier and is arranged at the lead foot of chip carrier surrounding, described chip is positioned on chip carrier, chip carrier periphery offers interface, described " Y " type Ka Gai cover after chip with interface grafting, the middle part of " Y " type Ka Gai offers manhole; Wire is connected with between chip and lead foot; The upper end of wire frame body is provided with packing colloid, and the coated described chip of packing colloid, can reduce costs, enhance productivity, and ensures package quality.
Description
Technical field
The utility model relates to integrated antenna package technical field, particularly relates to a kind of semiconductor-sealing-purpose conducting wire frame structure.
Background technology
Along with the development of integrated circuit technique, the encapsulation of integrated circuit requires more and more stricter.Common packaging technology is, is fixed on lead frame by IC chip, then recycles the coated protection IC chip of colloid encapsulation, so can complete the basic framework of semiconductor packaging structure.
Existing integrated circuit package structure, chip elargol is adhered on chip carrier, and need solidify elargol by baking procedure, and chip is fixed on chip carrier.Because using elargol to cause cost higher, and production efficiency is lower, and when occurring to encapsulate the problems such as bad or failure of chip, the chip be fixed on chip carrier directly can only be scrapped, thus affect the package quality of chip and the process rate of final finished.
Summary of the invention
The purpose of this utility model is to provide a kind of semiconductor-sealing-purpose conducting wire frame structure for the deficiencies in the prior art, can reduce costs, enhance productivity, and ensures package quality.
For achieving the above object, the utility model adopts following technical scheme.
A kind of semiconductor-sealing-purpose conducting wire frame structure, it comprises wire frame body, " Y " type Ka Gai and chip, described wire frame body comprises chip carrier and is arranged at the lead foot of chip carrier surrounding, described chip is positioned on chip carrier, chip carrier periphery offers interface, described " Y " type Ka Gai cover after chip with interface grafting, the middle part of " Y " type Ka Gai offers manhole; Wire is connected with between chip and lead foot; The upper end of wire frame body is provided with packing colloid, the coated described chip of packing colloid.
Described " Y " type Ka Gai comprises " Y " " type clamping sheet, three ends of " Y " type clamping sheet are provided with edge, edge and interface grafting.
Described wire frame body is square.
The utility model beneficial effect is: a kind of semiconductor-sealing-purpose conducting wire frame structure described in the utility model, can reduce costs, enhance productivity, and ensures package quality.
Accompanying drawing explanation
Fig. 1 is vertical view of the present utility model.
Fig. 2 is cutaway view of the present utility model.
Fig. 3 is the structural representation of " Y " of the present utility model type Ka Gai.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further described.
As shown in Figure 1 to Figure 3, a kind of semiconductor-sealing-purpose conducting wire frame structure described in the utility model, it comprises wire frame body 1, " Y " type card lid 3 and chip 2, described wire frame body 1 comprises chip carrier 10 and is arranged at the lead foot 11 of chip carrier 10 surrounding, described chip 2 is positioned on chip carrier 10, chip carrier 10 periphery offers interface, described " Y " type card lid 3 covers after chip 2 and interface grafting, the middle part of " Y " type card lid 3 offers manhole 32, contribute to flowing in manhole 32 when packing colloid 5 encapsulates, better fixing " Y " type card lid 3; Wire 4 is connected with between chip 2 and lead foot 11; The upper end of wire frame body 1 is provided with packing colloid 5, the coated described chip 2 of packing colloid 5.Further, described " Y " type card lid 3 comprises " Y " type clamping sheet 30, and three ends of " Y " type clamping sheet 30 are provided with edge 31, and edge 31 and interface grafting, should can be fixedly installed in chip 2 on chip carrier 10 by " Y " type card lid 3, and install simple and fast.Further described wire frame body 1 is square, and is convenient to support body punch forming.
During encapsulation; chip 2 is positioned on chip carrier 10; use " Y " type clamping sheet 30 fixed chip 2 again; then the upper end of packaging plastic packaging conductor frame body 1 is recycled; coated and protect IC 2, so can complete the basic framework of semiconductor packaging structure, can reduce costs; enhance productivity, ensure package quality.
The above is only better embodiment of the present utility model, therefore all equivalences done according to structure, feature and the principle described in the utility model patent claim change or modify, and are included in the utility model patent claim.
Claims (3)
1. a semiconductor-sealing-purpose conducting wire frame structure, it is characterized in that: it comprises wire frame body (1), " Y " type Ka Gai (3) and chip (2), described wire frame body (1) comprises chip carrier (10) and is arranged at the lead foot (11) of chip carrier (10) surrounding, described chip (2) is positioned on chip carrier (10), chip carrier (10) periphery offers interface, described " Y " type Ka Gai (3) cover chip (2) afterwards with interface grafting, the middle part of " Y " type Ka Gai (3) offers manhole (32); Wire (4) is connected with between chip (2) and lead foot (11); The upper end of wire frame body (1) is provided with packing colloid (5), the coated described chip (2) of packing colloid (5).
2. a kind of semiconductor-sealing-purpose conducting wire frame structure according to claim 1, it is characterized in that: described " Y " type Ka Gai (3) comprise " Y " type clamping sheet (30), three ends of " Y " type clamping sheet (30) are provided with edge (31), edge (31) and interface grafting.
3. a kind of semiconductor-sealing-purpose conducting wire frame structure according to claim 1, is characterized in that: described wire frame body (1) is square.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420781160.XU CN204315563U (en) | 2014-12-12 | 2014-12-12 | A kind of semiconductor-sealing-purpose conducting wire frame structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420781160.XU CN204315563U (en) | 2014-12-12 | 2014-12-12 | A kind of semiconductor-sealing-purpose conducting wire frame structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204315563U true CN204315563U (en) | 2015-05-06 |
Family
ID=53137864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420781160.XU Expired - Fee Related CN204315563U (en) | 2014-12-12 | 2014-12-12 | A kind of semiconductor-sealing-purpose conducting wire frame structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204315563U (en) |
-
2014
- 2014-12-12 CN CN201420781160.XU patent/CN204315563U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150506 Termination date: 20211212 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |