CN203025502U - Low background alpha and beta measurement instrument control device - Google Patents
Low background alpha and beta measurement instrument control device Download PDFInfo
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- CN203025502U CN203025502U CN 201220606613 CN201220606613U CN203025502U CN 203025502 U CN203025502 U CN 203025502U CN 201220606613 CN201220606613 CN 201220606613 CN 201220606613 U CN201220606613 U CN 201220606613U CN 203025502 U CN203025502 U CN 203025502U
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Abstract
The utility model relates to a low background alpha and beta measurement instrument control device. The device comprises a nuclear pulse pre-processing unit, a main control computing unit based on FPGA/CPLD, a communication interface unit and a high voltage and threshold value control unit. The main control computing unit based on FPGA/CPLD is connected with the nuclear pulse pre-processing unit, the communication interface unit and the high voltage and threshold value control unit separately, and the high voltage and threshold value control unit is connected with the nuclear pulse pre-processing unit. The device of the utility model has the following characteristics of high-speed parallel processing, real-time synchronous processing of multiple signals, easy extension, high integration level, reduced dosage of peripheral chips, improved stability, etc.
Description
Technical field
The utility model relates to a kind of control device, particularly a kind of low background α β measuring instrument control device.
Background technology
in the nuclear detection technology field, detector can be converted into fast electronic signal by the interaction (as producing photon or electronics etc.) with actuating medium at last with the energy of radiation (particle beams), partly carry out pre-service by front-end electronics again, comprise preposition amplification, the filtering moulding, screen or sampling, be converted into digital signal, then sending into controller part (CPU or MCU) calculates, analyze or record, the controller part also needs to communicate with host computer usually, interactive instruction and data, then discriminator being carried out threshold value controls or controlling of sampling, and detector is carried out high voltage control.
In this type of traditional low background α, β measuring instrument, circuit part comprises the pre-process unit, and the pre-process unit comprises amplifier, filtering circuit and comparer.Signal after comparer will be processed is converted into digit pulse, then screens by various composite door circuit and trigger, then sends into the processor that single-chip microcomputer consists of and carry out analysis and calculation.Single-chip microcomputer is communicated by letter with host computer, and mutual data of measuring, and to carry out control command mutual with host computer are carried out threshold value according to steering order to the pre-process unit and controlled, and the high voltage adjusting of carrying out of detector is controlled.As control core, it is convenient that single-chip microcomputer has programmed configurations to this conventional circuit structure by single-chip microcomputer, the advantages such as rich interface, but single-chip microcomputer is serial operation, only responds in the same time an interruption, namely processes one road signal.And single-chip microcomputer is by the in house software program, the data of the measurement of α, β to be carried out computational analysis, and the possibility that software program has race to fly has brought labile factor for the measurement of instrument.α, β surveying instrument progressively develop into 2 passages by single channel, 4 passages and hyperchannel (〉=6 passages at present), simultaneously treated signal expanded to 3 tunnel (2 passages) by 2 tunnel former (single channels), 6 tunnel (4 passages) and multichannel (hyperchannel).Single-chip microcomputer has larger limitation under the work in series principle, cause the loss of more measurement event.And, peripheral gate circuit and flip-flop circuit need to be according to the increases of port number and extra increasing, make circuit not possess extendability, and increase the failure rate of instrument integral body due to the use of more separate electronic device, reduce whole stability and reliability.
The utility model content
The utility model provides a kind of low background α β measuring instrument control device based on field programmable gate array (FPGA) or CPLD (CPLD), and this control device has the high-speed parallel processing power, can process in real time multiple signals.
The technical solution adopted in the utility model is: a kind of low background α β measuring instrument control device, comprise core pulse pre-process unit, and based on the main control computing unit of FPGA/CPLD, communications interface unit and high pressure and threshold value control module; Be connected with the threshold value control module with core pulse pre-process unit, communications interface unit and high pressure respectively based on the main control computing unit of FPGA/CPLD, high pressure and threshold value control module are connected with core pulse pre-process unit.
Press such scheme, described pre-process unit comprises prime amplifier, filtering circuit and amplitude discriminator circuit.Wherein the amplitude discriminator circuit adopts comparer or analog to digital converter to consist of, and the threshold value of comparer or analog to digital converter is adjusted control by HVT high voltage threshold's control module.
Press such scheme, described main control computing unit based on FPGA/CPLD comprises communication module, and data processing module and threshold value high pressure arrange module, and data processing module is connected module with communication module with the threshold value high pressure respectively and is connected.Data processing module is by communication module and communications interface unit interactive command, and the line command of going forward side by side is resolved, and according to analysis result, Packet Generation will be set and to the threshold value high pressure, module be set.
Press such scheme, described communications interface unit is serial ports transceiver module or USB module or network communication module.Send into serial ports transceiver module or USB module or network communication module based on the packet of the main control computing unit of FPGA/CPLD output temporary, then be connected with host computer by communications interface unit, send data and interactive command.
Press such scheme, described main control computing unit based on FPGA/CPLD also comprises comprehensive trigger module, is used for carrying out logical process to sending into signal.
Press such scheme, described comprehensive trigger module comprises logic gate and trigger.
Principle of work of the present utility model is: the main control computing unit based on FPGA/CPLD receives by the signal after the pre-process cell processing, after inside enters comprehensive trigger module comprehensive analysis and judgement, entering data processing module processes, data processing module is by communication module and communications interface unit interactive command, the line command of going forward side by side is resolved, and according to analysis result, Packet Generation will be set and to the threshold value high pressure, module be set.
Based on the outside connect threshold of the main control computing unit of FPGA/CPLD and high voltage control unit, based on the main control computing unit passing threshold high pressure of FPGA/CPLD, module is set and sends control command to threshold value and high voltage control unit, threshold value and high voltage control unit are controlled the threshold value of the comparer in the pre-process unit and the high pressure of detector in real time.
The beneficial effects of the utility model are:
1. this control device can adopt parallel work-flow to signal, can synchronously process the output signal of multiplexed detection device, can packet loss, increase the accuracy of measuring.
2. this control device by programming at chip internal, merges signal and processes, and calculates storage, transmission, a plurality of modules such as control.Can reduce the too much use of discrete device in traditional circuit, reduce the System on Chip/SoC consumption, save circuit board space, reduce the system failure rate that brings due to failure of chip.
3. can change the chip internal circuit structure according to the output signal path of actual detector based on the programmable characteristic of FPGA/CPLD in the main control computing unit of FPGA/CPLD in this control device, complete the synchronous expansion of processing of multiple signals.
4. this control device adopts the programming of hardware-level, and the circuit operation stability program operation phenomenon out of control can not occur higher than the single-chip microcomputer based on software/instruction, increases the stability of detection system.
5. in this control device, the main control computing unit based on FPGA/CPLD builds different transceiver communication modules at the internal condition actual needs, can be the SPI of standard, serial ports, USB, I2C etc. can be also self-defining communication protocol, and is more convenient with communicating by letter of exterior terminal/host computer.
Description of drawings
1. Fig. 1 is the structural representation of an embodiment of a kind of low background α of the utility model, β measuring instrument control device.
2. Fig. 2 is the core pulse pre-process cellular construction schematic diagram of an embodiment of the utility model.
3. Fig. 3 represents the main control computing unit structural representation based on FPGA/CPLD of an embodiment of the utility model.
4. Fig. 4 represents the communications interface unit structural representation of an embodiment of the utility model.
5. Fig. 5 represents high pressure and the threshold value peripheral control unit structural representation of an embodiment of the utility model.
Embodiment
Below by by embodiment, the utility model being described in further detail, but following examples are only illustrative, and protection domain of the present utility model is not subjected to the restriction of these embodiment.
As shown in Figure 1, the present invention mainly comprises core pulse pre-process unit 100, based on the main control computing unit 200 of FPGA/CPLD, and communications interface unit 300, high pressure and threshold value control module 400.
As shown in Figure 2, described core pulse pre-process unit 100 is comprised of a plurality of identical parallel processing modules, all comprises passive filter 110 in each module, prime amplifier 120, and the threshold value discriminator forms 130.The core pulse of each road input is first carried out low-pass filtering by passive filter 110, reduce high frequency noise, then smooth waveform is sent into prime amplifier 120 and is amplified, and at last the waveform that amplifies is sent into threshold value discriminator 130 and screens judgement.The pulse of multichannel core is output as the pulse of multichannel Transistor-Transistor Logic level at last through a plurality of parallel processing modules.
As shown in Figure 3, described master control computing unit 200 based on FPGA/CPLD, the CPLD device MaxII EPM570 of employing Altera, by hardware programming, comprehensive trigger module 210, data processing module 220 have been constructed at chip internal, communication module 230, the threshold value high pressure arranges module 240.
The pulse of multichannel Transistor-Transistor Logic level is input in CPLD, enters comprehensive trigger module 210, and multiple signals produce comprehensive multiplex pulse afterwards in these comprehensive analysis and judgement.Multiplex pulse enters data processing module 220 again, and what the data processing module within was synchronous carries out parallel processing to multiple signals, measurement count, and parallel synchronous is counted respectively on each road be stored in separately in register.Communication module 230 in CPLD adopts serial ports transmitting-receiving agreements, is connected also interaction data with external communication interface unit 300, and the data in all registers are packed according to certain format, sends according to certain sequential.
Described threshold value high pressure arrange module 240 receive packet is set after, send the control command bag of special data structure to external high pressure and threshold value control module 400 by the SPI interface.
Described communications interface unit 300 is serial ports transceiver module or USB module as shown in Figure 4, send into serial ports transceiver module 310 or USB module 320 is temporary based on the packet of main control computing unit 200 output of FPGA/CPLD, then be connected with host computer by 9 pin RS232 serial communication modes or USB interface, send data and interactive command.
As shown in Figure 5, described high pressure and threshold value control module 400 are comprised of two DAC410 and isolated amplifier 420, and wherein the precision of DAC is 10.DAC receives the threshold value high voltage control order bag that CPLD sends, according to the numerical information in order and bag, be converted to analog level signal, export to isolated amplifier 420, isolated amplifier 420 amplifies analog level signal or oppositely amplifies, and with front and back level isolation, at last output signal is sent into the threshold value discriminator 140 in outside high-pressure modular or core pulse pre-process unit 100.
Claims (7)
1. one kind low background α β measuring instrument control device is characterized in that: comprise core pulse pre-process unit, and based on the main control computing unit of FPGA/CPLD, communications interface unit and high pressure and threshold value control module; Be connected with the threshold value control module with core pulse pre-process unit, communications interface unit and high pressure respectively based on the main control computing unit of FPGA/CPLD, high pressure and threshold value control module are connected with core pulse pre-process unit.
2. low background α β measuring instrument control device as claimed in claim 1 is characterized in that: described pre-process unit comprises prime amplifier, filtering circuit and amplitude discriminator circuit.
3. low background α β measuring instrument control device as claimed in claim 2, is characterized in that: described amplitude discriminator circuit employing comparer or analog to digital converter formation.
4. low background α β measuring instrument control device as claimed in claim 1, it is characterized in that: described main control computing unit based on FPGA/CPLD comprises communication module, data processing module and threshold value high pressure arrange module, and data processing module is connected module with communication module with the threshold value high pressure respectively and is connected.
5. low background α β measuring instrument control device as claimed in claim 4, it is characterized in that: described main control computing unit based on FPGA/CPLD also comprises comprehensive trigger module, is used for carrying out logical process to sending into signal.
6. low background α β measuring instrument control device as claimed in claim 5, it is characterized in that: described comprehensive trigger module comprises logic gate and trigger.
7. low background α β measuring instrument control device as claimed in claim 1, it is characterized in that: described communications interface unit is serial ports transceiver module or USB module or network communication module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220606613 CN203025502U (en) | 2012-11-16 | 2012-11-16 | Low background alpha and beta measurement instrument control device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220606613 CN203025502U (en) | 2012-11-16 | 2012-11-16 | Low background alpha and beta measurement instrument control device |
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| CN203025502U true CN203025502U (en) | 2013-06-26 |
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| CN 201220606613 Expired - Lifetime CN203025502U (en) | 2012-11-16 | 2012-11-16 | Low background alpha and beta measurement instrument control device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102968080A (en) * | 2012-11-16 | 2013-03-13 | 湖北方圆环保科技有限公司 | Control device for low-background alpha-beta measuring instrument |
| CN112564705A (en) * | 2020-12-02 | 2021-03-26 | 湖北方圆环保科技有限公司 | Multi-channel data acquisition method for radon measuring instrument |
-
2012
- 2012-11-16 CN CN 201220606613 patent/CN203025502U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102968080A (en) * | 2012-11-16 | 2013-03-13 | 湖北方圆环保科技有限公司 | Control device for low-background alpha-beta measuring instrument |
| CN112564705A (en) * | 2020-12-02 | 2021-03-26 | 湖北方圆环保科技有限公司 | Multi-channel data acquisition method for radon measuring instrument |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130626 |