CN201688851U - Navigational computer of double-DSP-processor platform - Google Patents
Navigational computer of double-DSP-processor platform Download PDFInfo
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- CN201688851U CN201688851U CN2010201096653U CN201020109665U CN201688851U CN 201688851 U CN201688851 U CN 201688851U CN 2010201096653 U CN2010201096653 U CN 2010201096653U CN 201020109665 U CN201020109665 U CN 201020109665U CN 201688851 U CN201688851 U CN 201688851U
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Abstract
The utility model belongs to navigational computers, in particular to a navigational computer circuit of a double-DSP-processor platform. The utility model aims at designing an analog-to-digital mixing circuit of the navigational computer circuit of the double-DSP-processor platform with good popularity, realizes multi-task parallel fast processing, and can be compatible to a plurality of types and accelerate the research and production speed of an inertial navigation system. The navigational computer circuit of the double-DSP-processor platform comprises the DSP-processor platform, a gyro interface circuit, an accelerometer interface circuit and a communication interface circuit, wherein the DSP-processor platform is the double-DSP-processor platform and comprises an FPGA and two DSP minimum systems. The double-DSP-processor platform also comprises a secondary power supply and provides two power supplies for IO power supplies of a DSP and the FPGA, a nuclear-electric power supply and a power supply of a storage for peripheral expansion; and the DSP minimum system comprises a DSP, an SRAM/SDRAM/SBSRAM, and a FLASH. The navigational computer has the advantages of realizing parallel and fast processing of multiple tasks, being compatible to a plurality of types and accelerating the research and production speed of the inertial navigation system.
Description
Technical field
The utility model belongs to navigational computer, is specifically related to a kind of pair of dsp processor platform navigation calculating machine circuit.
Background technology
Present stage, navigational computer adopted single DSP processing platform more, and to outside gyro signal, add table signal, temperature signal etc. and carry out data acquisition, filtering is resolved then and navigated; Owing to have a large amount of filtering algorithms and navigation algorithm, and single DSP processing platform can not parallel processing, cause single DSP platform navigational computer to have potential topic of computing velocity and computing power shortcoming, simultaneously because versatility is not enough, cause the research and development of products cycle long, component purchase can not in time be supplied with, the new product reliability can not be verified very soon, seriously restricted the R﹠D and production process of inertial navigation system, even cause the huge waste of human and material resources, time, it is passive to locate in market competition.
Summary of the invention
The purpose of this utility model is at the defective of existing design, designs the good two dsp processor platform navigational computer modulus hybrid circuits of a kind of versatility, realizes the parallel fast processing of multitask, can compatible a plurality of models, and the quickening inertial navigation system grinds product speed.
The utility model is achieved in that a kind of pair of dsp processor platform navigational computer, comprises dsp processor platform, gyro interface circuit, accelerometer interface circuit, communication interface circuit; Wherein, the dsp processor platform is two dsp processor platforms, comprises FPGA and two DSP minimum systems.
Aforesaid a kind of pair of dsp processor platform navigational computer, wherein, two dsp processor platforms also comprise secondary power supply, and the power supply of the storer that IO mouth power supply, nuclear-electric power supply and the peripheral expansion of two DSP and FPGA use is provided; The DSP minimum system comprises DSP, SRAM/SDRAM/SBSRAM, FLASH.
Aforesaid a kind of pair of dsp processor platform navigational computer, wherein, secondary power supply 1 adopts three PTH04070 chips to produce IO mouth power supply, DSP nuclear-electric power supply, the FPGA nuclear-electric power supply of three power supply: DSP/FPGA, and these three power supplys link to each other with corresponding power pin of device such as DSP, FPGA, peripheral storages respectively.
Aforesaid a kind of pair of dsp processor platform navigational computer, wherein, the gyro interface circuit is the laser gyro interface circuit, the laser gyro signal connects the optocoupler input end, this schmitt trigger input end of optocoupler output termination, the I/O mouth of this schmitt trigger output termination FPGA 5 adopts gyro counter module logic in FPGA 5, the laser gyro signal is carried out counting after phase-detecting and the quadruple; The gyro temperature signal is through the RC low-pass filter circuit, and the IO mouth that the output of RC low-pass filter circuit meets FPGA adopts the unibus temperature test module logic among the FPGA, to gathering of laser gyro temperature.
Aforesaid a kind of pair of dsp processor platform navigational computer, wherein, accelerometer selects the signal input to enter low-pass filter, and low-pass filter 9 outputs connect the IO mouth of FPGA; Circuit is selected in the selecting of accelerometer temperature signal, selects circuit output 1 for the beam that shakes adds the table temperature, connects the shaping circuit input end, and shaping circuit output connects the IO mouth of FPGA, adopts the frequency measurement module logic of the Liang Jiabiao that shakes of FPGA, measures the frequency of this temperature signal; Select circuit output 2 for the flexible table temperature that adds, connect RC low-pass filter circuit input end, the I/O mouth of RC low-pass filter circuit output termination FPGA adopts the unibus temperature test module logic among the FPGA, finishes the flexible table selection of temperature signal that adds; The pulse signal of accelerometer enters the selection circuit input end, select the pulse signal of circuit output end 1 for the Liang Jiabiao that shakes, through the shaping circuit input end, the I/O mouth of shaping circuit output termination FPGA, adopt the beam that shakes among the FPGA to add table frequency measurement module, measure the frequency of each signal of Liang Jiabiao that shakes; Select circuit output end 2 to be the flexible pulse signal that adds table, connect the shaping circuit input end, the IO mouth of shaping circuit output termination FPGA adopts the common table counter module that adds among the FPGA, finishes to add the collection of showing pulse signal to flexible.
Aforesaid a kind of pair of dsp processor platform navigational computer, wherein, the communication interface circuit is made up of five road communication interfaces, electric selection signal input electric conversion chip, the electrical specification of selection input/output signal; Received signal enters electric conversion chip input end, and the electric conversion chip output connects the optocoupler input end, and the IO mouth of optocoupler output termination FPGA receives by the intelligent communication interface module in FPGA; The intelligent communication interface module sends signal and connects the input end of optocoupler through the IO of FPGA mouth, the output termination electric conversion chip input end of optocoupler, and the electric conversion chip output connects output signal.
The utility model has the advantages that: realize the parallel fast processing of multitask, can compatible a plurality of models, accelerate inertial navigation system and grind product speed.
Description of drawings
The two dsp processor platform synoptic diagram of Fig. 1;
Fig. 2 laser gyro interface circuit synoptic diagram;
Fig. 3 accelerometer interface circuit synoptic diagram;
Fig. 4 communication interface circuit diagram;
1. secondary power supply circuit 2.SRAM/SDRAM/SBSRAM 3.FLASH 4.DSP5.FPGA 6.DSP 7.SRAM/SDRAM/SBSRAM 8.FLASH 9. RLG Signals 10. laser gyro temperature signals 11. optocouplers 12. this schmitt trigger 13.RC low-pass filter circuits 14. accelerometer temperature signals 15. add the table temperature and select circuit 16. shaping circuit 17.RC low pass filters 18. to add table to select signal 19.RC low-pass filter circuit 20. to add table signal 21. to add table signal selecting circuit 22. shaping circuits 23. shaping circuits 24. communication ports and receive the electric selection signal 27. electric conversion chips of signal 25. communication port transmitted signals, 26. communication ports 28. optocouplers 29. optocouplers.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is described further:
A kind of pair of dsp processor platform navigational computer comprises two dsp processor platforms, gyro interface circuit, accelerometer interface circuit, communication interface circuit.
Two dsp processor platforms comprise secondary power supply, two DSP minimum systems and peripheral expansion storer thereof, FPGA.Secondary power supply provides the power supply of the storer that IO mouth power supply, nuclear-electric power supply and the peripheral expansion of two DSP and FPGA use.The DSP minimum system is made up of DSP, SRAM/SDRAM/SBSRAM, FLASH etc., and DSP is used for information pre-service, various mathematical algorithm and navigation algorithm; FLASH is used to store user program, data; The storage of program, data when SRAM/SDRAM/SBSRAM is used for dsp operation.FPGA be used for that peripheral interface is handled and two DSP between mutual communication, concrete communication modes can adopt serial asynchronous communication, dual port RAM, HPI etc.
Two dsp processor platform circuitry synoptic diagram are as shown in Figure 1: secondary power supply 1 adopts three PTH04070 chips to produce IO mouth power supply (this power supply also is used for other external memory storage), DSP nuclear-electric power supply, the FPGA nuclear-electric power supply of three power supply: DSP/FPGA, and these three power supplys link to each other with corresponding power pin of device such as DSP, FPGA, peripheral storages respectively; SDRAM/SBSRAM/ SRAM 2 or 7 links to each other data bus, address bus, control line according to user's bit wide with DSP 4 or 6 respective pin; FLASH3 or 8 links to each other data bus, address bus, control line according to user's bit wide with DSP 4 or 6 respective pin; DSP 4 and 6 inserts FPGA 5 to data bus, address bus, control line according to user's bit wide.
The laser gyro interface circuit comprises gyro signal and gyro processes temperature signal circuit.Laser gyro just/cosine signal earlier through isolating and shaping, carries out counting after phase-detecting and the quadruple in FPGA then; The gyro temperature is the unibus signal, through after the low-pass filtering, finishes the control of 1-wire temperature sensor then in FPGA earlier, and gathers the temperature data of gyro.
Laser gyro interface circuit synoptic diagram is as shown in Figure 2: laser gyro signal 9 connects optocoupler 11 input ends, optocoupler 11 these schmitt trigger 12 input ends of output termination, the I/O mouth of this schmitt trigger 12 output termination FPGA5, in FPGA 5, adopt gyro counter module logic, the laser gyro signal is carried out counting after phase-detecting and the quadruple; Gyro temperature signal 10 is through RC low-pass filter circuit 12, and the IO mouth that 12 outputs of RC low-pass filter circuit meet FPGA 5 adopts the unibus temperature test module logic among the FPGA 5, to gathering of laser gyro temperature.
Add the compatible flexible table and the Liang Jiabiao that shakes of adding of table interface circuit, mainly comprise adding the table type selecting, adding table signal, Temperature Treatment circuit.Wherein, add table and select signal after low-pass filtering, enter FPGA on the one hand and gather and be used to select FPGA inside to add table handing module accordingly; Be used to select to add the treatment circuit of showing under signal and temperature signal type and the type thereof on the other hand.If the type selecting signal is a high level, be that then the Liang Jiabiao that shakes, the beam that shakes add table temperature and the shaping of Jia Biao signal process, import FPGA, adopt the frequency measurement module of the Liang Jiabiao that shakes of FPGA, measure the frequency of this signal; If the selection signal is a low level, then be the flexible table that adds, the flexible temperature signal that adds table is imported FPGA by low-pass filtering, adopt the unibus temperature test module among the FPGA, finish the flexible table selection of temperature signal that adds, the flexible table pulse signal that adds enters FPGA through shaping, adopts the common table counter module that adds, and finishes to add the collection of showing pulse signal to flexible.
Accelerometer interface circuit synoptic diagram is as shown in Figure 3: accelerometer selects signal 18 inputs to enter low-pass filter 19, and low-pass filter 19 outputs connect the IO mouth of FPGA 5.Circuit 15 is selected in 14 selectings of accelerometer temperature signal, select circuit 15 outputs 1 (beam that shakes adds the table temperature) to connect shaping circuit 16 input ends, shaping circuit 16 outputs connect the IO mouth of FPGA 5, adopt the frequency measurement module logic of the Liang Jiabiao that shakes of FPGA 5, measure the frequency of this temperature signal; Select circuit 15 outputs 2 (the flexible table temperature that adds) RC low-pass filter circuit 17 input ends, the I/O mouth of RC low-pass filter circuit 17 output termination FPGA 5 adopts the unibus temperature test module logic among the FPGA 5, finishes the flexible table selection of temperature signal that adds.The pulse signal 20 of accelerometer enters selects circuit 21 input ends, select circuit 21 output terminals 1 (pulse signal of the Liang Jiabiao that shakes) through shaping circuit 22 input ends, the I/O mouth of shaping circuit 22 output termination FPGA5, adopt the beam that shakes among the FPGA 5 to add table frequency measurement module, measure the frequency of each signal of Liang Jiabiao that shakes; Select circuit 21 output terminals 2 (the flexible pulse signal that adds table) to connect shaping circuit 23 input ends, the IO mouth of shaping circuit 23 output termination FPGA 5 adopts the common table counter module that adds among the FPGA 5, finishes to add the collection of showing pulse signal to flexible.
The communication interface circuit is made up of five road communication interfaces, is used for the expansion of communication and external circuit.Every road interface can satisfy the RS232/RS422/RS485 electrical specification, is made up of electric selection signal, input signal, output signal processing circuit.Electric selection signal input control electric conversion chip, the electrical specification of selection input/output signal; Received signal is converted to Transistor-Transistor Logic level through the electric conversion chip, outputs to FPGA through after the light-coupled isolation, receives by the intelligent communication module in FPGA; The intelligent communication module produces and sends signal among the same FPGA of employing, and this signal outputs to the electric conversion chip after light-coupled isolation, be converted to the electrical specification of requirement after output send signal.
Simplex interface synoptic diagram is as shown in Figure 4: electric selection signal 26 input electric conversion chips 27, select the electrical specification of input/output signal; Received signal 24 enters electric conversion chip 27 input ends, electric conversion chip 27 output termination optocouplers 28 input ends, and the IO mouth of optocoupler 28 output termination FPGA 5 receives by the intelligent communication interface module in FPGA 5; The intelligent communication interface module sends signal and connects the input end of optocoupler 29, output termination electric conversion chip 4 input ends of optocoupler 29, electric conversion chip 4 output termination output signals 25 through the IO of FPGA 5 mouth.
According to user's needs, utilize the programmable characteristics of FPGA, but the task of two DSP of flexible allocation: for the very high navigational computer of reliability requirement, can adopt two DSP redundancy fault-tolerant structures; For the not enough navigational computer of single DSP data-handling capacity, then can adopt two DSP parallel organizations; Enough and reliability does not have the navigational computer of specific (special) requirements for single DSP data-handling capacity, then can only enable single DSP yet.
Claims (6)
1. a two dsp processor platform navigational computer comprises dsp processor platform, gyro interface circuit, accelerometer interface circuit, communication interface circuit; It is characterized in that: the dsp processor platform comprises FPGA and two DSP minimum systems for two dsp processor platforms.
2. a kind of pair of dsp processor platform navigational computer as claimed in claim 1, it is characterized in that: two dsp processor platforms also comprise secondary power supply, and the power supply of the storer that IO mouth power supply, nuclear-electric power supply and the peripheral expansion of two DSP and FPGA use is provided; The DSP minimum system comprises DSP, SRAM/SDRAM/SBSRAM, FLASH.
3. a kind of pair of dsp processor platform navigational computer as claimed in claim 2 is characterized in that: secondary power supply 1 adopts three PTH04070 chips to produce IO mouth power supply, DSP nuclear-electric power supply, the FPGA nuclear-electric power supply of three power supply: DSP/FPGA.
4. a kind of pair of dsp processor platform navigational computer as claimed in claim 3, it is characterized in that: the gyro interface circuit is the laser gyro interface circuit, laser gyro signal (9) connects optocoupler (11) input end, optocoupler (11) output this schmitt trigger of termination (12) input end, the I/O mouth of this schmitt trigger (12) output termination FPGA (5), in FPGA (5), adopt gyro counter module logic, the laser gyro signal is carried out counting after phase-detecting and the quadruple; Gyro temperature signal (10) is through RC low-pass filter circuit (12), and the IO mouth that RC low-pass filter circuit (12) output meets FPGA (5) adopts the unibus temperature test module logic among the FPGA (5), to gathering of laser gyro temperature.
5. a kind of pair of dsp processor platform navigational computer as claimed in claim 4 is characterized in that: accelerometer selects signal (18) input to enter low-pass filter (19), and low-pass filter (19) output connects the IO mouth of FPGA (5); Circuit (15) is selected in accelerometer temperature signal (14) selecting, select circuit (15) output 1 to add the table temperature for the beam that shakes, connect shaping circuit (16) input end, shaping circuit (16) output connects the IO mouth of FPGA (5), adopt the frequency measurement module logic of the Liang Jiabiao that shakes of FPGA (5), measure the frequency of this temperature signal; Select circuit (15) output 2 to be the flexible table temperature that adds, connect RC low-pass filter circuit (17) input end, the I/O mouth of RC low-pass filter circuit (17) output termination FPGA (5) adopts the unibus temperature test module logic among the FPGA (5), finishes the flexible table selection of temperature signal that adds; The pulse signal of accelerometer (20) enters selects circuit (21) input end, select the pulse signal of circuit (21) output terminal 1 for the Liang Jiabiao that shakes, through shaping circuit (22) input end, the I/O mouth of shaping circuit (22) output termination FPGA (5), adopt the beam that shakes among the FPGA (5) to add table frequency measurement module, measure the frequency of each signal of Liang Jiabiao that shakes; Select circuit (21) output terminal 2 to be the flexible pulse signal that adds table, connect shaping circuit (23) input end, the IO mouth of shaping circuit (23) output termination FPGA (5) adopts the common table counter module that adds among the FPGA (5), finishes to add the collection of showing pulse signal to flexible.
6. a kind of pair of dsp processor platform navigational computer as claimed in claim 5, it is characterized in that: the communication interface circuit is made up of five road communication interfaces, electric selection signal (26) input electric conversion chip (27), the electrical specification of selection input/output signal; Received signal (24) enters electric conversion chip (27) input end, electric conversion chip (27) output termination optocoupler (28) input end, and the IO mouth of optocoupler (28) output termination FPGA (5) receives by the intelligent communication interface module in FPGA (5); The intelligent communication interface module sends signal and connects the input end of optocoupler (29), output termination electric conversion chip (4) input end of optocoupler (29), electric conversion chip (4) output termination output signal (25) through the IO mouth of FPGA (5).
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010201096653U CN201688851U (en) | 2010-02-09 | 2010-02-09 | Navigational computer of double-DSP-processor platform |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010201096653U CN201688851U (en) | 2010-02-09 | 2010-02-09 | Navigational computer of double-DSP-processor platform |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102980582A (en) * | 2012-12-25 | 2013-03-20 | 重庆华渝电气仪表总厂 | Universal computer based on dual-ARM (advanced RISC machine) singlechip for platform-type inertial navigation equipment |
| CN106289256A (en) * | 2016-07-25 | 2017-01-04 | 湖北师范大学 | Signal calculated processing system based on two CSTR Yu FPGA architecture |
| CN108151741A (en) * | 2018-01-04 | 2018-06-12 | 北京原子机器人科技有限公司 | Multimode Intelligent inertial navigation sensor-based system and its data processing method |
| CN114374243A (en) * | 2021-12-22 | 2022-04-19 | 南京安广电力设备有限公司 | Energy storage battery control device and method |
-
2010
- 2010-02-09 CN CN2010201096653U patent/CN201688851U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102980582A (en) * | 2012-12-25 | 2013-03-20 | 重庆华渝电气仪表总厂 | Universal computer based on dual-ARM (advanced RISC machine) singlechip for platform-type inertial navigation equipment |
| CN102980582B (en) * | 2012-12-25 | 2015-05-20 | 重庆华渝电气仪表总厂 | Universal computer based on dual-ARM (advanced RISC machine) singlechip for platform-type inertial navigation equipment |
| CN106289256A (en) * | 2016-07-25 | 2017-01-04 | 湖北师范大学 | Signal calculated processing system based on two CSTR Yu FPGA architecture |
| CN108151741A (en) * | 2018-01-04 | 2018-06-12 | 北京原子机器人科技有限公司 | Multimode Intelligent inertial navigation sensor-based system and its data processing method |
| CN114374243A (en) * | 2021-12-22 | 2022-04-19 | 南京安广电力设备有限公司 | Energy storage battery control device and method |
| CN114374243B (en) * | 2021-12-22 | 2024-02-23 | 南京安广电力设备有限公司 | Energy storage battery control device and method |
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Granted publication date: 20101229 |