CN106649166A - Universal inertial data processing system based on uniform interface - Google Patents
Universal inertial data processing system based on uniform interface Download PDFInfo
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- CN106649166A CN106649166A CN201611252762.6A CN201611252762A CN106649166A CN 106649166 A CN106649166 A CN 106649166A CN 201611252762 A CN201611252762 A CN 201611252762A CN 106649166 A CN106649166 A CN 106649166A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q1/00—Details of selecting apparatus or arrangements
- H04Q1/02—Constructional details
- H04Q1/028—Subscriber network interface devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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Abstract
The invention discloses a universal inertial data processing system based on a uniform interface. The universal inertial data treatment system based on the uniform interface is characterized in that the data processing system comprises a pulse collection circuit, a communication interface circuit, a main control chip set, a data processing unit and a power source board, wherein the pulse collection circuit is used for collecting inertial positive and negative channel pulse output; the communication interface circuit achieves inertial data collection which is output by the inertial unit in a bus communication mode; a platinum resistance temperature measuring circuit measures compensating parameters which are needed when inertial precision is calculated, the main control chip set comprises a main processor and a subsidiary processor, communication interfaces with multiple types are extended through the main control chip set, and protocol conversion is conducted in software; the data treatment unit receives data transmitted by the main control chip set and achieves and conducts treatment. According to the universal inertial data processing system based on the uniform interface, multiple inertial test interfaces are integrated, multi-interface inertial data is unified into Ethernet output, multiple communication protocols are compatible, and multiple types of inertial test requirements are met.
Description
Technical field
The invention belongs to a used group test equipment field, more particularly, to a kind of universal used group based on unified interface
Data handling system, it is adaptable to which directly pulse output, universal synchronous output, asynchronous serial port output, CAN output, 1553B are total
The data acquisition and process of most of used group such as line output.
Background technology
Tank-type mixture (hereinafter referred to as " used group ") is the core component of missile control system, is fastened with screw after used group of upper bullet
In the instrument room of guided missile, the precision and stability of the directly flight attitude and the speed of service of sensitivity body, therefore used group is direct
Have influence on the flight precision of guided missile.
Used group tester is the important component part of used group test system.The effect of tester is to receive used group data, right
Used group data are resolved and are calculated used group precision parameter, so the Stability and veracity of ground test parameter is to affect used group
The key of final guidance precision.
Because model is various, used group of data output form of company's production presents diversified development trend, and existing
Used group test equipment also relies on a kind of test equipment based on isa bus, and the test equipment by test board by inserting in industry control
The test and data that 12 road pulse signals are completed in machine isa bus draw-in groove is calculated.But the equipment has following defect：
(1) test equipment is developed the nineties, can be only done used group of data acquisition of output of pulse signal, and for it
Used group of data of his form output board that needs to transfer converts the data into pulse signal and is acquired；
(2) temperature data acquisition of used group plus table and gyro cannot be realized；
(3) monitoring to being used to group electric power system cannot be realized；
(4) acquisition software can only be run under WIN98 operating systems, it is impossible to upgraded；
(5) volume is big, non-portable cabinet.
The disadvantages described above of former test equipment, causes the used group test of company to need continuous brand-new switching board, high cost, and utilizes
Rate is poor, precise decreasing after conversion, affects measuring accuracy.
The content of the invention
For the disadvantages described above or Improvement requirement of prior art, the invention provides a kind of used group of number based on unified interface
According to processing system, by the way that data processing unit, measurement and control unit, power supply and power supply monitoring unit are integrated in together into integration
In cabinet, poor pulse test equipment interoperability, insufficiency, technical problem inconvenient to carry are thus solved.
For achieving the above object, according to one aspect of the present invention, there is provided a kind of based on the universal used of unified interface
Group data handling system, it is characterised in that the data handling system includes pulse acquisition circuit, communication interface circuit, master control core
Piece group, data processing unit,
Wherein described pulse acquisition circuit, through signal processing circuit pulse signals carry out pretreatment be transmitted in it is described
CPLD circuit carries out used group Multichannel Acceleration meter and the positive and negative channel pulse of multichannel gyroscope is counted；
The communication interface circuit is realized and the main control chip group between with the used group data of bus form input and output；
The platinum resistance temperature Acquisition Circuit is by the measurement used group of Multichannel Acceleration meter and multichannel gyroscope and is used to
The temperature of body is organized to calculate compensating parameter required during used group precision.
The main control chip group is master and slave processor, and integrated various test interfaces realize the used group data of the plurality of type
Interface, the unification of multiple kinds；
The data processing unit receives the data of the main control chip group transmission and realizes and processed；
Wherein, transmitted using asynchronous serial port UART using the used group data of SPI communication transmission between the master and slave processor
Control command and status information, the tasks synchronization between double-core is controlled using external interrupt, to realize that diversiform data is adopted
Coordination between collection process.
Further, the primary processor communicates with the data processing unit, complete interface be uniformly controlled, agreement unification
Task scheduling between the collection of control, power supply, Power Supply Monitoring and multi-interface data；It is described to complete multiclass from processor
Type is used to the extension of group data acquisition interface and used group of data acquisition of multiplex roles.
Further, the coordination that the polymorphic type is used to group data acquisition is：Main control chip group from processor completes described
Used group of data are filled into transmission format protocol each field by a polymorphic type used group data acquisition, primary processor according to predetermined form
On, realize communications protocol formatting conversion, after transmit to the data processing unit, the data processing unit will be gathered
To used group of data parsed by message format, calculated, being processed a used group data.
Further, the master and slave processor is respectively STM32 family chips.
Further, wherein outside realizing Ethernet interface using the FMSC bus extensions of STM32 on the STM32 chips
Industry ethernet controller.
Further, platinum resistance temperature measuring circuit described in every road includes constant pressure source trilinear method bridge circuit, the signal of series connection
Modulate circuit and A/D converter circuit.
Further, the platinum resistance temperature Acquisition Circuit adopts constant pressure source trilinear method measuring method.
Further, the signal processing circuit includes bleeder circuit, Schmidt trigger and the level translator of series connection.
Further, the data handling system also include electric source monitoring circuit, using series connection solid-state relay and every
From amplifier, realize that multichannel is not used to the voltage acquisition monitoring of group secondary power supply altogether.
In general, by the contemplated above technical scheme of the present invention compared with prior art, can obtain down and show
Beneficial effect：
(1) various used group of test interface integrated first, is Ethernet output by the used group data unification of multiplex roles, compatible various
Communications protocol, a set of data acquisition system can meet the used group testing requirement of company's overwhelming majority；
(2) pulse data acquisition function is completed using PLD, compare former pulse collection systematic sampling scope,
Sampling precision improves more than 10 times, has the function that the sampling time can match somebody with somebody, the collection of positive and negative channel data is preserved concurrently；
(3) test system is controlled using double-core, the division of labor, cooperation, high with task-aware, execution efficiency between double-core
Feature, integration USB 2.0 and 10M/100M adaptive ethernets, possess big data bulk transfer ability, are provided simultaneously with using ether
The function of net online upgrading STM32 programs；
(4) integrated 9 road platinum resistance temperature Acquisition Circuit, using constant pressure source trilinear method measuring circuit to the internal RTD of used group
Temperature acquisition is carried out, acquisition precision is better than 0.1 DEG C, far above technical requirement；
(5) integrated used group of power supply, consumption current monitoring circuit, realize first voltage, electric current and monitor simultaneously, realize
The safe power supply of used set product；
(6) first in test equipment using database storage techniques, ordinary file storage, data base read-write speed are compared
Faster, security is higher, and memory capacity is bigger, and test data is realized first by minimum sampling period (10ms using database
Or per frame) sequential storage, during data exception, the moment of abnormal data generation can be positioned, the traceability of abnormal data is realized,
And member's pulse collection equipment can only be in backstage record second data；
(7) designed using Portable integral, it is integrated automatically with power-off and power supply monitoring system, 1553B bus couplings
Clutch and data processing and data acquisition, greatly reduce equipment cost and volume.
Description of the drawings
Fig. 1 is the universal used group of data collecting system overall structure block schematic illustration realized according to the present invention；
Fig. 2 is the module group composition structural representation of the signal conditioning circuit in the data collecting system realized according to the present invention
Figure；
Fig. 3 is the system composition connection diagram of the platinum resistance temperature measuring circuit realized according to the present invention；
Fig. 4 is the concrete composition structural representation of the platinum resistance temperature measuring circuit realized according to the present invention；
Fig. 5 is the control planning schematic diagram of the double-core circuit realized according to the present invention；
Fig. 6 is the STM32 double-core control circuit works in the universal used group of data collecting system realized according to the present invention
Make schematic flow sheet.
Specific embodiment
In order that the objects, technical solutions and advantages of the present invention become more apparent, below in conjunction with drawings and Examples,
The present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only to explain the present invention,
It is not intended to limit the present invention.Additionally, technical characteristic involved in invention described below each embodiment is only
Not constitute conflict each other just can be mutually combined.
The scheme that the present invention takes is：A kind of used group of universal data collecting system based on unified interface.Core circuit is adopted
With double-core STM32 control circuits, peripheral interface circuit includes that pulse acquisition circuit, synchronous serial communication interface circuit, 1553B are total
Line communication interface circuit, platinum resistance temperature measuring circuit, RS422 bus communication interface circuits, CAN communication interface circuit,
CPLD circuit, high speed USB serial bus communication interfaces circuit, Ethernet ethernet communication control circuits, used group power supply and prison
Slowdown monitoring circuit, voltage detecting circuit, data processing unit.
Double-core STM32 control circuits realize various data-interfaces, multiple kinds to single interface, the unification of single agreement.
Two panels STM32 point is main (Master), from (Slave) processor, different functions are realized respectively, primary processor mainly completes to connect
Mouth is unified, the task scheduling between agreement unification, system power supply control, Power Supply Monitoring and multi-interface data collection；From process
Device mainly completes the extension of used group data acquisition interface, enables the data acquisition session for adapting to multiplex roles.Master and slave processor
Between using the used group data of SPI communication transmission, control command and status information, the tasks synchronization between double-core are transmitted using UART
It is controlled using 4 tunnel external interrupts Ext [3: 0], realizes coordination, the unification between each data acquisition session.
Pulse acquisition circuit is made up of pulse shaper and CPLD programmable logic device internal calculators, is used to group pulse defeated
Enter and enter after pulse shaper CPLD, CPLD is counted to the pulse being input into, and CPLD and STM32 is carried out using FSMC buses
Connection simultaneously reads the counted number of pulses of CPLD by FSMC buses.
Synchronous communication control circuit is extended by the FSMC buses of STM32, and synchronous communication controller is PEF20525,
Two-way full duplex synchronous serial communication is realized by PEF20525, communication baud rate may be programmed, and maximum rate is 20Mbps.
1553B bus communication interfaces circuit is extended by the FSMC buses of STM32, communication controller be 8357
HT-61843GB-1, the communication interface is integrated in used group test equipment first, and its communication baud rate is 4Mbps.
Platinum resistance temperature measuring circuit adopts constant pressure source three-wire system mensuration, can be prevented effectively from because of wire heat using the method
Grass carrys out measure error, is to reduce the spontaneous heat affecting temperature measurement accuracy of product RTD, and measurement electric current is less than 0.4mA,
Wherein electric bridge is built using high accuracy, Low Drift Temperature resistance, further reduces measure error, and Surveying Actual Precision is better than 0.1 DEG C；
The communication controller that RS422 bus communication interfaces circuit and CAN communication interface circuit are carried using STM32
Connection transceiving driver is constituted, and realizes the used group of data acquisition with the output of RS422 buses or CAN output.
High speed USB serial bus communication interfaces circuit connects outside PHY using the USB_OTG HS interfaces of STM32
USB3300, USB interface is the backup interface of the data transfer of Ethernet, for the bulk transfer of big data, through actually testing
Card, USB_OTG high-speed interface the maximum data transfer rates have reached 430Mbps, far above STM32 Ethernet interface highests
The restriction of 100Mbps, can be used for the non real-time bulk transfer of big data.
Ethernet ethernet communications control circuit is expanded using the FSMC buses connection ethernet controller of STM32
Exhibition, ethernet communication controller is DM9000A, is mainly used in the used group data of real-time Transmission, by transplanting LwIP agreements on software
Stack, realizes the function of Ethernet data transmission.
Used group electric source monitoring circuit by on-off circuit and relay circuit, realize it is manual/auto with electric control switching, and
Maximum current is 20A, using ACS754LCB current sensors, can the used group of real-time monitoring consume a curent change, when electric current exceed it is pre-
If being reported to the police during value, the safe power supply to being used to group is realized.
Voltage detecting circuit wherein in observation circuit is using solid-state relay JGC-3032 and isolated amplifier
ISO124U, realizes that the voltage acquisition of group secondary power supply, the used group internal electric source situation of monitor in real time, using computing are not used in 5 tunnels altogether
Amplifier OPA2277, constitutes add circuit, and negative voltage is raised to into positive voltage, and the AD for realizing right ± 35V voltage wide-voltage ranges is adopted
Collection.
Data processing unit 13 is built using AIM-203 (Min_ATX) mainboard for grinding China, and the mainboard small volume is low in energy consumption,
And industrial rich interface, by writing software in data processing unit, used group pulse output collection can be flexibly realized, and carry out phase
Process, data storage etc. should be calculated.
Data acquisition system software is divided into data processing unit data processing software, double-core ARM control softwares, CPLD can
Programmed logic software；All softwares are designed by module, maintainable good, and extended capability and upgrading ability are strong, are used to group number
According to database purchase, management is adopted first, compare and use document storage mode, with read or write speed is fast, memory capacity big, safety
The features such as property is high.
Fig. 1 is a kind of system block diagram of pulse collection system of one embodiment of the invention, as shown in figure 1, including pulse
Acquisition Circuit 1, synchronous serial communication interface circuit 2,1553B bus communication interfaces circuit 3, platinum resistance temperature measuring circuit 4,
RS422 bus communication interfaces circuit 5, CAN communication interface circuit 6, CPLD circuit 7, main control chip group 8, high speed USB serial
Bus communication interface circuit 9, Ethernet ethernet communications control circuit 10, electric source monitoring circuit 11, data processing unit 12,
Power panel 13.
As shown in Fig. 2 used group pulse collection is made up of two parts, a part is physical circuit, i.e., at pulse collection signal
Reason circuit, another part is CPLD internal pulses logical circuit of counter circuits.
Pulse signal is reduced the pulse signal Jing bleeder circuits of used group of input by 12V by pulse collection signal processing circuit
To 5V or so, and after Schmitt trigger pulse signals carry out shaping, filtering, then change 5V through level translator
To be input to after 3.3V on the programmable timer outside input capture pin for extending to device CPLD and STM32, both can use
The timer collection of STM32 processors, it is also possible to be acquired using CPLD, reduce conceptual design risk.In the system number
According in acquisition scheme used group input pulse signal is acquired using CPLD, is compared using STM32 timer acquisition pulse numbers
For,
CPLD internal pulses logical circuit of counter electricity is programmed using Verilog FPGA language, CPLD internal logics
Circuit includes 4 modules, is respectively that frequency division module, counting module, output selecting module and output enable module.CPLD with
The data interaction of STM32 is completed by the FSMC buses of STM32, and frequency division module is mainly posted according to the sample frequency of FSMC writes
The storage completion system time divides.It is subsynchronous different to solve that counting module carries out 2 according to system clock to the pulse signal being input into
Step input interface cross clock domain stationary problem, and determine whether that pulse is come according to the rising edge of system clock, if there is pulse
Come in, complete addition and work, automatic clear after data spilling, when output enable signal is effective, CPLD is fixed according to sample frequency
When output pulse signal trigger STM32 external interrupt, STM32 in external interrupt by FSMC buses read CPLD pulse
Count value, during reading data, CPLD enters row decoding using the address date of FSMC, after address signal is effective, according to
Different address signals is put into the pulse data of different passages on the data wire of FSMC, completes whole step-by-step counting function.
The pulse acquisition circuit realized using Verilog is synchronized by clock synchronization mode to input pulse signal,
The synchronous technological difficulties of asynchronous input interface cross clock domain are solved, latch is with according to sampling parameter configurable clock generator divide ratio
And interrupt output frequency, realize sample frequency can Configuration Online and interrupt output High-Accuracy Frequency it is controllable.By test
Checking, the sampling precision of the pulse acquisition circuit can reach 10-6, and sample range can reach 6.5MHz, compare former pulse collection
Equipment, sampling precision improves an order of magnitude, and sample range expands 10 times.
Synchronous serial communication interface circuit 2 is extended using synchronous serial communication controller PEF20525, Communication Control
Device PEF20525 is connected with STM32 using FSMC bus parallels, and STM32 passes through FSMC bus configuration synchronous serial communication controllers
PEF20525, realize communication frequency can Configuration Online, highest communication baud rate up to 20Mbps, due to synchronous serial communication it is logical
Oversampling clock is synchronized to data-signal, has higher reliability than asynchronous serial communication, while using difference RS422 level
Transmission means, is capable of achieving remote, high reliability transport；
1553B bus communication interfaces circuit by 8357 1553B controllers HT-61843GB-1 and 1553B isolation transformation
Device HT-DB337/4A is constituted, and is attached using FSMC buses between HT-61843GB-1 and STM32.HT-61843GB-1 is total
Lane controller communication speed is 4Mbps, and for comparing the common 1Mbps communication baud rates of external import chip, traffic rate is carried
It is high 4 times.The communication controller supports binary channels, the bus links structure of dual redundant, realizes the high reliability of used group data
Transmission.
As shown in figure 3, platinum resistance temperature Acquisition Circuit adopts constant pressure source trilinear method measuring method, due to having in the used group of optical fiber
9 road RTDs need measurement, and the separate RTD Acquisition Circuit in 10 tunnels is integrated with the present system, wherein being used to supervise all the way
Control data collecting system temperature.Platinum resistance temperature measuring circuit is made up of 3 parts, be respectively constant pressure source trilinear method bridge circuit,
Signal conditioning circuit, ADS1258 high-precision AD change-over circuits.Wherein ADS1258 is connected to the SPI interface of STM32 (Slave)
On, ADS1258 sampling time sequences are controlled by SPI interface.Platinum resistance temperature collection particular hardware structural circuit as shown in Figure 4
In, R1, R2, R3, R4 constitute bridge circuit in electric bridge, and wherein Rw1～Rw3 is the lead wire circuit that electric bridge connects RTD, works as electricity
When bridge is balanced, Vin1 is equal with Vin2, and when bridge balance is broken, the difference between V1 and V2 is as shown in Equation 1
In bridge circuit, resistance R1～R3 should be produced with the resistance of R2 from high accuracy, the resistance of Low Drift Temperature, and R1 at same batch
From the resistance that drift bearing is consistent in product, because resistance R4 is with temperature change, R4=R0+ △ R are made, conductor resistance is due to warm
The impact of potential, resistance Rw has a small change, due to wire 1,2,3 it is isometric, it is believed that Rw1=Rw2=Rw3=r+
△ r, according to the wire of 2 meters of long AFR-2500.2, then r is about 0.2 Ω, and bringing R4, Rw1, Rw2, Rw3 into formula 1 can obtain
It is two parts as shown in formula 3, formula 4 by 2 points of formula：
Part I：
Part II：
Part I formula 3 is carried out arranging can be obtained
As shown in Equation 5, molecular moiety is without Δ r, denominator Section 1 (R1+R0+ΔR+r)×(R2+R3+ r) it is 108 magnitudes, point
Female Section 2 (R0+ΔR+r+R1+R2+R3+ r) × Δ r is 103Magnitude, denominator Section 3 Δ r210-2Magnitude, denominator Section 2
10 are differed with Section 15The individual order of magnitude, Section 3 is less, therefore denominator the 2nd, Section 3 are negligible.
In the case where reference voltage is 2.5V, VGND is as shown in Equation 6, by R1=R2=10K, R3=500 Ω, Rw1=
Rw2=Rw3Bring that formula 6 can be obtained and both sides are simultaneously divided by V intorefCan obtain
Therefore, Section 2 is negligible, and is understood according to the analysis of 2～formula of formula 7, the such as institute of formula 8 of the difference between V1 and V2
Show.Rt=R0+ △ R are made, then RTD resistance Rt can be obtained to the further deformation of formula 8 as shown in Equation 9.
Due to the lead resistance of wire it is very little, about 0.2 Ω, therefore the impact of conductor resistance can be ignored, then formula (9)
It is rewritable to be
This programme RTD design actual measurement range is -40 DEG C～100 DEG C, now the corresponding resistance point of RTD
400 Ω～700 Ω are not about for scope, now can be obtained according to formula 8, take VrefFor 2.5V, then when temperature is -40 DEG C, (resistance is
About 400 Ω) when Vin1-Vin2 obtain minimum of a value；When temperature is 100 DEG C, Vin1-Vin2 takes when (resistance is about 700 Ω)
Obtain maximum.
Bringing the value in formula (11) into formula (9), (10) respectively can show that value remains into after decimal point 5 and is
692.24877, as long as therefore connect RTD conductor length it is consistent, the error that conductor resistance causes is negligible.
According to formula (11) and the result of calculation of formula (12), the voltage difference minimum of a value at electric bridge two ends is -22.8929mV, maximum
Be worth for 44.5021mV, for ease of signals collecting, will electric bridge two ends voltage difference amplify 20 times after carry out sending into AD conversion chip
It is acquired, as shown in Figure 4, signal amplification circuit is divided into 2 grades to signal amplification circuit, and the first order forms ratio in the same direction by U1, U2
Example amplifying circuit, thus input impedance is very high, due to using symmetrical connected mode, thus can offset the temperature drift of operational amplifier
Phenomenon；Second level U3 connects into Differential Input mode, the single-ended signal output that differential signal is converted into.
Temperature collection circuit obtains the certainty of measurement better than 0.1 DEG C through actual verification, and this exists with theoretical calculation
Part variation, the main error and temperature drift by bridge circuit precision resistance of these differences, RTD cause from heat affecting, but
0.1 DEG C of certainty of measurement is considerably beyond 0.7 DEG C of certainty of measurement technical requirements required by the system.
Universal asynchronous RS422, RS232 serial communication circuit (5) and CAN communicating circuit (6) are carried using STM32
Communication interface connect corresponding transceiving driver and be extended, realize that principle is simpler, will not be described here.
As shown in figure 5, STM32 Dual-Core Communication control circuits are the cores of data acquisition system, two panels STM32 point is main
(Master), from (Slave) processor, different functions are realized respectively, primary processor mainly completes interface unification, agreement system
First, the task scheduling between system power supply control, Power Supply Monitoring and multi-interface data collection；Used group is mainly completed from processor
The extension of data acquisition interface and used group of data acquisition of multiplex roles, two panels STM32 can be made entirely by way of sharing out the work and help one another
Data collecting system operational efficiency is high, data acquisition is more reliable and more stable, it is also possible to solve STM32 because pin multiplexing causes part
The situation that function cannot be used.The double-core control system of data acquisition system is passed using SPI transmission datas, UART asynchronous serial ports
Defeated control command, GPIO are responsible for the tasks synchronization between double-core.Used group of data between main control chip group are passed by SPI
Send, wherein STM32 decides transmitting terminal from the SPI interface of processor, the SPI interface of primary processor is done from receiving terminal, the communication of SPI
Baud rate is 42Mbps, is transmitted using DMA transfer mode.
During actually used, the master (Master) of main control chip group, from workflow such as Fig. 6 of (Slave) processor
It is shown.After system electrification, two tasks are started after master chip initialization external interface, a task is that system power supply monitoring is appointed
Business, another is test instruction monitor task, and wherein system power supply monitor task is a periodicity execution task, test instruction
Monitor task is a preemptive type task, in test instruction monitor task, once receive the test that upper computer software sends refer to
Order just will test instruction be forwarded to from processor, wherein test instruction include data collection type, corresponding physical interface and
The information such as sampling parameter；One is returned from after test interface of the processor according to test instruction initialization corresponding data acquisition tasks
Status information, host computer chooses whether to continue to test according to status information, if status information is correct, host computer sends to start and surveys
Examination instruction, monitors to start from processor to start by external interrupt after test starting command and tests in test instruction monitor task
Task；The used group of data for collecting are sent to into primary processor by SPI from processor, primary processor carries out the data for receiving
Format and data processing unit is sent to by Ethernet after conversion；Once test instruction monitoring unit detects stopping test referring to
Order, stops data acquisition by external interrupt triggering from processor immediately.
It is to complete the formatting conversion of multiple kinds that primary processor also has a key task, will be used to a group data and press
Consolidation form is transmitted to data processing unit by Ethernet, and Ethernet data host-host protocol is as shown in table 1.
Table 1
Receive and used group of data are filled in transmission format protocol each field according to predetermined form after used group data,
The process that herein description protocol is changed by taking the protocol format that CAN protocol conversion is same as an example, CAN message form and data
Transformat definition structure body is as shown in table 2.
Table 2
After the message that control and testing board Master receives CAN, by all data distributions in CAN message structure
Data fields in host-host protocol, the FrameType in host-host protocol represents type of message (such as CAN, RS422,1553B
Deng), wherein CAN message type is represented with 0x90, in conversion unit of protocol, the finger of a sensing Tanslate_Msg is stated first
Pin * m_Tanslate_Msg, and for its dynamic assigning memory, protocol conversion process is as follows, wherein host-host protocol frame head, verification and
Calculate and postamble is omitted and do not write.
More specifically, because the USB interface for carrying of STM32 only supports low speed and Full-Speed mode, but STM32 inside collection
Into the controller of hi-speed USB interface, it is necessary to the USB fast modes that could use STM32 using outside PHY, adopt in notebook data
In collecting system, the hi-speed USB interface of STM32 is extended as outside PHY using USB3300, USB interface is used as the standby of Ethernet
Interface is used for used group data transfer, and Jing actual transmissions test, its transmission speed can reach 430Mbps, have than Ethernet higher
Transfer rate, be adapted to big data bulk transfer.
More specifically, realize that Ethernet interface typically can be realized using two schemes on STM32, scheme one is to use
The RMII interface or the outside PHY of MII interfaces connection that STM32 is carried realizes Ethernet interface, and scheme two is to use FMSC bus extensions
External ethernet bus control unit.Ethernet interface circuit is total using FMSC bus extension Ethernets in data acquisition system
Lane controller DM9000A, DM9000A are integrated with ethernet controller and PHY, using more convenient, simply；By moving on software
Plant the data transfer that LwIP protocol stacks are realized between control and testing board and data processing unit.
More specifically, it is used to group power supply and observation circuit is made up of manual switch circuit and relay circuit, its breaker in middle
S1 is single-pole double-throw switch (SPDT), and for switching control manually or software control, switch S2 to S5, relay K1-K4 control respectively 4
The turn-on and turn-off of road+BB voltages.Passed by sealing in an ACS754LCB electric current from switch and relay+BB voltages out
Sensor, the output of ACS754LCB is connected to AD acquisition interfaces in dual core processor circuit (9), and the electric current of 4 tunnel+BB is supervised
Survey.
More specifically, anode and negative terminal are passed through solid-state by voltage detecting circuit, five road input voltages simultaneously after partial pressure
Relay is sequentially switched to the input of add circuit, and the output of add circuit as the input of ISO124 isolated amplifiers,
By isolated amplifier, the ground of tested voltage is converted to AD locality by realization, and the output end of ISO124 is connected to double-core process
AD acquisition interfaces in device circuit (9), realize that 5 tunnels are not total to ground voltage collection.
As it will be easily appreciated by one skilled in the art that the foregoing is only presently preferred embodiments of the present invention, not to
The present invention, all any modification, equivalent and improvement made within the spirit and principles in the present invention etc. are limited, all should be included
Within protection scope of the present invention.
Claims (9)
1. a kind of universal used group of data handling system based on unified interface, it is characterised in that the data handling system includes
Pulse acquisition circuit (1), communication interface circuit (2,3,5,6), main control chip group (8), data processing unit (12),
Wherein described pulse acquisition circuit (1), through signal processing circuit pulse signals carry out pretreatment be transmitted in it is described
CPLD circuit (7) carries out used group Multichannel Acceleration meter and the positive and negative channel pulse of multichannel gyroscope is counted；
The communication interface circuit (2,3,5,6) is realized used with bus form input and output between the main control chip group (8)
Group data；
The platinum resistance temperature Acquisition Circuit (4) is by measuring the used group of Multichannel Acceleration meter and multichannel gyroscope and used group
The temperature of body is calculating compensating parameter required during used group precision.
The main control chip group (8) is master and slave processor, and integrated various test interfaces realize the used group data of the plurality of type
Interface, the unification of multiple kinds；
The data processing unit (12) receives the data of main control chip group (8) transmission and realizes and processed；
Wherein, controlled using asynchronous serial port UART transmission using the used group data of SPI communication transmission between the master and slave processor
Order and status information, the tasks synchronization between double-core is controlled using external interrupt, to realize at diversiform data collection
Coordination between reason.
2. universal used group of data handling system of unified interface is based on as claimed in claim 1, it is characterised in that the master
Processor communicates with the data processing unit (12), completes that interface is uniformly controlled, agreement is uniformly controlled, power supply, power supply
Task scheduling between monitoring and multi-interface data collection；It is described to complete polymorphic type from processor and be used to group data acquisition interface
Extension and used group of data acquisition of multiplex roles.
3. universal used group of data handling system of unified interface is based on as claimed in claim 1 or 2, it is characterised in that institute
State polymorphic type and be used to the coordination of group data acquisition and be：Main control chip group from processor completes a polymorphic type used group data acquisition,
Primary processor is filled into used group of data in transmission format protocol each field according to predetermined form, realizes the lattice of communications protocol
Formulaization is changed, after transmit to the data processing unit (12), the data processing unit (12) is by the used group of number for being collected
It is used to group data according to being parsed by message format, being calculated, processed.
4. universal used group of data handling system of unified interface is based on as claimed in claim 3, it is characterised in that described
Master and slave processor is respectively STM32 family chips.
5. the universal used group of data handling system based on unified interface as claimed in claim 4, it is characterised in that wherein institute
State the FMSC bus extension external ethernet bus control units that Ethernet interface is realized on STM32 chips using STM32.
6. the universal used group of data handling system based on unified interface as described in any one in claim 1-5, it is special
Levy and be, include per platinum resistance temperature measuring circuit described in road the constant pressure source trilinear method bridge circuit of series connection, signal conditioning circuit and
A/D converter circuit.
7. universal used group of data handling system of unified interface is based on as claimed in claim 6, it is characterised in that the platinum
Resistance temperature Acquisition Circuit adopts constant pressure source trilinear method measuring method.
8. universal used group of data handling system of unified interface is based on as claimed in claim 7, it is characterised in that the letter
Number process circuit includes bleeder circuit, Schmidt trigger and the level translator of series connection.
9. universal used group of data handling system of unified interface is based on as claimed in claim 8, it is characterised in that the number
Also include electric source monitoring circuit (11) according to processing system, using the solid-state relay and isolated amplifier of series connection, realize multichannel not
It is used to the voltage acquisition monitoring of group secondary power supply altogether.
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| CN108924027A (en) * | 2018-09-19 | 2018-11-30 | 武汉库迪智能技术有限公司 | A kind of EtherCAT main station controller based on ARM kernel |
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| CN109684251A (en) * | 2019-01-11 | 2019-04-26 | 杭州万高科技股份有限公司 | A kind of processing method of chip I/O data and a kind of chip |
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| CN113268100A (en) * | 2021-04-29 | 2021-08-17 | 中科慧远视觉技术(北京)有限公司 | Single-port multi-level input-output circuit and method |
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| CN115599722A (en) * | 2022-12-15 | 2023-01-13 | 深圳市欧瑞博科技股份有限公司（Cn） | Method and device for realizing accurate transmission of serial port data based on operating system kernel |
| CN117074825A (en) * | 2023-08-17 | 2023-11-17 | 昆山迈致治具科技有限公司 | Integrated function test system and method |
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| CN117033278A (en) * | 2023-10-08 | 2023-11-10 | 北京云成金融信息服务有限公司 | Data transmission method and system for multiple types of interfaces |
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