CN202795117U

CN202795117U - Voltage regulator circuit

Info

Publication number: CN202795117U
Application number: CN 201220508503
Authority: CN
Inventors: 吴勇; 王纪云; 王晓娟
Original assignee: Zhengzhou Dandian Technology Software Co Ltd
Current assignee: Zhengzhou Dandian Technology Software Co Ltd
Priority date: 2012-10-03
Filing date: 2012-10-03
Publication date: 2013-03-13
Anticipated expiration: 2022-10-03

Abstract

The utility model discloses a voltage regulator circuit. According to the circuit, a source electrode of a first P-channel metal oxide semiconductor (PMOS) transistor is connected with a voltage source, a grid electrode of the first PMOS transistor is connected with a drain electrode of a second N-channel metal oxide semiconductor (NMOS) transistor and a grid electrode and a drain electrode of a second PMOS transistor, a drain electrode of the first PMOS transistor is connected with a drain electrode of a first NMOS transistor and a grid electrode of a third PMOS transistor, a source electrode of the second PMOS transistor is connected with a voltage source, a source electrode of the third PMOS transistor is connected with the voltage source, a drain electrode of the third PMOS transistor is connected with a drain electrode of a third NMOS transistor and a voltage output end, a grid electrode of the first NMOS transistor is connected with a reference voltage input end, a source electrode of the first NMOS transistor is connected with a drain electrode of a fourth NMOS transistor and a source electrode of the second NMOS transistor, a grid electrode of the second NMOS transistor is connected with the voltage output end and ground respectively through a first resistor and a second resistor, grid electrodes of the third NMOS transistor and the fourth NMOS transistor are connected with a voltage input end, and source electrodes of the third NMOS transistor and the fourth NMOS transistor are grounded. The voltage regulator circuit has the advantages of being small in size, low in power consumption, high in speed, suitable for integration and simple in circuit structure.

Description

Regulating circuit

Technical field

The utility model relates to a kind of regulating circuit.

Background technology

Pressure regulation is the circuit module of often using in the circuit, is used for Circuit tuning function voltage.Generally adopt thyristor as the part of pressure regulation in the available circuit, but the area of thyristor is larger, it is larger to generate heat, and the power of consumption is also larger, is not applicable to integrated circuit, generally is at the external regulating circuit of chip.

The utility model content

Goal of the invention of the present utility model is: for the problem of above-mentioned existence, provide a kind of regulating circuit of MOS structure.

The technical solution adopted in the utility model is such: a kind of regulating circuit, this circuit comprise a PMOS transistor, the 2nd PMOS transistor, the 3rd PMOS transistor, the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the first resistance and the second resistance.

The transistorized source electrode of a described PMOS is connected to voltage source, and grid is connected to drain electrode, the transistorized grid of the 2nd PMOS and the drain electrode of the second nmos pass transistor, and drain electrode is connected to drain electrode and the transistorized grid of the 3rd PMOS of the first nmos pass transistor; The transistorized source electrode of described the 2nd PMOS is connected to voltage source; The transistorized source electrode of described the 3rd PMOS is connected to voltage source, and drain electrode is connected to drain electrode, the voltage output end of the 3rd nmos pass transistor; The grid of described the first nmos pass transistor is connected to reference voltage input terminal, and source electrode is connected to the drain electrode of the 4th nmos pass transistor and the source electrode of the second nmos pass transistor; The grid of described the second nmos pass transistor is connected to voltage output end and ground by the first resistance and the second resistance respectively; The grid of the grid of described the 3rd nmos pass transistor and the 4th nmos pass transistor all is connected to voltage input end, the source grounding of the source electrode of the 3rd nmos pass transistor and the 4th nmos pass transistor.

In above-mentioned circuit, a described PMOS transistor, the 2nd PMOS transistor and the 3rd PMOS transistor are the identical PMOS transistor of parameter.

In above-mentioned circuit, described the first nmos pass transistor, the second nmos pass transistor and the 3rd nmos pass transistor are the identical nmos pass transistor of parameter.

In above-mentioned circuit, described the first resistance is the identical resistance of parameter with the second resistance.

In sum, owing to adopted technique scheme, the beneficial effects of the utility model are: adopt the MOS structure, because the metal-oxide-semiconductor body is less, power consumption is little, speed is high, it is integrated to be applicable to, it is simple to cut circuit structure.

Description of drawings

Fig. 1 is the circuit theory diagrams of the utility model regulating circuit.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in detail.

In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.

As shown in Figure 1, be the circuit theory diagrams of the utility model regulating circuit.

A kind of regulating circuit comprises a PMOS transistor P1, the 2nd PMOS transistor P2, the 3rd PMOS transistor P3, the first nmos pass transistor N1, the second nmos pass transistor N2, the 3rd nmos pass transistor N3, the first resistance R 1 and the second resistance R 2.

Below in conjunction with Fig. 1 the annexation between above-mentioned each electronic devices and components of the utility model is elaborated: the source electrode of a described PMOS transistor P1 is connected to voltage source V DD, grid is connected to the drain electrode of the second nmos pass transistor N2, grid and the drain electrode of the 2nd PMOS transistor P2, and drain electrode is connected to the drain electrode of the first nmos pass transistor and the grid of the 3rd PMOS transistor P3; The source electrode of described the 2nd PMOS transistor P2 is connected to voltage source V DD; The source electrode of described the 3rd PMOS transistor P3 is connected to voltage source V DD, and drain electrode is connected to drain electrode, the voltage output end Vout of the 3rd nmos pass transistor N3; The grid of described the first nmos pass transistor N1 is connected to reference voltage input terminal Vref, and source electrode is connected to the drain electrode of the 4th nmos pass transistor N4 and the source electrode of the second nmos pass transistor N2; The grid of described the second nmos pass transistor N2 is connected to voltage output end Vout and ground by the first resistance R 1 and the second resistance R 2 respectively; The grid of the grid of described the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4 all is connected to voltage input end Vin, the source grounding of the source electrode of the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4.

In the above-mentioned circuit of the utility model, a described PMOS transistor P1, the 2nd PMOS transistor P2 are the identical PMOS transistor of parameter with the 3rd PMOS transistor P3.

In the above-mentioned circuit of the utility model, described the first nmos pass transistor N1, the second nmos pass transistor N2 are the identical nmos pass transistor of parameter with the 3rd nmos pass transistor N3.

In the above-mentioned circuit of the utility model, described the first resistance R 1 is the identical resistance of parameter with the second resistance R 2.

The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.

Claims

1. regulating circuit, it is characterized in that, comprise a PMOS transistor (P1), the 2nd PMOS transistor (P2), the 3rd PMOS transistor (P3), the first nmos pass transistor (N1), the second nmos pass transistor (N2), the 3rd nmos pass transistor (N3), the first resistance (R1) and the second resistance (R2);

The source electrode of a described PMOS transistor (P1) is connected to voltage source (VDD), grid is connected to the drain electrode of the second nmos pass transistor (N2), grid and the drain electrode of the 2nd PMOS transistor (P2), and drain electrode is connected to the drain electrode of the first nmos pass transistor and the grid of the 3rd PMOS transistor (P3); The source electrode of described the 2nd PMOS transistor (P2) is connected to voltage source (VDD); The source electrode of described the 3rd PMOS transistor (P3) is connected to voltage source (VDD), and drain electrode is connected to drain electrode, the voltage output end (Vout) of the 3rd nmos pass transistor (N3); The grid of described the first nmos pass transistor (N1) is connected to reference voltage input terminal (Vref), and source electrode is connected to the drain electrode of the 4th nmos pass transistor (N4) and the source electrode of the second nmos pass transistor (N2); The grid of described the second nmos pass transistor (N2) is connected to voltage output end (Vout) and ground by the first resistance (R1) and the second resistance (R2) respectively; The grid of the grid of described the 3rd nmos pass transistor (N3) and the 4th nmos pass transistor (N4) all is connected to voltage input end (Vin), the source grounding of the source electrode of the 3rd nmos pass transistor (N3) and the 4th nmos pass transistor (N4).

2. regulating circuit according to claim 1 is characterized in that, a described PMOS transistor (P1), the 2nd PMOS transistor (P2) and the 3rd PMOS transistor (P3) are the identical PMOS transistor of parameter.

3. regulating circuit according to claim 1 is characterized in that, described the first nmos pass transistor (N1), the second nmos pass transistor (N2) and the 3rd nmos pass transistor (N3) are the identical nmos pass transistor of parameter.

4. regulating circuit according to claim 1 is characterized in that, described the first resistance (R1) is the identical resistance of parameter with the second resistance (R2).