CN202795118U - Voltage regulator circuit - Google Patents

Voltage regulator circuit Download PDF

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Publication number
CN202795118U
CN202795118U CN 201220509019 CN201220509019U CN202795118U CN 202795118 U CN202795118 U CN 202795118U CN 201220509019 CN201220509019 CN 201220509019 CN 201220509019 U CN201220509019 U CN 201220509019U CN 202795118 U CN202795118 U CN 202795118U
Authority
CN
China
Prior art keywords
resistance
pass transistor
nmos pass
nmos transistor
barrier diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 201220509019
Other languages
Chinese (zh)
Inventor
周晓东
王晓娟
王纪云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhengzhou Dandian Technology Software Co Ltd
Original Assignee
Zhengzhou Dandian Technology Software Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhengzhou Dandian Technology Software Co Ltd filed Critical Zhengzhou Dandian Technology Software Co Ltd
Priority to CN 201220509019 priority Critical patent/CN202795118U/en
Application granted granted Critical
Publication of CN202795118U publication Critical patent/CN202795118U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model discloses a voltage regulator circuit. The voltage regulator circuit comprises a first N-channel metal oxide semiconductor (NMOS) transistor, a second NMOS transistor, a first resistor, a second resistor, an adjustable resistor and a schottky barrier diode, a grid electrode of the first NMOS transistor is connected to an voltage source through the first resistor and grounded through the adjustable resistor, a source electrode of the first NMOS transistor is grounded, a drain electrode of the first NMOS transistor is connected to a negative electrode end of the schottky barrier diode and a grid electrode of the second NMOS transistor and connected to the voltage source through the second resistor, a positive electrode end of the schottky barrier diode is grounded, a source electrode of the second NMOS transistor is grounded, and a drain electrode of the second NMOS transistor serves as an negative electrode of an output end. The voltage regulator circuit has the advantages of being small in size, low in power consumption, high in speed, suitable for integration and simple in circuit structure.

Description

Regulating circuit
Technical field
The utility model relates to a kind of regulating circuit.
Background technology
Pressure regulation is the circuit module of often using in the circuit, is used for Circuit tuning function voltage.Generally adopt thyristor as the part of pressure regulation in the available circuit, but the area of thyristor is larger, it is larger to generate heat, and the power of consumption is also larger, is not applicable to integrated circuit, generally is at the external regulating circuit of chip.
The utility model content
Goal of the invention of the present utility model is: for the problem of above-mentioned existence, provide a kind of regulating circuit of MOS structure.
The technical solution adopted in the utility model is such: a kind of regulating circuit of the present utility model, this circuit comprise the first nmos pass transistor, the second nmos pass transistor, the first resistance, the second resistance, adjustable resistance and Schottky-barrier diode; The grid of described the first nmos pass transistor is connected to voltage source and is connected to ground by adjustable resistance by the first resistance, source ground, drain electrode be connected to Schottky-barrier diode negative pole end, the second nmos pass transistor grid and be connected to voltage source by the second resistance; The positive terminal ground connection of Schottky-barrier diode; The source ground of the second nmos pass transistor, drain electrode is as the negative pole of output terminal.Small volume, power consumption is little, speed is high, it is integrated to be applicable to, and circuit structure is simple.
In above-mentioned circuit, described the first nmos pass transistor is the identical nmos pass transistor of parameter with the second nmos pass transistor.
In above-mentioned circuit, described the first resistance is the identical resistance of parameter with the second resistance.
In sum, owing to adopted technique scheme, the beneficial effects of the utility model are: this circuit body is less, power consumption is little, speed is high, it is integrated to be applicable to, and circuit structure is simple.
Description of drawings
Fig. 1 is the circuit theory diagrams of the utility model regulating circuit.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in detail.
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
As shown in Figure 1, be the circuit theory diagrams of the utility model regulating circuit.
Below in conjunction with Fig. 1 the annexation between above-mentioned each electronic devices and components of the utility model is elaborated: a kind of regulating circuit, this circuit comprise the first nmos pass transistor Q1, the second nmos pass transistor Q2, the first resistance R 1, the second resistance R 2, adjustable resistance RW1 and Schottky-barrier diode Z1; The grid of described the first nmos pass transistor Q1 is connected to voltage source V DD and is connected to ground GND by adjustable resistance RW1 by the first resistance R 1, source ground GND, drain electrode be connected to Schottky-barrier diode Z1 negative pole end, the second nmos pass transistor Q2 grid and be connected to voltage source V DD by the second resistance R 2; The positive terminal ground connection of Schottky-barrier diode Z1; The source ground GND of the second nmos pass transistor Q2, drain electrode is as the negative pole of output end vo ut.
In the above-mentioned circuit of the utility model, described the first nmos pass transistor Q1 is the identical nmos pass transistor of parameter with the second nmos pass transistor Q2.
In the above-mentioned circuit of the utility model, described the first resistance R 1 is the identical resistance of parameter with the second resistance R 2.
The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.

Claims (3)

1. a regulating circuit is characterized in that, comprises the first nmos pass transistor (Q1), the second nmos pass transistor (Q2), the first resistance (R1), the second resistance (R2), adjustable resistance (RW1) and Schottky-barrier diode (Z1); The grid of described the first nmos pass transistor (Q1) is connected to voltage source (VDD) and is connected to ground (GND) by adjustable resistance (RW1) by the first resistance (R1), source ground (GND), drain electrode be connected to Schottky-barrier diode (Z1) negative pole end, the second nmos pass transistor (Q2) grid and be connected to voltage source (VDD) by the second resistance (R2); The positive terminal ground connection of Schottky-barrier diode (Z1); The source ground (GND) of the second nmos pass transistor (Q2), drain electrode is as the negative pole of output terminal (Vout).
2. regulating circuit according to claim 1 is characterized in that, described the first nmos pass transistor (Q1) is the identical nmos pass transistor of parameter with the second nmos pass transistor (Q2).
3. regulating circuit according to claim 1 is characterized in that, described the first resistance (R1) is the identical resistance of parameter with the second resistance (R2).
CN 201220509019 2012-10-07 2012-10-07 Voltage regulator circuit Expired - Fee Related CN202795118U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201220509019 CN202795118U (en) 2012-10-07 2012-10-07 Voltage regulator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201220509019 CN202795118U (en) 2012-10-07 2012-10-07 Voltage regulator circuit

Publications (1)

Publication Number Publication Date
CN202795118U true CN202795118U (en) 2013-03-13

Family

ID=47822352

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201220509019 Expired - Fee Related CN202795118U (en) 2012-10-07 2012-10-07 Voltage regulator circuit

Country Status (1)

Country Link
CN (1) CN202795118U (en)

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130313

Termination date: 20131007